[Solved] Swconfig router and switch gl.inet ar150


#1

Hi trying to figure out how my Gl.inet Ar150 Atheros Soc9331 is working:

if I type: swconfig list

i get: found switch0 -eth1

but my mini router has only one radio, one wan port and one lan port.

if I type: swconfig dev eth1 help

I get:switch0 eth1(Ar7240/AR9330 built in switch), ports:5 (cpu@0), vlans: 16

I don t understand what this switch is ? wikipage https://wikidevi.com/wiki/Atheros_AR9331

doesn t say anything under switch column for ar150 probably because is built in ??

In any case if I type: swconfig dev eth1 show

I get:

Global attributes:
enable_vlan: 0
mirror_monitor_port: 15
Port 0:
enable_mirror_rx: 0
enable_mirror_tx: 0
pvid: 0
link: port:0 link:up speed:1000baseT full-duplex txflow rxflow
Port 1:
enable_mirror_rx: 0
enable_mirror_tx: 0
pvid: 0
link: port:1 link:down
Port 2:
enable_mirror_rx: 0
enable_mirror_tx: 0
pvid: 0
link: port:2 link:down
Port 3:
enable_mirror_rx: 0
enable_mirror_tx: 0
pvid: 0
link: port:3 link:down
Port 4:
enable_mirror_rx: 0
enable_mirror_tx: 0
pvid: 0
link: port:4 link:down
VLAN 0:
vid: 0
ports: 0 1 2 3 4

and if I type: swconfig dev eth1 por 15 show

I get:

Port 15:
             enable_mirror_rx: ???
             enable_mirror_tx ???
             pvid: ???
             link: ???

I am missing the logic of all this of course my /rtc/config/network doesnt have any line about a switch.

What is the globals setting ??

Please point me toward an explanation of switch or better easy to understand router architecture,

what I cant really find difficult to cope with is Port 15 when the swconfig dev eth1 help says:

switch0 eth1(Ar7240/AR9330 built in switch), ports:5 (cpu@0), vlans: 16

Thanks in advance for your patience.

Bests

P.


Where is the switch option menú on OpenWrt 18.06.1?
Swconfig versus etc/config/network
Add new init_setup for existing target board/router
Swconfig versus etc/config/network
#2

In a typical router configuration, there need to be two Ethernet interfaces, one for "WAN" and one for "LAN".

When devices have only a single phy (typically older or less expensive devices), OpenWrt generally accomplished this by using VLAN-tagged interfaces on the single phy. The switch then can use the VLAN tag to internally "wire" one to the WAN interface, and the other to one or more "LAN" ports.

A typical configuration might look like:

  • Port 0 -- electrically attached to eth0 on the SoC
  • Port 1 -- electrically attached to the "WAN" socket
  • Ports 2-5 -- electrically attached to the four "LAN" sockets

The the switch is used to internally "wire" those ports together

  • Port 0 -- VLAN 1, tagged; VLAN 2, tagged; PVID "blackhole" -- keep tagging so that eth0 can "split" WAN from LAN traffic. PVID should prohibit traffic as eth0 should only be sending and responding to tagged packets from/to eth0.1 or eth0.2
  • Port 1 -- VLAN 1, untagged; PVID 1 -- packets in the switch that are tagged VLAN 1 get sent out the WAN socket without a tag; packets coming in get tagged with VLAN 1
  • Ports 2-5 -- VLAN 2, untagged; PVID 2 -- packets in the switch that are tagged VLAN 2 get sent out the LAN sockets without a tag; packets coming in get tagged with VLAN 2

On your device

switch0 eth1(Ar7240/AR9330 built in switch), ports:5 (cpu@0), vlans: 16

says that the built-in switch has 5 total ports and that the VLAN table can have 16 entries.

You can use VLAN tags 1-15 without "fancy" UCI configuration. If you want to use a VLAN tag higher than 15, you'll need to explicitly set the VLAN ID and PVID in your /etc/config/network

As an example, here is how I would configure VLAN tag 1000 to connect a phy configured for VLAN tag 1000, connected to switch port 6, to send and receive VLAN-tagged packets over switch port 1.

config switch_vlan
        option device 'switch0'
        option vlan '4'
        option vid '1000'
        option ports '6t 1t'

My recollection is that when setting the PVID for a port, you need to specify it by the table-entry number that is associated with the actual tag given in the option vlan declaration, not the VLAN tag itself (specified in the option vid declaration).

More details at https://openwrt.org/docs/guide-user/base-system/basic-networking


#3

Hi, thanks a lot, still confusing to me,

more beef on the table I found the AR9331 datasheet:

seems like my minirouter doesn't uses all the available ports on the switch (built-in one),

its like the chip does have the exit but they are just there non physically connected to anything

(I am not brave enough to open the case !!).

Please correct me if I am wrong, this is what my logic tells me, the router still need the switch because

through switch0/eth1 port 0 the CPU talks to the LAN.

If I connect to a router or PC via cable the

'swconfig dev eth1 show' will list both port 0 channel to CPU and port 1 (on eth1) as linked

I need both of them to connect from CPU to LAN.

If I connect with relayd package the minirouter to a router via wifi (thanks to openwrt relay protocol see https://openwrt.org/docs/guide-user/network/wifi/relay_configuration) and then I log into the minirouter

after 'swconfig switch0(or eth1) show' will list only port 0 as linked.

I can not turn off the switch because otherwise I want be able to have the CPU connecting to LAN ? (right or not?)

My question is (I am still trying to find swconfig documentation accessible to my poor routing/linux etc background, I know about (https://openwrt.org/docs/techref/swconfig?s[]=swconfig ; https://openwrt.org/docs/guide-user/base-system/basic-networking part on config switch)

why when I boot up my openwrt router and run 'swconfig dev switch0 show' i get

Global attributes:
enable_vlan0: 0
mirror_monitor_port: 15

?

I mean is 'enable_vlan0: 0' means I enabled vlan0 or that vlan0 is not enabled ??

I am asking this because if I use

swconfig dev switch0 set mirror_monitor_port off

even without using swconfig dev switch0 set apply

using 'swconfig dev switch0 show' i get

Global attributes:
enable_vlan0: 0
mirror_monitor_port: 0

Of course the second question is why when I build and install openwrt and after the first boot

I get the mirror_monitor_port: 15 set up instead of mirror_monitor_port: 0 ?

thanks a lot

Best

P.

I'll try to figure out about VLAN later on


#4

Hi, ended up just addind

the line: config switch 'eth1'
option name 'eth1'

to my /etc/config/network

then: uci commit network

to find the switch menu under Luci network pane

just trying to figure out why its seems like I have the ports inverted,

what I am trying to do is mirroring CPU 0 port on eth1 (LAN port I hope) to figure out If I cant get mirroring of wireless traffic too using eth1 port as wireshark monitoring interface.

Problem is Luci show CPU 0 as eth0 instead of eth1 and assigns port 5 instead of /etc/config/network port 1 .

What I set on Luci:

switch

what I got on cat /etc/config/network

switch-cat

Any clue

could be something like this

Bests P.


#5

Hi, kind of figure out from kernel log that maybe this is not the way to accomplish what I was thinking about !
(said maybe going blind in here)

Found out inside openwrt/target/linux/ar71xx/files/arch/mips/ath79

this

"/*
 *  GL_ar150 board support
 *
 *  Copyright (C) 2011 dongyuqi <729650915@qq.com>
 *  Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
 *  Copyright (C) 2013 alzhao <alzhao@gmail.com>
 *  Copyright (C) 2014 Michel Stempin <michel.stempin@wanadoo.fr>
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
*/

#include <linux/gpio.h>

#include <asm/mach-ath79/ath79.h>

#include "dev-eth.h"
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-m25p80.h"
#include "dev-usb.h"
#include "dev-wmac.h"
#include "machtypes.h"


	
	/* register eth0 as WAN, eth1 as LAN */
	ath79_init_mac(ath79_eth0_data.mac_addr, art+GL_AR150_MAC0_OFFSET, 0);
	ath79_init_mac(ath79_eth1_data.mac_addr, art+GL_AR150_MAC1_OFFSET, 0);
	ath79_register_mdio(0, 0x0);
	ath79_register_eth(0);
	ath79_register_eth(1);

	/* register wireless mac with cal data */
	ath79_register_wmac(art + GL_AR150_CALDATA_OFFSET, art + GL_AR150_WMAC_MAC_OFFSET);
}

MIPS_MACHINE(ATH79_MACH_GL_AR150, "GL-AR150", "GL.iNet GL-AR150", gl_ar150_setup);

Do You know to whom I should ask about how figure out what the:

/* register eth0 as WAN, eth1 as LAN */
	ath79_init_mac(ath79_eth0_data.mac_addr, art+GL_AR150_MAC0_OFFSET, 0);
	ath79_init_mac(ath79_eth1_data.mac_addr, art+GL_AR150_MAC1_OFFSET, 0);
	ath79_register_mdio(0, 0x0);
	ath79_register_eth(0);
	ath79_register_eth(1);

means and if it could be the point where to reset GE0 to have both my ethernet cable plug sockets on the same switch ? Wondering if it could be something about how the hardware was wired or there is somewhere a place where a change of a setting could accomplish!

Screenshot%20from%202018-09-27%2019-38-29%20(copy)

given ar9331 soc datasheet (if it reliable)

Screenshot%20from%202018-09-27%2019-43-04

Thanks for any clue

Bests

P.


#6

i dont think these datasheets are reliable. MAC5 is not listed anywhere in the picture. one should start guessing if they meant mdio or counted from mac0 meaning mac4.

GE0 why is listed as 10/100, when both MACs are gigabit? even if it had only 2 wires it should still be possible to rule out standards and make it negotiate at customized link speed..

what you are trying to achieve i think is possible, you just need to hit right combination of registers


#7

Hi Psyborg,

thank You for Your kind reply.

If You have time please help me to understand better, I'lll try to be as short as possible.

I googled for ar71xx soc and found out another datasheet about ar7100 which seems it doesnt have a switch but only a gbethernet adapter with two ports.

So my question is:

openwrt for gl.inet ar150 uses ar71xxx as target platform to build the final bin image file.
inside the openwrt/target/linux/ar71xx/ repository there is everything to build the kernel (or part of it)for the minirouter adapting ar71xxx platform to the related chip the ar9331 (or the other way round adapting ar9331 to ar71xxx))??

Is there a diagram somewhere that could help to understand how all the makefiles inside the subdirectory of openwrt/target/linux/ar71xx/ like openwrt/target/linux/ar71xx/files/arch/mips/ath79
are called in sequence to build the final binary.

Its like in this way I would try to imagine how to reset the ge0 I was talking about in the previous
post

In some files like : openwrt / target / linux / ar71xx / files / arch / mips / include / asm / mach-ath79 / ag71xx_platform.h I can read:

25  struct ag71xx_platform_data { 
26  	phy_interface_t	phy_if_mode; 
27  	u32		phy_mask; 
28  	int		speed; 
29  	int		duplex; 
30  	u32		reset_bit; 
31  	u8		mac_addr[ETH_ALEN]; 
32  	struct device	*mii_bus_dev; 
33  
 
34  	u8		has_gbit:1; 
35  	u8		is_ar91xx:1; 
36  	u8		is_ar7240:1; 
37  	u8		is_ar724x:1; 
38  	u8		has_ar8216:1; 
39  	u8		use_flow_control:1; 
40  	u8		enable_sgmii_fixup:1; 
41  	u8		disable_inline_checksum_engine:1;

that looks something could be related to:

datasheet

here I am just fantasizing but u8 has an analogy with bit 8 where they say

CFG_SW_PHY_
ADDR_SWAP
RW Exchanges the address of PHY port 0 with that of PHY port 4 in the
Ethernet switch

which could be in someway related to how the internal wiring of the cpu <-> mac <-> mdio <-> ge
works ?

If I am getting everything completely wrong could you point me towards

something to read about how openwrt manage their targets architecture

and how the kernel "abstract away the hardware, providing uniform interface to user space" ?

The last phrase on quote is just to figure out if my logic is the correct one or I am getting

everything wrong ? Its like I am trying to understand too many things in one time.......

but the idea is still having the kernel to register only eth1 as interface and then use

software virtualization (Am I right?) to distinguish between LAN eth1.1 and WAN eth1.0 (is it possible?)

on my minirouter ?

Thanks again

Bests.

P.


#8

(Moved to For Developers section.)


#9

Hi I'll try with different wording found on 8devices Carambola2 forum,

think its the most proper wording to rephase my concept (I told You I am a real noob):"

Run eth0 and eth1 as part of AR9331 hardware switch

As far as I understand, the AR9331 has a 5-port internal hardware switch.

I would like to run the two physical ethernet ports which are rounted out of the Carambola2 to be handled both by the internal ethernet switch, having only one MAC port of the AR9331 talking to that switch. Does anyone know how to do this?

Why not just configure a software bridge using brctl on Linux? Well, software switching has higher latency and adds software load without any need.

Thanks in advance!"

Thanks

P.


#10

Hi Psyborg,

while browsing the openwrt git looking for ar9331 based devices with more than two ethernet plug

I found the TP-LINK TL-WR940N v4 router

under https://github.com/openwrt/openwrt/blob/master/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr940n-v4.c

I found the switch paraghraph I found:

static void __init tl_wr940n_setup(void)
{
	u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
	u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);

	ath79_register_m25p80(&tl_wr940n_flash_data);

	ath79_register_mdio(0, 0x0);

	ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
	ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);

	ath79_switch_data.phy4_mii_en = 1;

	ath79_register_eth(0);
	ath79_register_eth(1);

ath79_register_wmac(ee, mac);

are these the registry key you were talking about ? I don't know where to find them and of course

how to set them for the ge0/mac0 reset the datasheet was talking about.

Cheers

P.


#11

your device seem to be missing profile in target/linux/ar71xx/base-files/etc/board.d/02_network

adding something like this should work.

	ucidef_set_interface_lan "eth1" "eth0"
	ucidef_add_switch "switch0" \
		"0@eth1" "1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1"

#12

Hi Psyborg, sorry but I am not following please correct me if aI am wrong:

"UCI creates an abstraction layer for configuring network interfaces:
In /etc/config/network you allocate a name like lan or internet_wire or whatever to each ifname-variable for every device and then this name is consistently used through the entire UCI configuration. But this can only be used in conjunction with UCI!"

but I thought we were talking about devices (physical nic interfaces)

what I was thinking it was like booting up the routher with the 2 available physical ports of the switch
as two devices belonging to the switch as this makes sense according to the data sheet !
Unless the two interfaces are already connected by the switch and the datashhet is misleading.

Otherwise I am still in deep troubles trying to visualize the physical layout of the ar150 router.

Remember that all of this was to be able to mirror the data going thruough one port, to the second port
and use a PC connected to the 2nd port to analyze the traffic, and as far as I understood I can mirror traffic from one port to the other on a switch but not between unrelated unrelated ones.

Thanks

Best

P.


#13

sorry but in one post you have ar150 in other some tplink and then carambola.. which device really are you trying to configure?

single port qca9531 - i was able to connect via (default) gmac0 and via switch on gmac1 by modifying 02_network and rebuilding


#14

Hi Psyborg,

thank you for Your patience. I am very new to linux.. imagine about embedded ones.

ar150 uses 9330(or 9331)soc carambola2 uses the same chipset, TP-LINK TL-WR940N v4 too.

So my idea was to figure out the difference between the 3 machines surfing the openwrt build directory.

I found differences in target/linux/ath79/base-files/etc/board.d/02_network

and in all files in target/linux/ar71xx/files/arch/mips/ath79/
like mach-gl-ar150.c, mach-wifi-pineapple-nano.c, mach-tl-wr940n-v4.c
in these last ones

like ar150 says ..

    .......

    /* disable PHY_SWAP and PHY_ADDR_SWAP bits */
ath79_setup_ar933x_phy4_switch(false, false);

................

/* register eth0 as WAN, eth1 as LAN */
ath79_init_mac(ath79_eth0_data.mac_addr, art+GL_AR150_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, art+GL_AR150_MAC1_OFFSET, 0);
ath79_register_mdio(0, 0x0);
ath79_register_eth(0);
ath79_register_eth(1);

......................

wifi pineapple:

...........
ath79_setup_ar933x_phy4_switch(false, false);
ath79_register_mdio(0, 0x0);

ath79_init_mac(ath79_eth0_data.mac_addr,
	       art + WIFI_PINEAPPLE_NANO_MAC1_OFFSET, 0);
ath79_register_eth(0);

..............................

tl-wr940n-v4.c

....................
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);

ath79_switch_data.phy4_mii_en = 1;

ath79_register_eth(0);
ath79_register_eth(1);

......................................

then with a different SOC (ar9344 with switch AR8327) wndr4300 :
..............................................
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);

mdiobus_register_board_info(wndr4300_mdio0_info,
			    ARRAY_SIZE(wndr4300_mdio0_info));

ath79_register_mdio(0, 0x0);

/* GMAC0 is connected to an AR8327N switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);

...........................................

inside target/linux/ar71xx/base-files/etc/board.d/02_network

#!/bin/sh

Copyright (C) 2011-2015 OpenWrt.org

. /lib/functions/system.sh
. /lib/functions/uci-defaults.sh

ar71xx_setup_interfaces()
{
local board="$1"

case "$board" in


..............

wifi-pineapple-nano|\

..........

gl-ar150|\

.....................

tl-wr940n-v4|\

........................
wndr4300)
ucidef_add_switch "switch0"
"0@eth0" "1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1" "5:wan"

...................................

My questions are:

1--- target/linux/ar71xx/base-files/etc/board.d/02_network
defines the UCI configuration after the network devices are already loaded in the kernel ? yes or no ?
(is it the right wording or should I say something different) ?

2--- the only references to interfaces are the ath9_register_eth(0) in the mac-XXX files
are these files responsible for the loading or configuration of the network device driver definition in the kernel ?
(is it the right wording or should I say something different) ?

3-- how if is possible (I could borrow the 4300 set up and apply it to ar150 to have the 2 ethernet sockets
(the plug on my minirouter) be handled by the built in switch ??
Remember everything started from the ar9331 datasheet claiming about the built-in switch

4-- why in the

target/linux/ar71xx/files/arch/mips/ath79/Kconfig.openwrt:

.....
config ATH79_MACH_GL_AR150
bool "GL AR150 support"
select SOC_AR933X
select ATH79_DEV_ETH
select ATH79_DEV_GPIO_BUTTONS
select ATH79_DEV_LEDS_GPIO
select ATH79_DEV_M25P80
select ATH79_DEV_USB
select ATH79_DEV_WMAC
...................

there is nothing about a switch ? I mean I could be wrong but to me sounds like

select ATH79_DEV_ETH will load a driver for ethernet controller/devices/whathever ?(right ? wrong)?
why I dont have anything related to switch ??

5-- what is the 03_network-switchX-migration in target/linux/ar71xx/etc about ?

in some lines I can read:
............................
rb-2011uas-2hnd)
migrate_switch_name "eth0" "switch0"
migrate_switch_name "eth1" "switch1"
..............................

So eth0 could refer to both a switch or a normal single physical interface ??
How I can distinguish between them ?

Hope my question are clear to You, to me they are kind out of the logic I think I its behind openwrt

but I feel I am kind far from the right track at the moment.

THanks

P.


#15

hi

  1. -yes
  2. -yes, but they are not the only ones. they are actually, let's say, initializers of the lower-level code in dev-eth.c and similar files
  3. -if the datasheet informations are not contradictory and this can work (did not check while my ar9331 devices were operational) you should look for SW_ONLY_MODE in code (it is for ar934x) and reuse it for ar933x chipset
  4. -because switch-related code is already in files i wrote in answer to your question 2
  5. -something routerboard related, i've not checked it..

regarding uci configuration, yes, eth0 could refer to whichever interface you assign it to.
when it comes to kernel driver eth0 is usually tied to gmac0 and eth1 to gmac1 (this one shows link speed 1000Mbps in logs)


#16

Hi Psyborg,

found online the ar9344 soc datasheet quite impressive ar7100.pdf is 112pages; ar9331.pdf is 320pages and ar9344.pdf is466pages.

Screenshot%20from%202018-10-09%2018-19-00

And here the SW_ONLY_MODE part.

Talking about reusing it for ar933x chipset bring me to the:

Atheros AR71XX/AR724X/AR913X SoC register definitions in

openwrt/target/linux/ar71xx/image/lzma-loader/src/ar71xx_regs.h

where I find:
........................................
/*

  • AR933X GMAC interface
    */
    #define AR933X_GMAC_REG_ETH_CFG 0x00

#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
#define AR933X_ETH_CFG_MII_GE0 BIT(1)
#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)

/*

  • AR934X GMAC Interface
    */
    #define AR934X_GMAC_REG_ETH_CFG 0x00

#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
#define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
................................................

Now I'll have to find out what the lzma-loader is but first of all a question for You:

is the ar71xx_regs.h file patchable or I just have to add a
#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) line to ar93x1 GMAC interface block

inside the ar71xx_regs.h file? That's because I wasn' t able to find the file in the build_dir as per openwrt

patching instructions: https://openwrt.org/docs/guide-developer/build-system/use-patches-with-buildsystem.

In the meanwhile ill work on the other occurencies of SW_ONLY_MODE inside openwrt

hopefully I'll found a board that uses this switch only mode inside the target/ar71xx directory

Thanks again

Bests

P.


#17

look for airgateway pro in mach-ubnt-xm, /* GMAC0 is left unused in this configuration */

ar9331 datasheet shows bit(6) as reserved and RO. unless it is some other bit you could try just using ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);

good luck


#18

sorry I meant #define AR933X_ETH_CFG_SW_ONLY_MODE BIT(6) line to ar933x GMAC interface block


#19

Hi everybody, hoping that Psyborg is listening.

I am going mad trying to figure out how openwrt makefile proceds through the building tree.

Questions :slight_smile:

  1. Does Buildroot 'make graph-depends' works on openwrt ?
    I tried make graph-depends but no success.

Still working on ar150 soc ar9331 and built in switch behaviour
(funny note my kernel says SoC: Atheros AR9330 rev 1 but on the actual chip I can read ar9331)

  1. what is the difference between openwrt/target/linux/ar71xx
    and openwrt/target/linux/ath79 ?
    Are the two directory related meaning while building for my
    ar150 device makefile uses pieces of both the directories or only the one I select
    with make menuconfig, (that being ar71xx) ?

  2. surfed between mach-gl-ar150.c , dev-eth.h dev-eth.c ar71xx_regs.h ag71xx_platform.h
    trying to figure out differences between ar933x and ar934x, remember I am starting from
    AR934X_ETH_CFG_SW_ONLY_MODE. Is there some documentation that explains at list
    the relation between these files during building process ?

  3. I noticed, I wish, I had noticed earlier in ar71xx_regs.h:

   *
 * AR933X GMAC interface
 */
#define AR933X_GMAC_REG_ETH_CFG		0x00

#define AR933X_ETH_CFG_RGMII_GE0	BIT(0)
#define AR933X_ETH_CFG_MII_GE0		BIT(1)
#define AR933X_ETH_CFG_GMII_GE0		BIT(2)
#define AR933X_ETH_CFG_MII_GE0_MASTER	BIT(3)
#define AR933X_ETH_CFG_MII_GE0_SLAVE	BIT(4)
#define AR933X_ETH_CFG_MII_GE0_ERR_EN	BIT(5)
#define AR933X_ETH_CFG_SW_ONLY_MODE	BIT(6)   I added this line to copy mach-ubnt-xm behaviour
#define AR933X_ETH_CFG_SW_PHY_SWAP	BIT(7)
#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP	BIT(8)
#define AR933X_ETH_CFG_RMII_GE0		BIT(9)
#define AR933X_ETH_CFG_RMII_GE0_SPD_10	0
#define AR933X_ETH_CFG_RMII_GE0_SPD_100	BIT(10)

/*
 * AR934X GMAC Interface
 */
#define AR934X_GMAC_REG_ETH_CFG		0x00

#define AR934X_ETH_CFG_RGMII_GMAC0	BIT(0)
#define AR934X_ETH_CFG_MII_GMAC0	BIT(1)
#define AR934X_ETH_CFG_GMII_GMAC0	BIT(2)
#define AR934X_ETH_CFG_MII_GMAC0_MASTER	BIT(3)
#define AR934X_ETH_CFG_MII_GMAC0_SLAVE	BIT(4)
#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN	BIT(5)
#define AR934X_ETH_CFG_SW_ONLY_MODE	BIT(6)
#define AR934X_ETH_CFG_SW_PHY_SWAP	BIT(7)
#define AR934X_ETH_CFG_SW_APB_ACCESS	BIT(9)
#define AR934X_ETH_CFG_RMII_GMAC0	BIT(10)
#define AR933X_ETH_CFG_MII_CNTL_SPEED	BIT(11)
#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST	BIT(13)

that ar933x defines GE0 while ar9334 defines GMAC0.
Can I just consider them the same and copy ar934x GMAC0 pieces of code
changing them with GE0 ???

  1. Right now I'm just trying to copy pieces of code between the two mach different files
    (mach-gl-ar-150.c and mach-ubnt-xm.c) but I spend a lot time waiting for
    results of compiling, always getting errors of course. I am using the bare minimum
    selected ar71xx and gl-ar150 no other stuff (packages, modules etc).
    Is there a way to shorten the building time ?

Thanks any help will be appreciate

Bests

P.


[Solved] Router-set-up advertising
#20

Hi sorry again,

still about the

#define AR933X_ETH_CFG_SW_ONLY_MODE	BIT(6)

I am stuck at:

# make target/linux/{clean,prepare} V=s QUILT=1

# cd build_dir/target-mips_24kc_musl/linux-ar71xx_generic/linux-4.9.124/arch/mips/include/asm/mach-ath79

# quilt series

# quilt push platform/601-MIPS-ath79-add-more-register-defines.patch

.....................
.....................
Applying patch platform/105-spi-spi-ath79-use-gpio_set_value_cansleep-for-GPIO-c.patch
patching file drivers/spi/spi-ath79.c

Applying patch platform/106-02-MIPS-ath79-do-AR724x-PCIe-root-complex-init.patch
patching file arch/mips/include/asm/mach-ath79/ar71xx_regs.h
Hunk #1 FAILED at 169.
1 out of 1 hunk FAILED -- rejects in file arch/mips/include/asm/mach-ath79/ar71xx_regs.h
patching file arch/mips/pci/pci-ar724x.c
Patch platform/106-02-MIPS-ath79-do-AR724x-PCIe-root-complex-init.patch does not apply (enforce with -f)
kk@kk-WC:~/Documents/openwrt/build_dir/target-mips_24kc_musl/linux-ar71xx_generic/linux-4.9.124/arch/mips/include/asm/mach-ath79$ 
.......................

I had a look at

openwrt/target/linux/ar71xx/patches-4.9/106-02-MIPS-ath79-do-AR724x-PCIe-root-complex-init.patch

--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -169,6 +169,9 @@
 #define AR724X_PLL_REG_CPU_CONFIG	0x00
 #define AR724X_PLL_REG_PCIE_CONFIG	0x10
 
+#define AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS	BIT(16)
+#define AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET	BIT(25)
+
 #define AR724X_PLL_FB_SHIFT		0
 #define AR724X_PLL_FB_MASK		0x3ff
 #define AR724X_PLL_REF_DIV_SHIFT	10
--- a/arch/mips/pci/pci-ar724x.c
+++ b/arch/mips/pci/pci-ar724x.c
@@ -12,14 +12,18 @@
 #include <linux/irq.h>
 #include <linux/pci.h>
 #include <linux/init.h>
+#include <linux/delay.h>
...............................

a patch file pointing to two differents files ? I know I should study more but I first heard about patches
about one month ago !!

Does anybody have a clue how to get over this to finally having a chance to modify my
601-MIPS-ath79-add-more-register-defines.patch ?

Thanks a lot

Bests

P.