Support for Archer c50 v4


#1

Hello guys

I would like to know if the new Tp-link Archer C50 v4 supports the LEDE / OpenWrt firmware? It´s very similar to Archer C50 v3.0 (MT7628A vs MT7628A)
Is anyone working on LEDE firmware for Archer c50 v4?

Thanks


#2

Send me the links to the firmware a binary dump serial dump and ill try to port it.
But someone need to test my binaries .., send me pictures of the pcb as well pls high res would be nice.
Thx Elias


#3

For the support status of any device, please see the Table of Hardware.
You can reach the ToH via "Supported devices":
grafik

-> ToH filtered for C50

If your device is not listed as supported, then your device is not supported.


#5

Someone has a bootlog? And or pcb images, FCC looks the same for c50v3 ..

Seems to be same system like v3.0 but i cant promise. Should be possible to flash the v3 image when there is no difference in ram or rom. Dont try it! Send me Images from its inside instead!
Greetings Elias


#6

Hi, I also have this router, and I am too wondering if v3 will work. The FCC ID for mine is TE7C50V3, as you said. I took some pics of the inside. Let me know if you need me to zoom in on anything or take better ones.

Firmware Version:0.9.1 0.2 v0093.0 Build 180313 Rel.54477n(4555)
Hardware Version:Archer C50 v4 00000002

Pics:




#7

Thx,
the pcb is identical. I cant read the ram type, could be a different one. I expect they use a different bootloader version.
I will have a look into the binaries they both use uboot 4.3.0.0(1.1.3) i can say now but there could be some minor differences.


#8

Hi, I'm not sure which is the RAM chip. Is it this one?

ESMT
M14D5121632A
AZA1 -2.5B
P826F13 805


#9

ok its the same, now ive to check the flash layout to prevent bricking yours if you try to flash openwrt.


#10

As far as i can see the only difference is in the bootloader, openwrt wont replace the bootloader, hence i believe you can flash v3 version. I believe V4 is for a different country regulatory domain. But that shouldnt make a difference since in openwrt you will choose yours to meet the law.
Binwalk output:

xyz@androidbuilder:~# binwalk Archer_C50v4_EU_0.9.1_0.2_up_boot\[180313-rel54477\].bin

DECIMAL       HEXADECIMAL     DESCRIPTION
--------------------------------------------------------------------------------
80928         0x13C20         U-Boot version string, "U-Boot 1.1.3 (Mar 13 2018 - 15:00:31)"
132096        0x20400         LZMA compressed data, properties: 0x5D, dictionary size: 8388608 bytes, uncompressed size: 3650664 bytes
1442304       0x160200        Squashfs filesystem, little endian, version 4.0, compression:xz, size: 5833776 bytes, 839 inodes, blocksize: 131072 bytes, created: 2018-03-13 07:08:03

xyz@androidbuilder:~# binwalk Archer_C50v3_EU_0.9.1_0.6_up_boot\[171227-rel72331\].bin

DECIMAL       HEXADECIMAL     DESCRIPTION
--------------------------------------------------------------------------------
82272         0x14160         U-Boot version string, "U-Boot 1.1.3 (Dec 27 2017 - 19:50:29)"
132096        0x20400         LZMA compressed data, properties: 0x5D, dictionary size: 8388608 bytes, uncompressed size: 3650664 bytes
1442304       0x160200        Squashfs filesystem, little endian, version 4.0, compression:xz, size: 5246860 bytes, 696 inodes, blocksize: 131072 bytes, created: 2017-12-27 12:05:35

But be aware you still can brick it with a v3 image! I dunno if we need to change the tplink header or the checksum..


#11

I am confused about the output of mktplinkfw2.
These images are original stock images from tplink support, should'nt they match the checksum expected by mtkplinkfw2?

xyz@xyz:~# mktplinkfw -i Archer_C50v3_EU_0.9.1_0.4_up_boot\[170608-rel35472\].bin
File name              : Archer_C50v3_EU_0.9.1_0.4_up_boot[170608-rel35472].bin
File size              : 0x007c0200 /  8126976 bytes
[mktplinkfw] *** error: file does not seem to have V1/V2 header!

xyz@xyz:~# mktplinkfw2 -i Archer_C50v3_EU_0.9.1_0.4_up_boot\[170608-rel35472\].bin
File name              : Archer_C50v3_EU_0.9.1_0.4_up_boot[170608-rel35472].bin
File size              : 0x007c0200 /  8126976 bytes
Version 2 Header size  : 0x00000200 /      512 bytes
Unknown value 1        : 0x01000000 / 16777216 bytes
Header MD5Sum1         : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 (*ERROR*)
          --> expected : 0c 4e 62 99 a5 bd 58 b1 83 6e 58 35 6c 0c 2e 07
Header MD5Sum2         : ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff (purpose yet unknown, unchecked here)

Firmware version       : ver. 2.0
Hardware ID            : 0x001d9ba4 (unknown)
Hardware Revision      : 0x00000079
Software version       : 0.9.1-0.4

Kernel data offset     : 0x00020400 /   132096 bytes
Kernel data length     : 0x00129260 /  1217120 bytes
Kernel load address    : 0x00000080
Kernel entry point     : 0x50c10080
Rootfs data offset     : 0x00140000 /  1310720 bytes
Rootfs data length     : 0x003dc000 /  4046848 bytes
Boot loader data offset: 0x00000000 /        0 bytes
Boot loader data length: 0x00018284 /    98948 bytes
Total firmware length  : 0x007c0200 /  8126976 bytes
xyz@xyz:~# mktplinkfw2 -i Archer_C50v4_EU_0.9.1_0.2_up_boot\[180313-rel54477\].bin
File name              : Archer_C50v4_EU_0.9.1_0.2_up_boot[180313-rel54477].bin
File size              : 0x00790200 /  7930368 bytes
Version 2 Header size  : 0x00000200 /      512 bytes
Unknown value 1        : 0x02000000 / 33554432 bytes
Header MD5Sum1         : 6d 1b 34 41 27 f0 fc 1a ae 9a 34 c6 e3 e0 f2 27 (*ERROR*)
          --> expected : 73 ce 50 98 7b f6 ca 8a 69 33 d0 3c 59 32 bd eb
Header MD5Sum2         : ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff (purpose yet unknown, unchecked here)

Firmware version       : ver. 2.0
Hardware ID            : 0x001d589b (unknown)
Hardware Revision      : 0x00000093
Software version       : 0.9.1-0.2

Kernel data offset     : 0x00020400 /   132096 bytes
Kernel data length     : 0x00129400 /  1217536 bytes
Kernel load address    : 0x00000080
Kernel entry point     : 0x50c10080
Rootfs data offset     : 0x00140000 /  1310720 bytes
Rootfs data length     : 0x00591000 /  5836800 bytes
Boot loader data offset: 0x00000000 /        0 bytes
Boot loader data length: 0x00017da0 /    97696 bytes
Total firmware length  : 0x00790200 /  7930368 bytes


#12

ArcherC50v3 with ArcherC50v4 Image bootlog

[04030C0D][04030D06]
DDR Calibration DQS reg = 00008888


U-Boot 1.1.3 (Aug 18 2017 - 09:57:27)

Board: Ralink APSoC DRAM:  64 MB
relocate_code Pointer at: 83fb4000
gpiomode1 54154404.
gpiomode2 05540555.
flash manufacture id: c8, device id 40 17
find flash: GD25Q64B
============================================
Ralink UBoot Version: 4.3.0.0
--------------------------------------------
ASIC 7628_MP (Port5<->None)
DRAM component: 512 Mbits DDR, width 16
DRAM bus: 16 bit
Total memory: 64 MBytes
Flash component: SPI Flash
Date:Aug 18 2017  Time:09:57:27
============================================
icache: sets:512, ways:4, linesz:32 ,total:65536
dcache: sets:256, ways:4, linesz:32 ,total:32768

 ##### The CPU freq = 580 MHZ ####
 estimate memory size =64 Mbytes
RESET MT7628 PHY!!!!!!
continue to starting system.                                                  0
disable switch phyport...

3: System Boot system code via Flash.(0xbc020000)
do_bootm:argc=2, addr=0xbc020000
## Booting image at bc020000 ...
   Uncompressing Kernel Image ... OK
No initrd
## Transferring control to Linux (at address 8000c150) ...
## Giving linux memsize in MB, 64

Starting kernel ...


LINUX started...

 THIS IS ASIC
Linux version 2.6.36 (root@soho) (gcc version 4.6.3 (Buildroot 2012.11.1) ) #4 T                                   ue Mar 13 15:03:53 HKT 2018

 The CPU feqenuce set to 575 MHz

 MIPS CPU sleep mode enabled.
CPU revision is: 00019655 (MIPS 24Kc)
Software DMA cache coherency
Determined physical RAM map:
 memory: 04000000 @ 00000000 (usable)
Initrd not found or empty - disabling initrd
Zone PFN ranges:
  Normal   0x00000000 -> 0x00004000
Movable zone start PFN for each node
early_node_map[1] active PFN ranges
    0: 0x00000000 -> 0x00004000
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 16256
Kernel command line: console=ttyS1,115200 root=/dev/mtdblock2 rootfstype=squashf                                   s init=/sbin/init
PID hash table entries: 256 (order: -2, 1024 bytes)
Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
Primary instruction cache 64kB, VIPT, , 4-waylinesize 32 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
Writing ErrCtl register=0007f592
Readback ErrCtl register=0007f592
Memory: 61064k/65536k available (2725k kernel code, 4472k reserved, 674k data, 1                                   68k init, 0k highmem)
NR_IRQS:128
console [ttyS1] enabled
Calibrating delay loop... 386.04 BogoMIPS (lpj=772096)
pid_max: default: 4096 minimum: 301
Mount-cache hash table entries: 512
NET: Registered protocol family 16
RALINK_GPIOMODE = 54154404
RALINK_GPIOMODE = 54144404
***** Xtal 40MHz *****
start PCIe register access
RALINK_RSTCTRL = 2400000
RALINK_CLKCFG1 = fdbfffc0

*************** MT7628 PCIe RC mode *************
PCIE0 enabled
Port 0 N_FTS = 1b105000
init_rt2880pci done
bio: create slab <bio-0> at 0
vgaarb: loaded
pci 0000:00:00.0: BAR 0: can't assign mem (size 0x80000000)
pci 0000:00:00.0: BAR 8: assigned [mem 0x20000000-0x200fffff]
pci 0000:00:00.0: BAR 9: assigned [mem 0x20100000-0x201fffff pref]
pci 0000:00:00.0: BAR 1: assigned [mem 0x20200000-0x2020ffff]
pci 0000:00:00.0: BAR 1: set to [mem 0x20200000-0x2020ffff] (PCI address [0x2020                                   0000-0x2020ffff]
pci 0000:01:00.0: BAR 0: assigned [mem 0x20000000-0x200fffff 64bit]
pci 0000:01:00.0: BAR 0: set to [mem 0x20000000-0x200fffff 64bit] (PCI address [                                   0x20000000-0x200fffff]
pci 0000:01:00.0: BAR 6: assigned [mem 0x20100000-0x2010ffff pref]
pci 0000:00:00.0: PCI bridge to [bus 01-01]
pci 0000:00:00.0:   bridge window [io  disabled]
pci 0000:00:00.0:   bridge window [mem 0x20000000-0x200fffff]
pci 0000:00:00.0:   bridge window [mem 0x20100000-0x201fffff pref]
BAR0 at slot 0 = 0
bus=0x0, slot = 0x0
res[0]->start = 0
res[0]->end = 0
res[1]->start = 20200000
res[1]->end = 2020ffff
res[2]->start = 0
res[2]->end = 0
res[3]->start = 0
res[3]->end = 0
res[4]->start = 0
res[4]->end = 0
res[5]->start = 0
res[5]->end = 0
bus=0x1, slot = 0x0
res[0]->start = 20000000
res[0]->end = 200fffff
res[1]->start = 0
res[1]->end = 0
res[2]->start = 0
res[2]->end = 0
res[3]->start = 0
res[3]->end = 0
res[4]->start = 0
res[4]->end = 0
res[5]->start = 0
res[5]->end = 0
Switching to clocksource Ralink Systick timer
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 2048 (order: 2, 16384 bytes)
TCP bind hash table entries: 2048 (order: 1, 8192 bytes)
TCP: Hash tables configured (established 2048 bind 2048)
TCP reno registered
NET: Registered protocol family 1
squashfs: version 4.0 (2009/01/31) Phillip Lougher
fuse init (API version 7.15)
msgmni has been set to 119
io scheduler noop registered
io scheduler deadline registered (default)
Ralink gpio driver initialized
i2cdrv_major = 218
Serial: 8250/16550 driver, 2 ports, IRQ sharing enabled
serial8250: ttyS0 at MMIO 0x10000d00 (irq = 21) is a 16550A
serial8250: ttyS1 at MMIO 0x10000c00 (irq = 20) is a 16550A
brd: module loaded
flash manufacture id: c8, device id 40 17
GD25Q64B(c8 40170000) (8192 Kbytes)
mtd .name = raspi, .size = 0x00800000 (8M) .erasesize = 0x00010000 (64K) .numeraseregions = 0
Creating 7 MTD partitions on "raspi":
0x000000030000-0x000000050000 : "boot"
0x000000050000-0x000000190000 : "kernel"
0x000000190000-0x0000007c0000 : "rootfs"
mtd: partition "rootfs" set to be root filesystem
0x0000007c0000-0x0000007d0000 : "config"
0x0000007d0000-0x0000007e0000 : "romfile"
0x0000007e0000-0x0000007f0000 : "rom"
0x0000007f0000-0x000000800000 : "radio"
Register flash device:flash0
PPP generic driver version 2.4.2
PPP MPPE Compression module registered
NET: Registered protocol family 24
Mirror/redirect action on
u32 classifier
    Actions configured
Netfilter messages via NETLINK v0.30.
nf_conntrack version 0.5.0 (2048 buckets, 8192 max)
ip_tables: (C) 2000-2006 Netfilter Core Team, Type=Linux
TCP cubic registered
NET: Registered protocol family 10
ip6_tables: (C) 2000-2006 Netfilter Core Team
IPv6 over IPv4 tunneling driver
NET: Registered protocol family 17
Ebtables v2.0 registered
802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
All bugs added by David S. Miller <davem@redhat.com>
List of all partitions:
1f00             128 mtdblock0 (driver?)
1f01            1280 mtdblock1 (driver?)
1f02            6336 mtdblock2 (driver?)
1f03              64 mtdblock3 (driver?)
1f04              64 mtdblock4 (driver?)
1f05              64 mtdblock5 (driver?)
1f06              64 mtdblock6 (driver?)
No filesystem could mount root, tried:  squashfs
Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(31,2)


#13

Archerv3 with V3 image bootlog:

[04030C0D][04030D07]
DDR Calibration DQS reg = 00008988


U-Boot 1.1.3 (Aug 18 2017 - 09:57:27)

Board: Ralink APSoC DRAM:  64 MB
relocate_code Pointer at: 83fb4000
******************************
Software System Reset Occurred
******************************
gpiomode1 54154404.
gpiomode2 05540555.
flash manufacture id: c8, device id 40 17
find flash: GD25Q64B
============================================
Ralink UBoot Version: 4.3.0.0
--------------------------------------------
ASIC 7628_MP (Port5<->None)
DRAM component: 512 Mbits DDR, width 16
DRAM bus: 16 bit
Total memory: 64 MBytes
Flash component: SPI Flash
Date:Aug 18 2017  Time:09:57:27
============================================
icache: sets:512, ways:4, linesz:32 ,total:65536
dcache: sets:256, ways:4, linesz:32 ,total:32768

 ##### The CPU freq = 580 MHZ ####
 estimate memory size =64 Mbytes
RESET MT7628 PHY!!!!!!
continue to starting system.                                                                                     0
disable switch phyport...

3: System Boot system code via Flash.(0xbc020000)
do_bootm:argc=2, addr=0xbc020000
## Booting image at bc020000 ...
   Uncompressing Kernel Image ... OK
No initrd
## Transferring control to Linux (at address 8000c150) ...
## Giving linux memsize in MB, 64

Starting kernel ...

f`xfffx~x~fxxxxffffffffLinux version 2.6.36 (soho@soho) (gcc version 4.6.3 (Buildroot 2012.11.1) ) #1 Tue Feb 7 11:23:58 HKT 2017

 The CPU feqenuce set to 575 MHz

 MIPS CPU sleep mode enabled.
CPU revision is: 00019655 (MIPS 24Kc)
Software DMA cache coherency
Determined physical RAM map:
 memory: 04000000 @ 00000000 (usable)
Initrd not found or empty - disabling initrd
Zone PFN ranges:
  Normal   0x00000000 -> 0x00004000
Movable zone start PFN for each node
early_node_map[1] active PFN ranges
    0: 0x00000000 -> 0x00004000
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 16256
Kernel command line: console=ttyS1,115200 root=/dev/mtdblock2 rootfstype=squashfs init=/sbin/init
PID hash table entries: 256 (order: -2, 1024 bytes)
Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
Primary instruction cache 64kB, VIPT, , 4-waylinesize 32 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
Writing ErrCtl register=0007f590
Readback ErrCtl register=0007f590
Memory: 61136k/65536k available (2713k kernel code, 4400k reserved, 677k data, 168k init, 0k highmem)
NR_IRQS:128
console [ttyS1] enabled
Calibrating delay loop... 386.04 BogoMIPS (lpj=772096)
pid_max: default: 4096 minimum: 301
Mount-cache hash table entries: 512
NET: Registered protocol family 16
RALINK_GPIOMODE = 54154404
RALINK_GPIOMODE = 54144404
***** Xtal 40MHz *****
start PCIe register access
RALINK_RSTCTRL = 2400000
RALINK_CLKCFG1 = fdbfffc0

*************** MT7628 PCIe RC mode *************
PCIE0 enabled
Port 0 N_FTS = 1b105000
init_rt2880pci done
bio: create slab <bio-0> at 0
vgaarb: loaded
pci 0000:00:00.0: BAR 0: can't assign mem (size 0x80000000)
pci 0000:00:00.0: BAR 8: assigned [mem 0x20000000-0x200fffff]
pci 0000:00:00.0: BAR 9: assigned [mem 0x20100000-0x201fffff pref]
pci 0000:00:00.0: BAR 1: assigned [mem 0x20200000-0x2020ffff]
pci 0000:00:00.0: BAR 1: set to [mem 0x20200000-0x2020ffff] (PCI address [0x20200000-0x2020ffff]
pci 0000:01:00.0: BAR 0: assigned [mem 0x20000000-0x200fffff 64bit]
pci 0000:01:00.0: BAR 0: set to [mem 0x20000000-0x200fffff 64bit] (PCI address [0x20000000-0x200fffff]
pci 0000:01:00.0: BAR 6: assigned [mem 0x20100000-0x2010ffff pref]
pci 0000:00:00.0: PCI bridge to [bus 01-01]
pci 0000:00:00.0:   bridge window [io  disabled]
pci 0000:00:00.0:   bridge window [mem 0x20000000-0x200fffff]
pci 0000:00:00.0:   bridge window [mem 0x20100000-0x201fffff pref]
BAR0 at slot 0 = 0
bus=0x0, slot = 0x0
res[0]->start = 0
res[0]->end = 0
res[1]->start = 20200000
res[1]->end = 2020ffff
res[2]->start = 0
res[2]->end = 0
res[3]->start = 0
res[3]->end = 0
res[4]->start = 0
res[4]->end = 0
res[5]->start = 0
res[5]->end = 0
bus=0x1, slot = 0x0
res[0]->start = 20000000
res[0]->end = 200fffff
res[1]->start = 0
res[1]->end = 0
res[2]->start = 0
res[2]->end = 0
res[3]->start = 0
res[3]->end = 0
res[4]->start = 0
res[4]->end = 0
res[5]->start = 0
res[5]->end = 0
Switching to clocksource Ralink Systick timer
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 2048 (order: 2, 16384 bytes)
TCP bind hash table entries: 2048 (order: 1, 8192 bytes)
TCP: Hash tables configured (established 2048 bind 2048)
TCP reno registered
NET: Registered protocol family 1
squashfs: version 4.0 (2009/01/31) Phillip Lougher
fuse init (API version 7.15)
msgmni has been set to 119
io scheduler noop registered
io scheduler deadline registered (default)
Ralink gpio driver initialized
i2cdrv_major = 218
Serial: 8250/16550 driver, 2 ports, IRQ sharing enabled
serial8250: ttyS0 at MMIO 0x10000d00 (irq = 21) is a 16550A
serial8250: ttyS1 at MMIO 0x10000c00 (irq = 20) is a 16550A
brd: module loaded
flash manufacture id: c8, device id 40 17
GD25Q64B(c8 40170000) (8192 Kbytes)
mtd .name = raspi, .size = 0x00800000 (8M) .erasesize = 0x00010000 (64K) .numeraseregions = 0
Creating 7 MTD partitions on "raspi":
0x000000000000-0x000000020000 : "boot"
0x000000020000-0x000000160000 : "kernel"
0x000000160000-0x0000007c0000 : "rootfs"
mtd: partition "rootfs" set to be root filesystem
0x0000007c0000-0x0000007d0000 : "config"
0x0000007d0000-0x0000007e0000 : "romfile"
0x0000007e0000-0x0000007f0000 : "rom"
0x0000007f0000-0x000000800000 : "radio"
Register flash device:flash0
PPP generic driver version 2.4.2
PPP MPPE Compression module registered
NET: Registered protocol family 24
Mirror/redirect action on
u32 classifier
    Actions configured
Netfilter messages via NETLINK v0.30.
nf_conntrack version 0.5.0 (2048 buckets, 8192 max)
ip_tables: (C) 2000-2006 Netfilter Core Team, Type=Linux
keeeeps on booting

#14

We can see v4 has different partition layout!
v3:

Creating 7 MTD partitions on "raspi":
0x000000000000-0x000000020000 : "boot"
0x000000020000-0x000000160000 : "kernel"
0x000000160000-0x0000007c0000 : "rootfs"
mtd: partition "rootfs" set to be root filesystem
0x0000007c0000-0x0000007d0000 : "config"
0x0000007d0000-0x0000007e0000 : "romfile"
0x0000007e0000-0x0000007f0000 : "rom"
0x0000007f0000-0x000000800000 : "radio"

v4:

Creating 7 MTD partitions on "raspi":
0x000000030000-0x000000050000 : "boot"
0x000000050000-0x000000190000 : "kernel"
0x000000190000-0x0000007c0000 : "rootfs"
mtd: partition "rootfs" set to be root filesystem
0x0000007c0000-0x0000007d0000 : "config"
0x0000007d0000-0x0000007e0000 : "romfile"
0x0000007e0000-0x0000007f0000 : "rom"
0x0000007f0000-0x000000800000 : "radio"


#15

I just received a C50 v4 from Amazon (although the description specified v3).
Has anybody tried flashing the v3 firmware? Is it worth trying?
Does the different partition layout of the original firmware make a difference for openwrt?
As far as I see, debricking should be possible even if the wrong firmware was flashed - can anybody confirm that?
Thanks in advance.


#16

Debricking should be possible openwrt wont touch bootloader..
I have not the time atm to keep porting but ill keep on soon..


#17

TP-Link partially broke TFTP recovery with the v4. You will need to pad the Factory image, as TFTP Recovery uses wrong offsets.

The C50v4 is indeed hardware-wise completely identical with the C50v3, the difference lies within a TP-Link design-choice. They are using a split-uboot design, already present in some way on newer QCA based devices. It consists of a "factory-uboot" and a "image-uboot". Factory-uboot is never touched and contains recovery-routines (TFTP / HTTP). "image-uboot" seems to be updated with every firmware-release.

I ported OpenWRT on the C50v4, but i'm not sure if my design with integrating a from source pre-compiled uboot image is the right way. There is no way to flash an image without the "image-uboot" as every way (WebUI / TFTP / HTTP) requires this bootloader to be in place.

If anyone is interested, it can be found here (will rebase it to latest maste later this weekend): https://github.com/blocktrron/openwrt/commit/c38577305289fd1d0659d5e1008eda6104869a6a

It will poop out a factory-image (For use with GUI and HTTP recovery) and a tftp recovery for use with the partially-broken TFTP recovery (Hold down reset button as usual). In case you want to go back to TP-Link firmware, note "Modified firmware-uboot" in the linked commit message. Enter this HTTP recovery, there you can upload the TP-Link firmware.

Everything i'm aware of is working fine and we even have support for TP-Links new U-Boot integrated HTTP recovery.


#18

I asume they've done that because they'll switch to tplink header v3 on theire low cost router images soon.
Do you had a look at: https://github.com/xdarklight/mktplinkfw3 ?

I quote :

" There is no obvious way to get an OpenWrt image booted which doesn't bundle a bootloader, has boot_ofs and boot_len values of 0x00 , the required second header at 0x20200 followed by kernel+rootfs. Changing the kernel_ofs value to 0x00 0x02 0x04 0x00 for both headers didn't worked as expected. I guess the kernel_ofs should be read by the bootloader to identify the kernel start address within the flash. Either the bootloader has a hard-coded kernel start address or my value is wrong."

I would like to give the possibility to use a single uboot enivronment to save some space for the rootfs which is smaler on the v4. For tplink there is no need to have that space left but for us openwrt users it is important, particularly without usb port. So a downgrade to v3 would be my choice. So tftp is they way to go for me, its quite easy XD.
For the user who do not like to struggle with a second program your solution could be better one.

Thx for your work i dont have a v4 to give it a try.


#19

Thank you so much for your port. I copied your c50v4 branch and compiled the image - it worked like a charm so far!

Keep up the good work!

Kind regards

JS11


#20

Hi! It is possible to download the compiled image any place?


#21

Hello,

please can you share your compiled OpenWRT image for the C50v4.

Best Regards