I have a Velocloud 520-AC, based on X86.
I tried to follow the guide here
in order to start with a clean openwrt, to see what works and what doesn't.
after runing this command :
# Write image
dd if=openwrt-x86-64-generic-ext4-combined-efi.img bs=1M of=/dev/sda
followed by a reboot, now it is in a boot loop, and i can't stop it...
an idea of how I can get out of this ?
this is the output that loops :
Sage_coreboot-4.0-VELOCLOUD-EDGE-01.00.00.05 Fri Apr 27 14:21:51 PDT 2018 starting...
Mainboard: Mohon Peak Version 2.0
Build: SageBios_Mohon_Peak - 292
Sage_coreboot-4.0-VELOCLOUD-EDGE-01.00.00.05 Fri Apr 27 14:21:51 PDT 2018 starting...
Mainboard: Mohon Peak Version 2.0
Build: SageBios_Mohon_Peak - 292
Detected C0 stepping SOC
Setting up static southbridge registers... done.
done.
RTC Init
Setting up static northbridge registers... done.
Back from rangeley_early_initialization()
Starting the Intel FSP (early_init)
ConfigureDefaultUpdData
PcdEnableIQAT 1
PcdEnableLan 1
PcdEnableLan 1
PcdEnableLan 1
PcdEnableLan 1
PcdEnableUsb20 1
PcdEnableSata2 1
PcdEnableSata3 1
Sage_coreboot-4.0-VELOCLOUD-EDGE-01.00.00.05 Fri Apr 27 14:21:51 PDT 2018 starting...
Mainboard: Mohon Peak Version 2.0
Build: SageBios_Mohon_Peak - 292
Sage_coreboot-4.0-VELOCLOUD-EDGE-01.00.00.05 Fri Apr 27 14:21:51 PDT 2018 starting...
Mainboard: Mohon Peak Version 2.0
Build: SageBios_Mohon_Peak - 292
Detected C0 stepping SOC
Setting up static southbridge registers... done.
done.
RTC Init
Setting up static northbridge registers... done.
Back from rangeley_early_initialization()
Starting the Intel FSP (early_init)
ConfigureDefaultUpdData
PcdEnableIQAT 1
PcdEnableLan 1
PcdEnableLan 1
PcdEnableLan 1
PcdEnableLan 1
PcdEnableUsb20 1
PcdEnableSata2 1
PcdEnableSata3 1
Sage_coreboot-4.0-VELOCLOUD-EDGE-01.00.00.05 Fri Apr 27 14:21:51 PDT 2018 starting...
Mainboard: Mohon Peak Version 2.0
Build: SageBios_Mohon_Peak - 292
Sage_coreboot-4.0-VELOCLOUD-EDGE-01.00.00.05 Fri Apr 27 14:21:51 PDT 2018 starting...
Mainboard: Mohon Peak Version 2.0
Build: SageBios_Mohon_Peak - 292
Detected C0 stepping SOC
Setting up static southbridge registers... done.
done.
RTC Init
Setting up static northbridge registers... done.
Back from rangeley_early_initialization()
Starting the Intel FSP (early_init)
ConfigureDefaultUpdData
PcdEnableIQAT 1
PcdEnableLan 1
PcdEnableLan 1
PcdEnableLan 1
PcdEnableLan 1
PcdEnableUsb20 1
PcdEnableSata2 1
PcdEnableSata3 1
default PMC_CFG reg: 0x8
abase is: 0x400
default TCO_STS reg: 0x0
default TCO_TMR reg: 0x640000
Raising Watchdog timer timeout to 3min...TCO_TMR value applied: 0x640000
done.
default TCO1_CNT reg: 0x800
TCO1_CNT value applied: 0x0
romstage_main_continue status: 0 hob_list_ptr: 7fc20000
FSP Status: 0x0
CPU id(406d8): Intel(R) Atom(TM) CPU C2358 @ 1.74GHz
AES supported, TXT NOT supported, VT supported
TODO Sideband Register DRP setting
TPM initialization.
CAR: Could not find migration base!
lpc_tpm: Read reg 0x0 returns 0x81
lpc_tpm: Write reg 0x0 with 0x2
lpc_tpm: Read reg 0x0 returns 0xa1
lpc_tpm: Write reg 0x18 with 0x40
lpc_tpm: Read reg 0x18 returns 0x40
lpc_tpm: Read reg 0x18 returns 0x40
lpc_tpm: Read reg 0x19 returns 0x8
lpc_tpm: Write reg 0x18 with 0x0
lpc_tpm: Write reg 0x18 with 0xc1
lpc_tpm: Write reg 0x18 with 0x0
lpc_tpm: Write reg 0x18 with 0x0
lpc_tpm: Write reg 0x18 with 0x0
lpc_tpm: Write reg 0x18 with 0xc
lpc_tpm: Write reg 0x18 with 0x0
lpc_tpm: Write reg 0x18 with 0x0
lpc_tpm: Read reg 0x18 returns 0x88
lpc_tpm: Read reg 0x18 returns 0x88
lpc_tpm: Read reg 0x19 returns 0x8
lpc_tpm: Write reg 0x18 with 0x0
lpc_tpm: Write reg 0x18 with 0x99
lpc_tpm: Write reg 0x18 with 0x0
lpc_tpm: Read reg 0x18 returns 0x88
lpc_tpm: Read reg 0x18 returns 0x88
lpc_tpm: Read reg 0x19 returns 0x8
lpc_tpm: Write reg 0x18 with 0x1
lpc_tpm: Read reg 0x18 returns 0x8
lpc_tpm: Read reg 0x18 returns 0x80
lpc_tpm: Read reg 0x18 returns 0x80
lpc_tpm: Write reg 0x18 with 0x20
lpc_tpm: Read reg 0x18 returns 0x80
lpc_tpm: Read reg 0x18 returns 0x90
lpc_tpm: Read reg 0x19 returns 0x8
lpc_tpm: Read reg 0x24 returns 0x0
lpc_tpm: Read reg 0x24 returns 0xc4
lpc_tpm: Read reg 0x24 returns 0x0
lpc_tpm: Read reg 0x24 returns 0x0
lpc_tpm: Read reg 0x24 returns 0x0
lpc_tpm: Read reg 0x24 returns 0xa
lpc_tpm: Read reg 0x24 returns 0x0
lpc_tpm: Read reg 0x24 returns 0x0
lpc_tpm: Read reg 0x18 returns 0x90
lpc_tpm: Read reg 0x18 returns 0x90
lpc_tpm: Read reg 0x19 returns 0x2
lpc_tpm: Read reg 0x24 returns 0x0
lpc_tpm: Read reg 0x24 returns 0x1e
lpc_tpm: Read reg 0x18 returns 0x80
lpc_tpm: Read reg 0x18 returns 0x80
lpc_tpm: Write reg 0x18 with 0x40
lpc_tpm: Read reg 0x18 returns 0x80
lpc_tpm: Write reg 0x18 with 0x40
lpc_tpm: Read reg 0x18 returns 0x40
TPM: command 0x99 returned 0x1e
TPM: Error code 0x1e.
CBMEM region 7fbe0000-7fbfffff (cbmem_check_toc)
CBMEM region 7fbe0000-7fbfffff (cbmem_initialize_empty)
Adding CBMEM entry as no. 1
Adding CBMEM entry as no. 2
Adding CBMEM entry as no. 3
Trying CBFS ramstage loader.
CBFS: loading stage fallback/ramstage @ 0x100000 (278688 bytes), entry @ 0x100000
coreboot-4.0-VELOCLOUD-EDGE-01.00.00.05 Fri Apr 27 14:21:51 PDT 2018 booting...
Enumerating buses...
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/1f0e] enabled
PCI: 00:01.0 subordinate bus PCI Express
PCI: 00:01.0 [8086/1f10] enabled
PCI: 00:02.0 subordinate bus PCI Express
PCI: 00:02.0 [8086/1f11] enabled
PCI: 00:03.0 subordinate bus PCI Express
PCI: 00:03.0 [8086/1f12] enabled
PCI: 00:04.0 subordinate bus PCI Express
PCI: 00:04.0 [8086/1f13] enabled
PCI: 00:0b.0 [8086/1f18] enabled
PCI: 00:0e.0 [8086/1f14] enabled
PCI: 00:0f.0 [8086/1f16] enabled
PCI: 00:13.0 [8086/1f15] enabled
PCI: 00:14.0 [8086/1f41] enabled
PCI: 00:14.1 [8086/1f41] enabled
PCI: 00:14.2 [8086/1f41] enabled
PCI: 00:14.3 [8086/1f41] enabled
PCI: 00:16.0 [8086/1f2c] enabled
PCI: 00:17.0 [8086/1f22] enabled
PCI: 00:18.0 [8086/1f32] enabled
PCI: 00:1f.0 [8086/1f38] enabled
PCI: 00:1f.3 [8086/1f3c] enabled
PCI: pci_scan_bus for bus 01
PCI: pci_scan_bus returning with max=001
PCI: pci_scan_bus for bus 02
PCI: pci_scan_bus returning with max=002
PCI: pci_scan_bus for bus 03
PCI: 03:00.0 [104c/8241] enabled
PCI: pci_scan_bus returning with max=003
Enabling Common Clock Configuration
ASPM: Enabled L1
PCI: pci_scan_bus for bus 04
PCI: 04:00.0 [8086/1522] enabled
PCI: 04:00.1 [8086/1522] enabled
PCI: pci_scan_bus returning with max=004
Enabling Common Clock Configuration
ASPM: Enabled L1
Enabling Common Clock Configuration
ASPM: Enabled L1
PCI: pci_scan_bus returning with max=004
done
FspNotify(EnumInitPhaseAfterPciEnumeration)
Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)
Allocating resources...
Reading resources...
SMM memory location: 0x7fe00000 SMM memory size: 0x200000
Subtracting 2M for SMM
Available memory above 4GB: 2048M
Adding PCIe config bar base=0xe0000000 size=0x10000000
SMBUS: rangeley_smbus_read_resouce
Done reading resources.
Setting resources...
SMM memory location: 0x7fe00000 SMM memory size: 0x200000
Subtracting 2M for SMM
Available memory above 4GB: 2048M
Adding PCIe config bar base=0xe0000000 size=0x10000000
PCI: 00:01.0 1c <- [0x000000ef9f - 0x000000ef9e] size 0x00000000 gran 0x0c bus 01 io
PCI: 00:01.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 mem
PCI: 00:01.0 10 <- [0x00dfe00000 - 0x00dfe1ffff] size 0x00020000 gran 0x11 mem64
PCI: 00:02.0 1c <- [0x000000ef9f - 0x000000ef9e] size 0x00000000 gran 0x0c bus 02 io
PCI: 00:02.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:02.0 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 02 mem
PCI: 00:02.0 10 <- [0x00dfe20000 - 0x00dfe3ffff] size 0x00020000 gran 0x11 mem64
PCI: 00:03.0 1c <- [0x000000ef9f - 0x000000ef9e] size 0x00000000 gran 0x0c bus 03 io
PCI: 00:03.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 03 prefmem
PCI: 00:03.0 20 <- [0x00dfc00000 - 0x00dfcfffff] size 0x00100000 gran 0x14 bus 03 mem
PCI: 00:03.0 10 <- [0x00dfe40000 - 0x00dfe5ffff] size 0x00020000 gran 0x11 mem64
PCI: 03:00.0 10 <- [0x00dfc00000 - 0x00dfc0ffff] size 0x00010000 gran 0x10 mem64
PCI: 03:00.0 18 <- [0x00dfc10000 - 0x00dfc11fff] size 0x00002000 gran 0x0d mem64
PCI: 00:04.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 04 io
PCI: 00:04.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 04 prefmem
PCI: 00:04.0 20 <- [0x00dfd00000 - 0x00dfdfffff] size 0x00100000 gran 0x14 bus 04 mem
PCI: 00:04.0 10 <- [0x00dfe60000 - 0x00dfe7ffff] size 0x00020000 gran 0x11 mem64
PCI: 04:00.0 10 <- [0x00dfd00000 - 0x00dfd1ffff] size 0x00020000 gran 0x11 mem
PCI: 04:00.0 18 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io
PCI: 04:00.0 1c <- [0x00dfd40000 - 0x00dfd43fff] size 0x00004000 gran 0x0e mem
PCI: 04:00.1 10 <- [0x00dfd20000 - 0x00dfd3ffff] size 0x00020000 gran 0x11 mem
PCI: 04:00.1 18 <- [0x0000001020 - 0x000000103f] size 0x00000020 gran 0x05 io
PCI: 04:00.1 1c <- [0x00dfd44000 - 0x00dfd47fff] size 0x00004000 gran 0x0e mem
PCI: 00:0b.0 18 <- [0x00dfe80000 - 0x00dfe9ffff] size 0x00020000 gran 0x11 mem64
PCI: 00:0b.0 20 <- [0x00dff20000 - 0x00dff23fff] size 0x00004000 gran 0x0e mem64
PCI: 00:13.0 10 <- [0x00dff35000 - 0x00dff353ff] size 0x00000400 gran 0x0a mem64
PCI: 00:14.0 10 <- [0x00dfea0000 - 0x00dfebffff] size 0x00020000 gran 0x11 mem64
PCI: 00:14.0 18 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io
PCI: 00:14.0 20 <- [0x00dff24000 - 0x00dff27fff] size 0x00004000 gran 0x0e mem64
PCI: 00:14.1 10 <- [0x00dfec0000 - 0x00dfedffff] size 0x00020000 gran 0x11 mem64
PCI: 00:14.1 18 <- [0x0000002020 - 0x000000203f] size 0x00000020 gran 0x05 io
PCI: 00:14.1 20 <- [0x00dff28000 - 0x00dff2bfff] size 0x00004000 gran 0x0e mem64
PCI: 00:14.2 10 <- [0x00dfee0000 - 0x00dfefffff] size 0x00020000 gran 0x11 mem64
PCI: 00:14.2 18 <- [0x0000002040 - 0x000000205f] size 0x00000020 gran 0x05 io
PCI: 00:14.2 20 <- [0x00dff2c000 - 0x00dff2ffff] size 0x00004000 gran 0x0e mem64
PCI: 00:14.3 10 <- [0x00dff00000 - 0x00dff1ffff] size 0x00020000 gran 0x11 mem64
PCI: 00:14.3 18 <- [0x0000002060 - 0x000000207f] size 0x00000020 gran 0x05 io
PCI: 00:14.3 20 <- [0x00dff30000 - 0x00dff33fff] size 0x00004000 gran 0x0e mem64
PCI: 00:16.0 10 <- [0x00dff35400 - 0x00dff357ff] size 0x00000400 gran 0x0a mem
PCI: 00:17.0 10 <- [0x00000020c0 - 0x00000020c7] size 0x00000008 gran 0x03 io
PCI: 00:17.0 14 <- [0x00000020e0 - 0x00000020e3] size 0x00000004 gran 0x02 io
PCI: 00:17.0 18 <- [0x00000020c8 - 0x00000020cf] size 0x00000008 gran 0x03 io
PCI: 00:17.0 1c <- [0x00000020e4 - 0x00000020e7] size 0x00000004 gran 0x02 io
PCI: 00:17.0 20 <- [0x0000002080 - 0x000000209f] size 0x00000020 gran 0x05 io
PCI: 00:17.0 24 <- [0x00dff34000 - 0x00dff347ff] size 0x00000800 gran 0x0b mem
PCI: 00:18.0 10 <- [0x00000020d0 - 0x00000020d7] size 0x00000008 gran 0x03 io
PCI: 00:18.0 14 <- [0x00000020e8 - 0x00000020eb] size 0x00000004 gran 0x02 io
PCI: 00:18.0 18 <- [0x00000020d8 - 0x00000020df] size 0x00000008 gran 0x03 io
PCI: 00:18.0 1c <- [0x00000020ec - 0x00000020ef] size 0x00000004 gran 0x02 io
PCI: 00:18.0 20 <- [0x00000020a0 - 0x00000020bf] size 0x00000020 gran 0x05 io
PCI: 00:18.0 24 <- [0x00dff34800 - 0x00dff34fff] size 0x00000800 gran 0x0b mem
PCI: 00:1f.3 10 <- [0x00dff35800 - 0x00dff3581f] size 0x00000020 gran 0x05 mem
Done setting resources.
Done allocating resources.
Enabling resources...
PCI: 00:00.0 subsystem <- 0000/0000
PCI: 00:00.0 cmd <- 07
PCI: 00:01.0 bridge ctrl <- 0003
PCI: 00:01.0 cmd <- 02
PCI: 00:02.0 bridge ctrl <- 0003
PCI: 00:02.0 cmd <- 02
PCI: 00:03.0 bridge ctrl <- 0003
PCI: 00:03.0 cmd <- 06
PCI: 00:04.0 bridge ctrl <- 0003
PCI: 00:04.0 cmd <- 07
PCI: 00:0b.0 subsystem <- 0000/0000
PCI: 00:0b.0 cmd <- 102
PCI: 00:0e.0 subsystem <- 0000/0000
PCI: 00:0e.0 cmd <- 00
PCI: 00:0f.0 cmd <- 04
PCI: 00:13.0 subsystem <- 0000/0000
PCI: 00:13.0 cmd <- 106
PCI: 00:14.0 subsystem <- 0000/0000
PCI: 00:14.0 cmd <- 107
PCI: 00:14.1 subsystem <- 0000/0000
PCI: 00:14.1 cmd <- 103
PCI: 00:14.2 subsystem <- 0000/0000
PCI: 00:14.2 cmd <- 103
PCI: 00:14.3 subsystem <- 0000/0000
PCI: 00:14.3 cmd <- 103
PCI: 00:16.0 subsystem <- 0000/0000
PCI: 00:16.0 cmd <- 102
PCI: 00:17.0 subsystem <- 0000/0000
PCI: 00:17.0 cmd <- 103
PCI: 00:18.0 subsystem <- 0000/0000
PCI: 00:18.0 cmd <- 103
soc_decode_init
PCI: 00:1f.0 subsystem <- 0000/0000
PCI: 00:1f.0 cmd <- 107
PCI: 00:1f.3 subsystem <- 0000/0000
SMBUS: smbus_set_subsystem
PCI: 00:1f.3 cmd <- 103
PCI: 03:00.0 cmd <- 02
PCI: 04:00.0 cmd <- 03
PCI: 04:00.1 cmd <- 03
done.
Initializing devices...
Root Device init
CPU_CLUSTER: 0 init
start_eip=0x00001000, code_size=0x00000031
Initializing CPU #0
CPU: vendor Intel device 406d8
CPU: family 06, model 4d, stepping 08
Enabling cache
CPU: Intel(R) Atom(TM) CPU C2358 @ 1.74GHz.
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local apic... apic_id: 0x00 done.
Enabling VMX
CPU: 0 has 2 cores, 1 threads per core
CPU: 0 has core 2
CPU #0 initialized
Waiting for 1 CPUS to stop
Initializing CPU #1
CPU: vendor Intel device 406d8
CPU: family 06, model 4d, stepping 08
Enabling cache
CPU: Intel(R) Atom(TM) CPU C2358 @ 1.74GHz.
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Setting up local apic... apic_id: 0x02 done.
Enabling VMX
CPU #1 initialized
All AP CPUs stopped (1218 loops)
PCI: 00:00.0 init
PCI: 00:0b.0 init
PCI: 00:0e.0 init
PCI: 00:0f.0 init
PCI: 00:13.0 init
PCI: 00:14.0 init
PCI: 00:14.1 init
PCI: 00:14.2 init
PCI: 00:14.3 init
PCI: 00:16.0 init
PCI: 00:17.0 init
SATA: Initializing...
SATA: Controller in AHCI mode.
ABAR: DFF34000
PCI: 00:18.0 init
SATA: Initializing...
SATA: Controller in AHCI mode.
ABAR: DFF34800
PCI: 00:1f.0 init
soc: lpc_init
Southbridge APIC ID = 2
5: Disabled, skip it
6: Disabled, skip it
7: Disabled, skip it
8: Disabled, skip it
9: Disabled, skip it
10: Disabled, skip it
12: Disabled, skip it
13: Disabled, skip it
16: Disabled, skip it
17: Disabled, skip it
18: Disabled, skip it
21: Disabled, skip it
25: Disabled, skip it
26: Disabled, skip it
27: Disabled, skip it
28: Disabled, skip it
29: Disabled, skip it
30: Disabled, skip it
PCI_CFG IRQ: Write PCI config space IRQ assignments
PCI_CFG IRQ: Finished writing PCI config space IRQ assignments
NMI sources disabled.
PCI: 03:00.0 init
PCI: 04:00.0 init
PCI: 04:00.1 init
Devices initialized
CBMEM region 7fbe0000-7fbfffff (cbmem_locate_table)
CBMEM region 7fbe0000-7fbfffff (cbmem_check_toc)
Adding CBMEM entry as no. 4
Moving GDT to 7fbe0800...ok
Finalize devices...
Devices finalized
=== FSP HOB Data Structure ===
FSP Hoblistptr: 0x7fc20000
HOB 0x7fc20000 is an EFI_HOB_TYPE_HANDOFF (type 0x1)
HOB 0x7fc20038 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4)
HOB 0x7fc20158 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4)
HOB 0x7fc204f0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
HOB 0x7fc20508 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
HOB 0x7fc20518 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
HOB 0x7fc20878 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4)
HOB 0x7fc20920 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
HOB 0x7fc20938 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
HOB 0x7fc20988 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
HOB 0x7fc209a0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
HOB 0x7fc20b18 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
HOB 0x7fc20b30 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
HOB 0x7fc20b78 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
HOB 0x7fc20b88 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
HOB 0x7fc20b98 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
HOB 0x7fc20bb0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
HOB 0x7fc20bc0 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3)
HOB 0x7fc20bf0 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3)
HOB 0x7fc20c20 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3)
HOB 0x7fc20c50 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3)
HOB 0x7fc20c80 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4)
HOB 0x7fc20ce0 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4)
HOB 0x7fc20d18 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3)
HOB 0x7fc20d48 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3)
HOB 0x7fc20d78 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4)
HOB 0x7fc21728 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4)
HOB 0x7fc239a8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
HOB 0x7fc239d8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
HOB 0x7fc23a08 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
HOB 0x7fc23a38 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4)
HOB 0x7fc27a50 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4)
HOB 0x7fc29ce8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
HOB 0x7fc29d18 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4)
HOB 0x7fc29ec8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
HOB 0x7fc29ef8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
HOB 0x7fc29f28 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
HOB 0x7fc29f58 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
HOB 0x7fc29f70 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
HOB 0x7fc29fa0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
HOB 0x7fc29fd0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
HOB 0x7fc2a000 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
HOB 0x7fc2a030 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
HOB 0x7fc2a060 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
HOB 0x7fc2a090 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
HOB 0x7fc2a0a0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
HOB 0x7fc2a0d0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
HOB 0x7fc2a100 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
HOB 0x7fc2a130 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
HOB 0x7fc2a538 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
HOB 0x7fc2a568 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7)
HOB 0x7fc2a678 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
HOB 0x7fc2a6a8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
HOB 0x7fc2a6d8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2)
HOB 0x7fc2a708 is an EFI_HOB_TYPE_END_OF_HOB_LIST (type 0xffff)
=== End of FSP HOB Data Structure ===
Copying Interrupt Routing Table to 0x000f0000... done.
Adding CBMEM entry as no. 5
Copying Interrupt Routing Table to 0x7fbe0a00... done.
PIRQ table: 320 bytes.
MP_Tables: Start writing the MP_Tables at 0xf0400
MP_Tables: Finished writing the MP_Table from 0x000f0410 - 0x000f0584
Adding CBMEM entry as no. 6
MP_Tables: Start writing the MP_Tables at 0x7fbe1a00
MP_Tables: Finished writing the MP_Table from 0x7fbe1a10 - 0x7fbe1b84
MP table: 388 bytes.
Adding CBMEM entry as no. 7
ACPI: Writing ACPI tables at 7fbe2a00.
ACPI: * FACS
ACPI: * DSDT
ACPI: * FADT
ACPI: added table 1/32, length now 40
ACPI: * SPCR
ACPI: added table 2/32, length now 44
ACPI: * HPET
ACPI: added table 3/32, length now 48
ACPI: * MADT
ACPI: added table 4/32, length now 52
ACPI: * MCFG
ACPI: added table 5/32, length now 56
ACPI: Patching up global NVS in DSDT at offset 0x025e -> 0x7fbe5230
Adding CBMEM entry as no. 8
ACPI: * DSDT @ 7fbe2c50 Length 23a1
ACPI: * SSDT
Found 1 CPU(s) with 2 core(s) each.
Turbo is available but hidden
PSS: 2100MHz power 8 control 0x1500 status 0x1500
PSS: 1800MHz power 0 control 0x1200 status 0x1200
PSS: 1600MHz power 0 control 0x1000 status 0x1000
PSS: 1400MHz power 0 control 0xe00 status 0xe00
PSS: 2100MHz power 8 control 0x1500 status 0x1500
PSS: 1800MHz power 0 control 0x1200 status 0x1200
PSS: 1600MHz power 0 control 0x1000 status 0x1000
PSS: 1400MHz power 0 control 0xe00 status 0xe00
ACPI: added table 6/32, length now 60
current = 7fbe5820
ACPI: done.
ACPI tables: 11808 bytes.
Adding CBMEM entry as no. 9
smbios_write_tables: 7fbee000
Probing SPI flash to get ready for SMBIOS update SF: Detected W25Q64 with page size 1000, total 800000
SN:VC05200064294
BSN:
Board Version:2.8
UUID:▒▒▒M▒f▒@▒▒▒':=
BSN:
BSN:1909DF00554
Board Version:2.8
Root Device (Intel Mohon Peak)
CPU_CLUSTER: 0 (Intel Rangeley Northbridge)
APIC: 00 (Socket rPGA989 CPU)
APIC: acac (unknown)
DOMAIN: 0000 (Intel Rangeley Northbridge)
PCI: 00:00.0 (Intel Rangeley Northbridge)
PCI: 00:01.0 (Intel Rangeley Northbridge)
PCI: 00:02.0 (Intel Rangeley Northbridge)
PCI: 00:03.0 (Intel Rangeley Northbridge)
PCI: 00:04.0 (Intel Rangeley Northbridge)
PCI: 00:0b.0 (Intel Rangeley Southbridge)
PCI: 00:0e.0 (Intel Rangeley Southbridge)
PCI: 00:13.0 (Intel Rangeley Southbridge)
PCI: 00:14.0 (Intel Rangeley Southbridge)
PCI: 00:14.1 (Intel Rangeley Southbridge)
PCI: 00:14.2 (Intel Rangeley Southbridge)
PCI: 00:14.3 (Intel Rangeley Southbridge)
PCI: 00:16.0 (Intel Rangeley Southbridge)
PCI: 00:17.0 (Intel Rangeley Southbridge)
PCI: 00:18.0 (Intel Rangeley Southbridge)
PCI: 00:1f.0 (Intel Rangeley Southbridge)
PCI: 00:1f.3 (Intel Rangeley Southbridge)
PCI: 00:0f.0 (unknown)
PCI: 03:00.0 (unknown)
PCI: 04:00.0 (unknown)
PCI: 04:00.1 (unknown)
APIC: 02 (unknown)
SMBIOS tables: 428 bytes.
Adding CBMEM entry as no. 10
Writing table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum 981f
Table forward entry ends at 0x00000528.
... aligned to 0x00001000
Writing coreboot table at 0x7fbee800
rom_table_end = 0x7fbee800
... aligned to 0x7fbf0000
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000a0000-00000000000fffff: RESERVED
3. 0000000000100000-000000007fbdffff: RAM
4. 000000007fbe0000-000000007fbfffff: CONFIGURATION TABLES
5. 000000007fc00000-000000007fdfffff: RESERVED
6. 00000000e0000000-00000000efffffff: RESERVED
7. 00000000fee00000-00000000fee00fff: RESERVED
8. 0000000100000000-000000017fffffff: RAM
Wrote coreboot table at: 7fbee800, 0x1b8 bytes, checksum a5e
coreboot table: 464 bytes.
FREE SPACE 0. 7fbf6800 00009800
CAR GLOBALS 1. 7fbe0200 00000200
484f4221 2. 7fbe0400 00000200
ROMSTAGE 3. 7fbe0600 00000200
GDT 4. 7fbe0800 00000200
IRQ TABLE 5. 7fbe0a00 00001000
SMP TABLE 6. 7fbe1a00 00001000
ACPI 7. 7fbe2a00 0000b400
GNVS PTR 8. 7fbede00 00000200
SMBIOS 9. 7fbee000 00000800
COREBOOT 10. 7fbee800 00008000
Enabling USB3 clock..
do_smbus_read_byte() snbus_base=0xefa0, devce=0x69, addr=0x82
read address 0x82: 0xff
status = 0
Enabling Spread Spectrum..
do_smbus_read_byte() snbus_base=0xefa0, devce=0x69, addr=0x84
read address 0x84: 0xfd
status = 0
CBFS: located payload @ ffc2a0b8, 44159 bytes.
Loading segment from rom address 0xffc2a0b8
code (compression=1)
New segment dstaddr 0xea8e4 memsize 0x1571c srcaddr 0xffc2a0f0 filesize 0xac47
(cleaned up) New segment addr 0xea8e4 size 0x1571c offset 0xffc2a0f0 filesize 0xac47
Loading segment from rom address 0xffc2a0d4
Entry Point 0x000fccc5
Payload being loaded below 1MiB without region being marked as RAM usable.
Loading Segment: addr: 0x00000000000ea8e4 memsz: 0x000000000001571c filesz: 0x000000000000ac47
Post relocation: addr: 0x00000000000ea8e4 memsz: 0x000000000001571c filesz: 0x000000000000ac47
using LZMA
dest 000ea8e4, end 00100000, bouncebuffer 7fb57000
FspNotify(EnumInitPhaseReadyToBoot)
FSP Header Version: 1
FSP Revision: 1.112
Returned from FspNotify(EnumInitPhaseReadyToBoot)
Jumping to boot code at 000fccc5
SeaBIOS (version SageBIOS-20180426_163332-jordan-ubuntu-virtualBox)
Attempting to find coreboot table
Found coreboot table forwarder.
Now attempting to find coreboot memory map
Found mainboard Intel Mohon Peak
malloc preinit
Relocating init from 0x000eb8a0 to 0x7fb98b80 (size 29632)
malloc init
Found CBFS header at 0xfffffb90
Add romfile: cmos_layout.bin (size=1352)
Add romfile: fallback/romstage (size=35664)
Add romfile: pci8086,1f41.rom (size=71168)
Add romfile: fallback/ramstage (size=63672)
Add romfile: fallback/payload (size=44159)
Add romfile: config (size=4966)
Add romfile: bootorder (size=355)
Add romfile: (size=3251416)
Add romfile: mrc.cache (size=65536)
Add romfile: cpu_microcode_blob.bin (size=84992)
Add romfile: (size=45912)
Add romfile: fsp.bin (size=389120)
Add romfile: (size=133976)
init ivt
init bda
Copying data 355@0xffc36128 to 355@0x7fb97ef0
boot order:
1:
2: /pci@i0cf8/usb@16/hub@1/usb-*@1
3: /pci@i0cf8/usb@16/hub@1/usb-*@2
4: /pci@i0cf8/pci-bridge@3/usb@0/usb-*@1
5: /pci@i0cf8/pci-bridge@3/usb@0/usb-*@2
6: /pci@i0cf8/pci-bridge@3/usb@0/usb-*@3
7: /pci@i0cf8/pci-bridge@3/usb@0/usb-*@4
8: /pci@i0cf8/usb@16/hub@1/usb-*@4
9: !/pci@i0cf8/*@14
10: !/pci@i0cf8/*@14,1
11: !/pci@i0cf8/*@14,2
12: !/pci@i0cf8/*@14,3
13: !/pci@i0cf8/*@17/drive@0/disk@0
14:
init bios32
init PMM
init PNPBIOS table
init keyboard
init mouse
init pic
math cp init
CPU Mhz=1746
init timer
PCI probe
Found 21 PCI devices (max PCI bus is 04)
Relocating coreboot bios tables
Copying MPTABLE from 0x7fbe1a00/7fbe1a10 to 0x000f2ad0 with length 184
Copying ACPI RSDP from 0x7fbe2a00 to 0x000f2aa0
Copying SMBIOS entry point from 0x7fbee000 to 0x000f2a80
Using pmtimer, ioport 0x408
Scan for VGA option rom
/7fb96000\ Start thread
|7fb96000| init usb
|7fb96000| XHCI init on dev 03:00.0: regs @ 0xdfc00000, 4 ports, 64 slots, 64 byte contexts
|7fb96000| XHCI extcap 0x1 @ dfc009c0
|7fb96000| XHCI protocol USB 2.00, 2 ports (offset 1), def 1
|7fb96000| XHCI protocol USB 3.00, 2 ports (offset 3), def 0
/7fb95000\ Start thread
|7fb95000| configure_xhci: resetting
init serial
Found 2 serial ports
init ahci
ebda moved from 9f000 to 9e800
AHCI controller at 17.0, iobase dff34000, irq 15
AHCI: cap 0xc720ff01, ports_impl 0x3
/7fb93000\ Start thread
|7fb93000| AHCI/0: probing
|7fb96000| EHCI init on dev 00:16.0 (regs=0xdff35420)
/7fb92000\ Start thread
|7fb95000| configure_xhci: setup 1 scratch pad buffers
/7fb91000\ Start thread
|7fb91000| AHCI/1: probing
|7fb93000| AHCI/0: link down
AHCI controller at 18.0, iobase dff34800, irq 10
AHCI: cap 0xc3309f01, ports_impl 0x3
/7fb8f000\ Start thread
|7fb8f000| AHCI/0: probing
|7fb91000| AHCI/1: link down
\7fb93000/ End thread
\7fb96000/ End thread
/7fb96000\ Start thread
/7fb93000\ Start thread
/7fb8e000\ Start thread
|7fb8e000| AHCI/1: probing
|7fb8f000| AHCI/0: link down
\7fb91000/ End thread
/7fb91000\ Start thread
/7fb8d000\ Start thread
uart_check_keystrokes: error too many bytes are available
so the last line until it loops again is : uart_check_keystrokes: error too many bytes are available
