Support for Xiaomi Wifi R3P Pro?


#182

@ilyas it was the only way to earn schematics)))


#183

@pellmen i have a favor to ask you... this "panic with micron chip" we had earlier is bothering me... i've hoped I could track it down to a bug in my code (or somewhere) but it just doesn't make sense. I've seen the posts on 4pda, about how a custom pandorabox build worked, but that doesn't really make sense to me either (ie, needing to modify uboot seems strange).

looking at the bootlogs (https://4pda.ru/forum/index.php?showtopic=810698&view=findpost&p=82662335) and particularly the bit where it prints out the mtd partition table, it looks like they end the partition table at 0x00000f200000 while on my bits I end the partition table at 0x00000ff80000 ... I wonder if that's the trick to get it to work on Micron chips (ie, end the partition table early). (BTW, one "technical document" talks about reserving 2% of space for bad blocks... -2% of 256MB would end us around 0xfa00000 (which is still earlier than 0xf200000)...

so now for my "favor"... I really want to make "openwrt on mir3p" a success (i don't know if you can tell already)... and it irks me to know that users with micron chips won't be able to install my bits (at least it seems that way)... do you think "skull999666" (who reported the panic) or "toikvl" (apparently he also has a micron chip) would be able to help out (since I don't have one I can test with)...

what I'd like to see (perhaps most importantly) is the bootlog from "stock" xiaomi firmware booting the mir3p with a micron chip... I want to know where the mtd table ends on stock/micron... and if it ends somewhere different (like 0xf200000), if they would be willing to test custom bits? i got the official go-ahead to release two versions (for the ESMT chip and for the Micron chip) of openwrt/mir3p but I first want to see if I can figure out what's wrong.

I guess I could post to 4pda but I'm shy because I don't speak russian :wink: and i don't know anyone there.. but if you think it's best for me to post there directly, I'll do that.


#184

@ilyas, done. I'll add link with log to this message when somebody will provide it.

Here's the link to log with stock on micron with bads from creator of pandora: https://downloads.pangubox.com/刷机说明/小米路由器Pro/bootlog.txt


#185

@pellmen thanks! (and turns out my "solution" isn't going to work... how annoying...)


#186

EDIT: a bug crept in. build is bad. pci is broken, wifi doesn't work. don't install. uploading new build in a few minutes.
EDIT2: bug fixed. new bits uploaded to the same location.

pushed out new build. pretty much the same as the last (I don't think I changed anything). just sync'ed with openwrt/master (kernel 4.14.104) and built packages for some commonly requested features. @splash i have l2tp (btw, did you install the previous packages I put up there?) and @pjgowtham i have samba 3.6 ... (and a couple of others requested on 4pda) @pellmen i added russian language support to luci (again)


#187

I've noticed that, in the latest fixed build, changes to WiFi configuration (SSID, authentication, etc.) start to work only after router reboot.
"save and apply" nor "save" and "reload config" in MTK tab does not seem to have effect.


#188

@tekaeren I did disable and enable the interface again. It worked fine. You were right. "save and apply" function is supposed to restart the interface.

@ilyas Unbricked my router with UART and TFTFP'd the intramfs file from your latest release and it worked like a charm. I couldn't flash it back to stock though. I must have messed up something during initial install. Is there any other way to flash stock with UART instead of using a flash drive?

The latest release has wifi working and ill update here once i get samba working. The USB port and Wifi are working though.

EDIT: The learning curve is surely steep
I still see apclii0/apcli0 ( Don't know if i am supposed to see that)

Bootlog of the xiaomi stock usb recovery option not working :

===================================================================
                MT7621   stage1 code 10:33:11 (ASIC)
                CPU=50000000 HZ BUS=16666666 HZ
==================================================================
Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x11100000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-1200Mhz ===
PLL3 FB_DL: 0x7, 1/0 = 587/437 1D000000
PLL4 FB_DL: 0x8, 1/0 = 576/448 21000000
PLL2 FB_DL: 0x1c, 1/0 = 535/489 71000000
do DDR setting..[00320381]
Apply DDR3 Setting...(use customer AC)
          0    8   16   24   32   40   48   56   64   72   80   88   96  104  112  120
      --------------------------------------------------------------------------------
0000:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0001:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0002:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0003:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0004:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0005:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0006:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0007:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0008:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0009:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000E:|    0    0    0    0    0    0    0    0    0    0    1    1    1    1    1    1
000F:|    0    0    0    0    1    1    1    1    1    1    1    1    1    1    1    0
0010:|    1    1    1    1    1    1    1    1    1    0    0    0    0    0    0    0
0011:|    1    1    1    1    0    0    0    0    0    0    0    0    0    0    0    0
0012:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0013:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0014:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0015:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0016:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0017:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0018:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0019:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001E:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001F:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
rank 0 coarse = 15
rank 0 fine = 72
B:|    0    0    0    0    0    0    0    0    1    1    1    0    0    0    0    0
opt_dle value:9
DRAMC_R0DELDLY[018]=00001C1B
==================================================================
                RX      DQS perbit delay software calibration
==================================================================
1.0-15 bit dq delay value
==================================================================
bit|     0  1  2  3  4  5  6  7  8  9
--------------------------------------
0 |    6 5 5 6 5 5 5 3 3 6
10 |    6 7 6 8 6 7
--------------------------------------

==================================================================
2.dqs window
x=pass dqs delay value (min~max)center
y=0-7bit DQ of every group
input delay:DQS0 =27 DQS1 = 28
==================================================================
bit     DQS0     bit      DQS1
0  (1~52)26  8  (1~52)26
1  (1~52)26  9  (1~53)27
2  (0~52)26  10  (0~55)27
3  (1~54)27  11  (1~54)27
4  (1~53)27  12  (0~56)28
5  (1~52)26  13  (1~52)26
6  (1~50)25  14  (1~56)28
7  (1~53)27  15  (1~56)28
==================================================================
3.dq delay value last
==================================================================
bit|    0  1  2  3  4  5  6  7  8   9
--------------------------------------
0 |    7 6 6 6 5 6 7 3 5 7
10 |    7 8 6 10 6 7
==================================================================
==================================================================
     TX  perbyte calibration
==================================================================
DQS loop = 15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqsdly_pass[0]=15,  finish count=1
dqs_perbyte_dly.last_dqsdly_pass[1]=15,  finish count=2
DQ loop=15, cmp_err_1 = ffff0080
dqs_perbyte_dly.last_dqdly_pass[1]=15,  finish count=1
DQ loop=14, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqdly_pass[0]=14,  finish count=2
byte:0, (DQS,DQ)=(8,8)
byte:1, (DQS,DQ)=(8,8)
20,data:88
[EMI] DRAMC calibration passed

===================================================================
                MT7621   stage1 code done
                CPU=50000000 HZ BUS=16666666 HZ
===================================================================


U-Boot 1.1.3 (Jan 19 2017 - 17:14:12)

Board: Ralink APSoC DRAM:  256 MB
Power on memory test. Memory size= 256 MB...OK!
relocate_code Pointer at: 8ffac000

Config XHCI 40M PLL
Allocate 16 byte aligned buffer: 8ffe0050
Enable NFI Clock
# MTK NAND # : Use HW ECC
NAND ID [C8 DA 90 95 44]
Device found in MTK table, ID: c8da, EXT_ID: 909544
Support this Device in MTK table! c8da
select_chip
[NAND]select ecc bit:4, sparesize :64 spare_per_sector=16
Signature matched and data read!
load_fact_bbt success 2047
load fact bbt success
[mtk_nand] probe successfully!
mtd->writesize=2048 mtd->oobsize=64,    mtd->erasesize=131072  devinfo.iowidth=8
..============================================
Ralink UBoot Version: 5.0.0.0
--------------------------------------------
ASIC MT7621A DualCore (MAC to MT7530 Mode)
DRAM_CONF_FROM: Auto-Detection
DRAM_TYPE: DDR3
DRAM bus: 16 bit
Xtal Mode=3 OCP Ratio=1/3
Flash component: NAND Flash
Date:Jan 19 2017  Time:17:14:12
============================================
icache: sets:256, ways:4, linesz:32 ,total:32768
dcache: sets:256, ways:4, linesz:32 ,total:32768

 ##### The CPU freq = 880 MHZ ####
 estimate memory size =256 Mbytes
#Reset_MT7530
set LAN/WAN LLLLW

Please choose the operation:
   1: Load system code to SDRAM via TFTP.
   2: Load system code then write to Flash via TFTP.
   3: Boot system code via Flash (default).
   4: Entr boot command line interface.
   7: Load Boot Loader code then write to Flash via Serial.
   9: Load Boot Loader code then write to Flash via TFTP.                     3
You choosed 4
                                                                              0


4: System Enter Boot Command Line Interface.

U-Boot 1.1.3 (Jan 19 2017 - 17:14:12)
MT7621 # setenv flag_try_sys1_failed 0
MT7621 # setenv flag_try_sys2_failed 1
MT7621 # setenv uart_en 1
MT7621 # saveenv
Saving Environment to NAND Flash...
..Erasing NAND Flash...
ranand_erase: start:40000, len:20000
.Writing to NAND Flash...
done
MT7621 # reset

===================================================================
                MT7621   stage1 code 10:33:11 (ASIC)
                CPU=50000000 HZ BUS=16666666 HZ
==================================================================
Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x11100000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-1200Mhz ===
PLL3 FB_DL: 0x7, 1/0 = 601/423 1D000000
PLL4 FB_DL: 0x8, 1/0 = 605/419 21000000
PLL2 FB_DL: 0x1c, 1/0 = 665/359 71000000
do DDR setting..[00320381]
Apply DDR3 Setting...(use customer AC)
          0    8   16   24   32   40   48   56   64   72   80   88   96  104  112  120
      --------------------------------------------------------------------------------
0000:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0001:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0002:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0003:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0004:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0005:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0006:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0007:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0008:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0009:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    1
000E:|    0    0    0    0    0    0    0    0    0    0    1    1    1    1    1    1
000F:|    0    0    0    0    0    1    1    1    1    1    1    1    1    1    0    0
0010:|    1    1    1    1    1    1    1    1    1    0    0    0    0    0    0    0
0011:|    1    1    1    1    0    0    0    0    0    0    0    0    0    0    0    0
0012:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0013:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0014:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0015:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0016:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0017:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0018:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0019:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001E:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001F:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
rank 0 coarse = 16
rank 0 fine = 32
B:|    0    0    0    0    0    0    0    0    1    1    1    0    0    0    0    0
opt_dle value:9
DRAMC_R0DELDLY[018]=00001D1B
==================================================================
                RX      DQS perbit delay software calibration
==================================================================
1.0-15 bit dq delay value
==================================================================
bit|     0  1  2  3  4  5  6  7  8  9
--------------------------------------
0 |    6 5 5 6 5 5 5 3 3 6
10 |    7 7 6 8 6 7
--------------------------------------

==================================================================
2.dqs window
x=pass dqs delay value (min~max)center
y=0-7bit DQ of every group
input delay:DQS0 =27 DQS1 = 29
==================================================================
bit     DQS0     bit      DQS1
0  (1~51)26  8  (0~52)26
1  (1~52)26  9  (1~53)27
2  (1~52)26  10  (3~56)29
3  (1~53)27  11  (1~53)27
4  (1~52)26  12  (0~55)27
5  (1~54)27  13  (1~52)26
6  (1~50)25  14  (1~56)28
7  (1~51)26  15  (1~55)28
==================================================================
3.dq delay value last
==================================================================
bit|    0  1  2  3  4  5  6  7  8   9
--------------------------------------
0 |    7 6 6 6 6 5 7 4 6 8
10 |    7 9 8 11 7 8
==================================================================
==================================================================
     TX  perbyte calibration
==================================================================
DQS loop = 15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqsdly_pass[0]=15,  finish count=1
dqs_perbyte_dly.last_dqsdly_pass[1]=15,  finish count=2
DQ loop=15, cmp_err_1 = ffff0080
dqs_perbyte_dly.last_dqdly_pass[1]=15,  finish count=1
DQ loop=14, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqdly_pass[0]=14,  finish count=2
byte:0, (DQS,DQ)=(8,8)
byte:1, (DQS,DQ)=(8,8)
20,data:88
[EMI] DRAMC calibration passed

===================================================================
                MT7621   stage1 code done
                CPU=50000000 HZ BUS=16666666 HZ
===================================================================


U-Boot 1.1.3 (Jan 19 2017 - 17:14:12)

Board: Ralink APSoC DRAM:  256 MB
Power on memory test. Memory size= 256 MB...OK!
relocate_code Pointer at: 8ffac000

Config XHCI 40M PLL
******************************
Software System Reset Occurred
******************************
Allocate 16 byte aligned buffer: 8ffe0050
Enable NFI Clock
# MTK NAND # : Use HW ECC
NAND ID [C8 DA 90 95 44]
Device found in MTK table, ID: c8da, EXT_ID: 909544
Support this Device in MTK table! c8da
select_chip
[NAND]select ecc bit:4, sparesize :64 spare_per_sector=16
Signature matched and data read!
load_fact_bbt success 2047
load fact bbt success
[mtk_nand] probe successfully!
mtd->writesize=2048 mtd->oobsize=64,    mtd->erasesize=131072  devinfo.iowidth=8
..============================================
Ralink UBoot Version: 5.0.0.0
--------------------------------------------
ASIC MT7621A DualCore (MAC to MT7530 Mode)
DRAM_CONF_FROM: Auto-Detection
DRAM_TYPE: DDR3
DRAM bus: 16 bit
Xtal Mode=3 OCP Ratio=1/3
Flash component: NAND Flash
Date:Jan 19 2017  Time:17:14:12
============================================
icache: sets:256, ways:4, linesz:32 ,total:32768
dcache: sets:256, ways:4, linesz:32 ,total:32768

 ##### The CPU freq = 880 MHZ ####
 estimate memory size =256 Mbytes
#Reset_MT7530
set LAN/WAN LLLLW

Please choose the operation:
   1: Load system code to SDRAM via TFTP.
   2: Load system code then write to Flash via TFTP.
   3: Boot system code via Flash (default).
   4: Entr boot command line interface.
   7: Load Boot Loader code then write to Flash via Serial.
   9: Load Boot Loader code then write to Flash via TFTP.                     0
Booting System 1
..Erasing NAND Flash...
ranand_erase: start:40000, len:20000
.Writing to NAND Flash...
done

3: System Boot system code via Flash.
## Booting image at bc200000 ...
   Image Name:   MIPS OpenWrt Linux-4.14.104
   Image Type:   MIPS Linux Kernel Image (lzma compressed)
   Data Size:    6302233 Bytes =  6 MB
   Load Address: 80001000
   Entry Point:  80001000
.................................................................................................   Verifying Checksum ... Bad Data CRC
..Erasing NAND Flash...
ranand_erase: start:40000, len:20000
.Writing to NAND Flash...
done

===================================================================
                MT7621   stage1 code 10:33:11 (ASIC)
                CPU=50000000 HZ BUS=16666666 HZ
==================================================================
Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x11100000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-1200Mhz ===
PLL3 FB_DL: 0x6, 1/0 = 529/495 19000000
PLL4 FB_DL: 0x8, 1/0 = 569/455 21000000
PLL2 FB_DL: 0x1c, 1/0 = 729/295 71000000
do DDR setting..[00320381]
Apply DDR3 Setting...(use customer AC)
          0    8   16   24   32   40   48   56   64   72   80   88   96  104  112  120
      --------------------------------------------------------------------------------
0000:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0001:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0002:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0003:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0004:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0005:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0006:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0007:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0008:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0009:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000E:|    0    0    0    0    0    0    0    0    0    0    1    1    1    1    1    1
000F:|    0    0    0    0    1    1    1    1    1    1    1    1    1    1    1    0
0010:|    1    1    1    1    1    1    1    1    1    0    0    0    0    0    0    0
0011:|    1    1    1    1    0    0    0    0    0    0    0    0    0    0    0    0
0012:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0013:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0014:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0015:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0016:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0017:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0018:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0019:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001E:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001F:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
rank 0 coarse = 15
rank 0 fine = 72
B:|    0    0    0    0    0    0    0    0    1    1    1    0    0    0    0    0
opt_dle value:9
DRAMC_R0DELDLY[018]=00001D1C
==================================================================
                RX      DQS perbit delay software calibration
==================================================================
1.0-15 bit dq delay value
==================================================================
bit|     0  1  2  3  4  5  6  7  8  9
--------------------------------------
0 |    6 5 5 6 5 5 5 3 3 5
10 |    7 7 6 8 6 7
--------------------------------------

==================================================================
2.dqs window
x=pass dqs delay value (min~max)center
y=0-7bit DQ of every group
input delay:DQS0 =28 DQS1 = 29
==================================================================
bit     DQS0     bit      DQS1
0  (1~51)26  8  (1~52)26
1  (1~53)27  9  (0~52)26
2  (0~52)26  10  (3~56)29
3  (1~55)28  11  (1~54)27
4  (1~51)26  12  (1~56)28
5  (1~52)26  13  (1~52)26
6  (1~51)26  14  (1~57)29
7  (1~52)26  15  (1~56)28
==================================================================
3.dq delay value last
==================================================================
bit|    0  1  2  3  4  5  6  7  8   9
--------------------------------------
0 |    8 6 7 6 7 7 7 5 6 8
10 |    7 9 7 11 6 8
==================================================================
==================================================================
     TX  perbyte calibration
==================================================================
DQS loop = 15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqsdly_pass[0]=15,  finish count=1
dqs_perbyte_dly.last_dqsdly_pass[1]=15,  finish count=2
DQ loop=15, cmp_err_1 = ffff0080
dqs_perbyte_dly.last_dqdly_pass[1]=15,  finish count=1
DQ loop=14, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqdly_pass[0]=14,  finish count=2
byte:0, (DQS,DQ)=(8,8)
byte:1, (DQS,DQ)=(8,8)
20,data:88
[EMI] DRAMC calibration passed

===================================================================
                MT7621   stage1 code done
                CPU=50000000 HZ BUS=16666666 HZ
===================================================================


U-Boot 1.1.3 (Jan 19 2017 - 17:14:12)

Board: Ralink APSoC DRAM:  256 MB
Power on memory test. Memory size= 256 MB...OK!
relocate_code Pointer at: 8ffac000

Config XHCI 40M PLL
******************************
Software System Reset Occurred
******************************
Allocate 16 byte aligned buffer: 8ffe0050
Enable NFI Clock
# MTK NAND # : Use HW ECC
NAND ID [C8 DA 90 95 44]
Device found in MTK table, ID: c8da, EXT_ID: 909544
Support this Device in MTK table! c8da
select_chip
[NAND]select ecc bit:4, sparesize :64 spare_per_sector=16
Signature matched and data read!
load_fact_bbt success 2047
load fact bbt success
[mtk_nand] probe successfully!
mtd->writesize=2048 mtd->oobsize=64,    mtd->erasesize=131072  devinfo.iowidth=8
..============================================
Ralink UBoot Version: 5.0.0.0
--------------------------------------------
ASIC MT7621A DualCore (MAC to MT7530 Mode)
DRAM_CONF_FROM: Auto-Detection
DRAM_TYPE: DDR3
DRAM bus: 16 bit
Xtal Mode=3 OCP Ratio=1/3
Flash component: NAND Flash
Date:Jan 19 2017  Time:17:14:12
============================================
icache: sets:256, ways:4, linesz:32 ,total:32768
dcache: sets:256, ways:4, linesz:32 ,total:32768

 ##### The CPU freq = 880 MHZ ####
 estimate memory size =256 Mbytes
#Reset_MT7530
set LAN/WAN LLLLW

Please choose the operation:
   1: Load system code to SDRAM via TFTP.
   2: Load system code then write to Flash via TFTP.
   3: Boot system code via Flash (default).
   4: Entr boot command line interface.
   7: Load Boot Loader code then write to Flash via Serial.
   9: Load Boot Loader code then write to Flash via TFTP.                     0
Boot failure detected on both systems
Verifying kernel1 uImage CRC, addr: 0xbc200000
   Image Name:   MIPS OpenWrt Linux-4.14.104
   Image Type:   MIPS Linux Kernel Image (lzma compressed)
   Data Size:    6302233 Bytes =  6 MB
   Load Address: 80001000
   Entry Point:  80001000
.................................................................................................   Verifying Checksum ... Bad Data CRC
Verifying kernel2 uImage CRC, addr: 0xbc600000
   Image Name:   MIPS OpenWrt Linux-4.14.104
   Image Type:   MIPS Linux Kernel Image (lzma compressed)
   Data Size:    1915975 Bytes =  1.8 MB
   Load Address: 80001000
   Entry Point:  80001000
..............................   Verifying Checksum ... OK
Booting System 2
..Erasing NAND Flash...
ranand_erase: start:40000, len:20000
.Writing to NAND Flash...
done

3: System Boot system code via Flash.
## Booting image at bc600000 ...
   Image Name:   MIPS OpenWrt Linux-4.14.104
   Image Type:   MIPS Linux Kernel Image (lzma compressed)
   Data Size:    1915975 Bytes =  1.8 MB
   Load Address: 80001000
   Entry Point:  80001000
..............................   Verifying Checksum ... OK
   Uncompressing Kernel Image ... OK
commandline uart_en=1 factory_mode=0 usb_u3=1
No initrd
## Transferring control to Linux (at address 80001000) ...
## Giving linux memsize in MB, 256

Starting kernel ...

[    0.000000] Linux version 4.14.104 (ilyas@fish) (gcc version 7.4.0 (OpenWrt GCC 7.4.0 r9514+3-302f7d57a9)) #0 SMP Wed Mar 6 14:49:28 2019


#189

@tekaeren yeah that mtk luci interface is broken (as you've noticed).... the /sbin/mtkwifi script is also broken (actually iwconfig and a bunch of other stuff is also broken...) but... as you may have noticed... wifi works... and imho it works well :wink:


#190

ilyas, no, last time I never managed to install the vpn server, kernel not support it said. today put your new release. all packages were set except the server. but the xl2tpd.ipk not installed.

root@OpenWrt:/tmp# opkg install xl2tpd.ipk
Installing xl2tpd (1.3.13-1) to root...
Collected errors:
 * satisfy_dependencies_for: Cannot satisfy the following dependencies for xl2tpd:
 *      kernel (= 4.14.105-1-eb8ed4b9bf234e78fd5debca12157d30)
 * opkg_install_cmd: Cannot install package xl2tpd.
root@OpenWrt:/tmp# opkg install vpn1.ipk
Installing ppp-mod-pppol2tp (2.4.7-12) to root...
Collected errors:
 * satisfy_dependencies_for: Cannot satisfy the following dependencies for ppp-mod-pppol2tp:
 *      kernel (= 4.14.105-1-eb8ed4b9bf234e78fd5debca12157d30)
 * opkg_install_cmd: Cannot install package ppp-mod-pppol2tp.

I need this (ppp-mod-pppol2tp, xl2tpd) packages. Can you give me the right versions of these packages?

And Wi-Fi speed in new release is not stable. some times it stop at all...:thinking:


#191

Restart your router and try without opkg update. If you tested wifi by using internet, it can be unreliable. Test using LAN


#192

WiFi only in lan. copy tested file by 100 Mb. at the RC1 version it was very fast, somthing like 32Mb/s,
at the last version is max 18Mb/s, and when file is copied at 70% speed goes down to zero...:fearful:


#193

As far as my reading of this thread goes, i have a botched up kernel0 and i require kernel0.bin(mtd8) to use uboot recovery method.

Checkout the tftp/serial method mentioned here :
https://openwrt.org/toh/xiaomi/mir3g
https://openwrt.org/toh/xiaomi/mir3

They flash kernel0 (mtd8.bin) before doing usb recovery method.
http://4pda.ru/forum/index.php?showtopic=810698&st=1940#entry71638926


#194

@pjgowtham looks like you wrote openwrt into both kernel partitions :wink: also you didn't back up the partitions i'm assuming :wink:

i'll figure out the offsets and let you know how to mtd write the xiaomi stock firmware...

or.... maybe this is easier... i'm posting my kernel0 file on my "release" page. download that. you're going to need to do something like

mtd write kernel0 kernel_stock
fw_setenv flag_try_sys1_failed 0
fw_setenv flag_try_sys2_failed 1
reboot

EDIT: apcli0/apclii0 are still there. they actually are meant to serve a purpose. but i compiled mt7615e without "STA mode" support so i have no idea what will happen if you enable them (possibly panic)... and since the configuration is loaded directly by the driver and the driver loads at boot.... you might end up in a panic loop. not a huge deal if you have an UART i guess..


#195

@splash ... that sucks. sorry i didn't upload xl2tpd.ipk .. i didn't realize it had a kernel dependency. also sucks that openwrt has already moved on to 4.14.105 (my latest was 4.14.104)...

i just uploaded the last xl2tpd.ipk i built... probably the commit version isn't going to match (although the kernel version will...) don't worry about that. i just committed some package files, didn't touch anything likely to conflict.

download install with opkg install --force-depends


#196

@splash that's strange.... when you say 18Mb do you mean megabit or megabyte? because i get (easily) 115mbit on 2.4ghz and ~290mbit on 5ghz...

what kind of speeds is everyone seeing?

btw, i'm not married to 5.0.2.0 ... it just happens to be the first one i've managed to compile... and i guess i'm a little proud of it (and it's been working well for me... i had an uptime of ~3 days without any issues and about >30 devices connected.... but parts of the code are obviously seriously broken (as in... i don't believe cfg80211 support ever compiled...) so maybe it's a good idea to move back to 4.4.2.1 or whatever the previous release was (and all the fun of getting that to compile)...


#197

Thanks for the kernel0 file. It worked like a charm. I was able rollback to stock and install openwrt again by the method in the wiki through ssh. I was able to use the same miwifi_ssh.bin and password that i used before. You might want to consider adding this step in the wiki for souls like me. UART comes handy everywhere. Good thing i bricked my router before.

About samba : I can't get it working. Seems too complicated for my head. I was trying to mount a 4TB NTFS HDD. I installed block mount and all your packages. I just didnt know how to proceed further. opkg install luci-app-samba gives me unknown package error.

Backup and restore function doesnt honor wifi settings. I am guessing that's intentional for now.

root@OpenWrt:~# lsusb -t
/:  Bus 02.Port 1: Dev 1, Class=root_hub, Driver=xhci-mtk/1p, 5000M
    |__ Port 1: Dev 2, If 0, Class=Mass Storage, Driver=usb-storage, 5000M
/:  Bus 01.Port 1: Dev 1, Class=root_hub, Driver=xhci-mtk/2p, 480M
root@OpenWrt:~# ls -l /dev/sd*
brw-------    1 root     root        8,   0 Jan  1  1970 /dev/sda
brw-------    1 root     root        8,   1 Jan  1  1970 /dev/sda1
root@OpenWrt:~# opkg install block-mount
Installing block-mount (2018-12-28-af93f4b8-4) to root...
Downloading http://downloads.openwrt.org/snapshots/targets/ramips/mt7621/packages/block-mount_2018-12-28-af93f4b8-4_mipsel_24kc.ipk
Configuring block-mount.
this file has been obsoleted. please call "/sbin/block mount" directly
root@OpenWrt:~# block info | grep "/dev/sd"
/dev/sda1: UUID="0000001800000048" TYPE="ntfs"
root@OpenWrt:~# uci show fstab
fstab.@global[0]=global
fstab.@global[0].anon_swap='0'
fstab.@global[0].anon_mount='0'
fstab.@global[0].auto_swap='1'
fstab.@global[0].auto_mount='1'
fstab.@global[0].delay_root='5'
fstab.@global[0].check_fs='0'
fstab.@mount[0]=mount
fstab.@mount[0].target='/mnt/sda1'
fstab.@mount[0].uuid='96D229E5D229C9F7'
fstab.@mount[0].enabled='0'
root@OpenWrt:~# ls -l /mnt/sda1
root@OpenWrt:~# service fstab boot
block: /dev/ubiblock0_0 is already mounted on /rom
block: /dev/ubi0_1 is already mounted on /overlay
block: No "mount.ntfs" utility available
block: mounting /dev/sda1 (ntfs) as /mnt/sda1 failed (2) - No such file or directory
root@OpenWrt:~# ls -l /mnt/sda1
root@OpenWrt:~# /sbin/block mount
block: /dev/ubiblock0_0 is already mounted on /rom
block: /dev/ubi0_1 is already mounted on /overlay
block: No "mount.ntfs" utility available
block: mounting /dev/sda1 (ntfs) as /mnt/sda1 failed (2) - No such file or directory
root@OpenWrt:~# opkg install kmod-fs-ntfs -force-depends
Installing kmod-fs-ntfs (4.14.105-1) to root...
Downloading http://downloads.openwrt.org/snapshots/targets/ramips/mt7621/packages/kmod-fs-ntfs_4.14.105-1_mipsel_24kc.ipk
Configuring kmod-fs-ntfs.
Collected errors:
 * satisfy_dependencies_for: Cannot satisfy the following dependencies for kmod-fs-ntfs:
 *      kernel (= 4.14.105-1-eb8ed4b9bf234e78fd5debca12157d30)

#198

Hi guys, I just followed the "Unlocking & Installing OpenWrt" step by step here:
https://openwrt.org/inbox/xiaomi/xiaomi_r3p_pro#info

Steps 1 through to 16 worked fine:
I copied and pasted each line of the commands individually as suggested and the device rebooted but all I'm getting now is a flashing amber light with the occasional flicker of blue then back to amber non-stop.

Im then getting connected / disconnected on loop via the NIC on my PC. Any ideas?

I literally followed the instructions to the letter. Hmm :face_with_monocle:


#199

You need to try uboot recovery and try to move back to stock and start over again.

Download stock firmware and rename it to miwifi.bin
Format your flash drive to fat32, copy your miwifi.bin to your flash drive and connect it to your router
Disconnect power from router
Now press and hold the reset button and power on the router ( hold it until the light starts flashing ) .Wait for 5 minutes. It will restore to stock.


#200

Tried that and it's not happening.
1, Downloaded stock firmware :ballot_box_with_check:
2, Formatted the USB FAT32 :ballot_box_with_check:
3, Renamed stock firmware to miwifi.bin :ballot_box_with_check:
4, Disconnected the power as usual :ballot_box_with_check:
5, Pressed and held the rest button :ballot_box_with_check:
6, Powered on the device with button held in :ballot_box_with_check:
7, waited for usual amber flashing light (Problem starts) *

  • At this point where you usually get amber flashing and then the USB drive starts functioning like when i've previously changed between stock chinese, taiwanese or developer firmwares, the device doesn't work as it usually would now.

Instead it kind of flashes amber and blinks blue for a split second and then amber again then blue. The NIC ports on the back flicker for a split second when it flashes blue on the front.

Do I need to pull this thing apart and use my USB to TTL device or do you reckon I can i get around this without doing that?


#201

UART/TTL is the only recovery option available in case boot fails and uboot recovery doesnt work. You need a uart ttl device and try the steps in the wiki.