https://www.gl-inet.com/products/gl-mt2500/ - I signed up for their marketing email months ago, their "Brume 2" is going up for pre-order tomorrow. Specs look pretty good - no idea what price will be. Thoughts?
Edit: Anyone know how good they've been on following GPL and supporting/contributing back to OpenWRT?
1 Gbps LAN and 2.5 Gbps WAN. I'd call that odd instead of "pretty good".
Considering how warm the Brume can get, I imagine that this one, as small as the Brume and with holes on only one side will be hotter.
Look at their forum. Their software is beta most of the time and never up to date to recent OpenWRT. And I mean beta with lots of bugs.
GL.iNet has just started taking pre-orders for the Brume 2 security gateway starting at $49 for the GL-MT2500 and $59 for the GL-MT2500A. Note those are quantity and time-limited offers, after which the prices will be $69 and $89 respectively.
Let’s see if there will be a Brume W 2 too
and its wireless counterpart https://www.cnx-software.com/2023/01/08/gl-inet-gl-mt3000-wifi-6-router-review-specs-unboxing-teardown/
Is there any sort of timeline on possible OpenWrt support for this device? Is the new SoC a hold-up?
Secondary question, once it is supported, is it likely that one could swap the LAN and WAN ports in OpenWrt (i.e. use the 2.5 Gbps port for LAN and 1 Gbps for WAN)? Or is there a hardware reason this won't work?
Someone who owns the device will need to do the port, if no one does that it won’t get supported.
There are no timelines for adding devices.
If I were willing to donate a device, how would I go about finding a developer that is willing and interested in doing this? I really have no idea how the community works here or who the major device-support contributors are.
So based on entries like this:
7 days ago Daniel Golle mediatek: backport pinctrl driver for MT7981 SoC
... work is in progress for this SoC, which is a precursor to any specific device support.
Thank you.
I see some more commits have been added in the meantime for this soc (filogic 820). Even something that looks like support for MT3000A. It seems similar to MT2500A in a lot of ways, though with WiFi and smaller NAND. So not similar enough yet.
I have some of these MT2500A devices and was planning to use them to set up some nice Wireguard tunnels - but I think I'll refrain from using them until some proper public OpenWRT version/support for it surfaces. I simply don't trust the stock firmware. 
Therefor, subscribing to this thread and giving it a bump to let you guys know there's still interest in this device.
Update: It seems MT3000 is really really close. Just the NAND size/partition sizes differ and there are some mini GPIO assignment differences. The latter I could probably manage to fix in the dts, but I have no idea how to go about figuring out the partition definitions inside the DTS versus the MT3000 one. If someone could point me to the right direction, I'm willing to test/figure it out.
root@GL-MT2500:~# cat /proc/partitions
major minor #blocks name
179 0 7634944 mmcblk0
179 1 2048 mmcblk0p1
179 2 512 mmcblk0p2
179 3 2048 mmcblk0p3
179 4 2048 mmcblk0p4
179 5 32768 mmcblk0p5
179 6 7593472 mmcblk0p6
179 7 7538688 mmcblk0p7
31 0 2048 mtdblock0
root@GL-MT2500:~# cat /proc/mtd
dev: size erasesize name
mtd0: 00200000 00010000 "log"
root@GL-MT2500:~# dmesg |grep mmc
[ 0.000000] Kernel command line: console=ttyS0,115200n1 loglevel=8 earlycon=uart8250,mmio32,0x11002000 root=PARTLABEL=rootfs rootwait rootfstype=squashfs,f2fs block2mtd.block2mtd=/dev/mmcblk0p1,65536,log
[ 0.968741] mmc0: new high speed MMC card at address 0001
[ 0.975201] mmcblk0: mmc0:0001 8GTF4R 7.28 GiB
[ 0.980501] mmcblk0boot0: mmc0:0001 8GTF4R partition 1 4.00 MiB
[ 0.987141] mmcblk0boot1: mmc0:0001 8GTF4R partition 2 4.00 MiB
[ 0.993136] mmcblk0rpmb: mmc0:0001 8GTF4R partition 3 512 KiB, chardev (249:0)
[ 1.026175] mmcblk0: p1 p2 p3 p4 p5 p6
[ 7.561138] F2FS-fs (mmcblk0p7): Mounted with checkpoint version = 978f0f
root@GL-MT2500:~# fdisk -l
The backup GPT table is not on the end of the device.
Disk /dev/mmcblk0: 7.28 GiB, 7818182656 bytes, 15269888 sectors
Units: sectors of 1 * 512 = 512 bytes
Sector size (logical/physical): 512 bytes / 512 bytes
I/O size (minimum/optimal): 512 bytes / 512 bytes
Disklabel type: gpt
Disk identifier: 2BD17853-102B-4500-AA1A-8A21D4D7984D
Device Start End Sectors Size Type
/dev/mmcblk0p1 4096 8191 4096 2M Linux filesystem
/dev/mmcblk0p2 8192 9215 1024 512K Linux filesystem
/dev/mmcblk0p3 9216 13311 4096 2M Linux filesystem
/dev/mmcblk0p4 13312 17407 4096 2M Linux filesystem
/dev/mmcblk0p5 17408 82943 65536 32M Linux filesystem
/dev/mmcblk0p6 82944 15269887 15186944 7.2G Linux filesystem
Disk /dev/mtdblock0: 2 MiB, 2097152 bytes, 4096 sectors
Units: sectors of 1 * 512 = 512 bytes
Sector size (logical/physical): 512 bytes / 512 bytes
I/O size (minimum/optimal): 512 bytes / 512 bytes
NAME FSTYPE FSVER LABEL UUID FSAVAIL FSUSE% MOUNTPOINT
mtdblock0
mmcblk0
├─mmcblk0p1
├─mmcblk0p2
├─mmcblk0p3
├─mmcblk0p4
├─mmcblk0p5
├─mmcblk0p6 squashfs 0 100% /rom
└─mmcblk0p7 f2fs rootfs_data 9c858e2a-0ba1-4e7e-ac64-2132ad64e19e 6.8G 6% /overlay
mmcblk0boot0
mmcblk0boot1
dtb % cat mt2500-emmc.dts
/dts-v1/;
/ {
compatible = "glinet,mt2500-emmc\0mediatek,mt7981";
interrupt-parent = <0x01>;
#address-cells = <0x02>;
#size-cells = <0x02>;
model = "GL.iNet GL-MT2500";
cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x00>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x01>;
};
};
pwm@10048000 {
compatible = "mediatek,mt7981-pwm";
reg = <0x00 0x10048000 0x00 0x1000>;
#pwm-cells = <0x02>;
clocks = <0x02 0x0d 0x02 0x0c 0x02 0x0e 0x02 0x0f 0x02 0x10>;
clock-names = "top\0main\0pwm1\0pwm2\0pwm3";
};
thermal-zones {
cpu-thermal {
polling-delay-passive = <0x3e8>;
polling-delay = <0x3e8>;
thermal-sensors = <0x03 0x00>;
};
};
thermal@1100c800 {
#thermal-sensor-cells = <0x01>;
compatible = "mediatek,mt7981-thermal";
reg = <0x00 0x1100c800 0x00 0x800>;
interrupts = <0x00 0x8a 0x04>;
clocks = <0x02 0x1c 0x02 0x2f 0x02 0x30>;
clock-names = "therm\0auxadc\0adc_32k";
mediatek,auxadc = <0x04>;
mediatek,apmixedsys = <0x05>;
nvmem-cells = <0x06>;
nvmem-cell-names = "calibration-data";
phandle = <0x03>;
};
adc@1100d000 {
compatible = "mediatek,mt7981-auxadc\0mediatek,mt7622-auxadc";
reg = <0x00 0x1100d000 0x00 0x1000>;
clocks = <0x02 0x2f 0x02 0x30>;
clock-names = "main\032k";
#io-channel-cells = <0x01>;
phandle = <0x04>;
};
wed@15010000 {
compatible = "mediatek,wed";
wed_num = <0x02>;
pci_slot_map = <0x00 0x01>;
reg = <0x00 0x15010000 0x00 0x1000 0x00 0x15011000 0x00 0x1000>;
interrupt-parent = <0x01>;
interrupts = <0x00 0xcd 0x04 0x00 0xce 0x04>;
};
wdma@15104800 {
compatible = "mediatek,wed-wdma";
reg = <0x00 0x15104800 0x00 0x400 0x00 0x15104c00 0x00 0x400>;
};
ap2woccif@151A5000 {
compatible = "mediatek,ap2woccif";
reg = <0x00 0x151a5000 0x00 0x1000 0x00 0x151ad000 0x00 0x1000>;
interrupt-parent = <0x01>;
interrupts = <0x00 0xd3 0x04 0x00 0xd4 0x04>;
};
wocpu0_ilm@151E0000 {
compatible = "mediatek,wocpu0_ilm";
reg = <0x00 0x151e0000 0x00 0x8000>;
};
wocpu_dlm@151E8000 {
compatible = "mediatek,wocpu_dlm";
reg = <0x00 0x151e8000 0x00 0x2000 0x00 0x151f8000 0x00 0x2000>;
resets = <0x07 0x00>;
reset-names = "wocpu_rst";
};
wocpu_boot@15194000 {
compatible = "mediatek,wocpu_boot";
reg = <0x00 0x15194000 0x00 0x1000>;
};
reserved-memory {
#address-cells = <0x02>;
#size-cells = <0x02>;
ranges;
secmon@43000000 {
reg = <0x00 0x43000000 0x00 0x30000>;
no-map;
};
wmcpu-reserved@47C80000 {
compatible = "mediatek,wmcpu-reserved";
no-map;
reg = <0x00 0x47c80000 0x00 0x100000>;
phandle = <0x17>;
};
wocpu0_emi@47D80000 {
compatible = "mediatek,wocpu0_emi";
no-map;
reg = <0x00 0x47d80000 0x00 0x40000>;
shared = <0x00>;
};
wocpu_data@47DC0000 {
compatible = "mediatek,wocpu_data";
no-map;
reg = <0x00 0x47dc0000 0x00 0x240000>;
shared = <0x01>;
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
oscillator@0 {
compatible = "fixed-clock";
#clock-cells = <0x00>;
clock-frequency = <0x2625a00>;
clock-output-names = "clkxtal";
phandle = <0x1d>;
};
infracfg_ao@10001000 {
compatible = "mediatek,mt7981-infracfg_ao\0syscon";
reg = <0x00 0x10001000 0x00 0x68>;
#clock-cells = <0x01>;
phandle = <0x02>;
};
infracfg@10001040 {
compatible = "mediatek,mt7981-infracfg\0syscon";
reg = <0x00 0x10001068 0x00 0x1000>;
#clock-cells = <0x01>;
phandle = <0x09>;
};
topckgen@1001B000 {
compatible = "mediatek,mt7981-topckgen\0syscon";
reg = <0x00 0x1001b000 0x00 0x1000>;
#clock-cells = <0x01>;
phandle = <0x08>;
};
apmixedsys@1001E000 {
compatible = "mediatek,mt7981-apmixedsys\0syscon";
reg = <0x00 0x1001e000 0x00 0x1000>;
#clock-cells = <0x01>;
phandle = <0x05>;
};
dummy_system_clk {
compatible = "fixed-clock";
clock-frequency = <0x2625a00>;
#clock-cells = <0x00>;
phandle = <0x19>;
};
dummy_gpt_clk {
compatible = "fixed-clock";
clock-frequency = <0x1312d00>;
#clock-cells = <0x00>;
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <0x01>;
clock-frequency = <0xc65d40>;
interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>;
};
watchdog@1001c000 {
compatible = "mediatek,mt7622-wdt\0mediatek,mt6589-wdt";
reg = <0x00 0x1001c000 0x00 0x1000>;
interrupts = <0x00 0x6e 0x04>;
#reset-cells = <0x01>;
status = "okay";
};
interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <0x03>;
interrupt-parent = <0x01>;
interrupt-controller;
reg = <0x00 0xc000000 0x00 0x40000 0x00 0xc080000 0x00 0x200000>;
interrupts = <0x01 0x09 0x04>;
phandle = <0x01>;
};
trng@1020f000 {
compatible = "mediatek,mt7981-rng";
};
serial@11002000 {
compatible = "mediatek,mt6577-uart";
reg = <0x00 0x11002000 0x00 0x400>;
interrupts = <0x00 0x7b 0x04>;
clocks = <0x02 0x1e>;
assigned-clocks = <0x08 0x50 0x02 0x00>;
assigned-clock-parents = <0x08 0x00 0x09 0x01>;
status = "okay";
};
serial@11003000 {
compatible = "mediatek,mt6577-uart";
reg = <0x00 0x11003000 0x00 0x400>;
interrupts = <0x00 0x7c 0x04>;
clocks = <0x02 0x1f>;
assigned-clocks = <0x08 0x50 0x02 0x01>;
assigned-clock-parents = <0x08 0x00 0x09 0x01>;
status = "disabled";
};
serial@11004000 {
compatible = "mediatek,mt6577-uart";
reg = <0x00 0x11004000 0x00 0x400>;
interrupts = <0x00 0x7d 0x04>;
clocks = <0x02 0x20>;
assigned-clocks = <0x08 0x50 0x02 0x02>;
assigned-clock-parents = <0x08 0x00 0x09 0x01>;
status = "disabled";
};
i2c@11007000 {
compatible = "mediatek,mt7981-i2c";
reg = <0x00 0x11007000 0x00 0x1000 0x00 0x10217080 0x00 0x80>;
interrupts = <0x00 0x88 0x04>;
clock-div = <0x01>;
clocks = <0x02 0x1d 0x02 0x19>;
clock-names = "main\0dma";
#address-cells = <0x01>;
#size-cells = <0x00>;
status = "disabled";
};
pcie@11280000 {
compatible = "mediatek,mt7981-pcie\0mediatek,mt7986-pcie";
device_type = "pci";
reg = <0x00 0x11280000 0x00 0x4000>;
reg-names = "pcie-mac";
#address-cells = <0x03>;
#size-cells = <0x02>;
interrupts = <0x00 0xa8 0x04>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x10000000>;
status = "disabled";
clocks = <0x02 0x38 0x02 0x39 0x02 0x3a 0x02 0x3b>;
phys = <0x0a 0x02>;
phy-names = "pcie-phy";
#interrupt-cells = <0x01>;
interrupt-map-mask = <0x00 0x00 0x00 0x07>;
interrupt-map = <0x00 0x00 0x00 0x01 0x0b 0x00 0x00 0x00 0x00 0x02 0x0b 0x01 0x00 0x00 0x00 0x03 0x0b 0x02 0x00 0x00 0x00 0x04 0x0b 0x03>;
interrupt-controller {
interrupt-controller;
#address-cells = <0x00>;
#interrupt-cells = <0x01>;
phandle = <0x0b>;
};
};
crypto@10320000 {
compatible = "inside-secure,safexcel-eip97";
reg = <0x00 0x10320000 0x00 0x40000>;
interrupts = <0x00 0x74 0x04 0x00 0x75 0x04 0x00 0x76 0x04 0x00 0x77 0x04>;
interrupt-names = "ring0\0ring1\0ring2\0ring3";
clocks = <0x08 0x42>;
clock-names = "top_eip97_ck";
assigned-clocks = <0x08 0x63>;
assigned-clock-parents = <0x08 0x15>;
};
pinctrl@11d00000 {
compatible = "mediatek,mt7981-pinctrl";
reg = <0x00 0x11d00000 0x00 0x1000 0x00 0x11c00000 0x00 0x1000 0x00 0x11c10000 0x00 0x1000 0x00 0x11d20000 0x00 0x1000 0x00 0x11e00000 0x00 0x1000 0x00 0x11e20000 0x00 0x1000 0x00 0x11f00000 0x00 0x1000 0x00 0x11f10000 0x00 0x1000 0x00 0x1000b000 0x00 0x1000>;
reg-names = "gpio_base\0iocfg_rt_base\0iocfg_rm_base\0iocfg_rb_base\0iocfg_lb_base\0iocfg_bl_base\0iocfg_tm_base\0iocfg_tl_base\0eint";
gpio-controller;
#gpio-cells = <0x02>;
gpio-ranges = <0x0c 0x00 0x00 0x38>;
interrupt-controller;
interrupts = <0x00 0xe1 0x04>;
interrupt-parent = <0x01>;
#interrupt-cells = <0x02>;
phandle = <0x0c>;
spi1-pins {
phandle = <0x16>;
mux {
function = "spi";
groups = "spi1_1";
};
};
mmc0-pins-default {
phandle = <0x13>;
mux {
function = "flash";
groups = "emmc_45";
};
};
mmc0-pins-uhs {
phandle = <0x14>;
mux {
function = "flash";
groups = "emmc_45";
};
};
};
syscon@15000000 {
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "mediatek,mt7981-ethsys\0syscon";
reg = <0x00 0x15000000 0x00 0x1000>;
#clock-cells = <0x01>;
#reset-cells = <0x01>;
phandle = <0x0d>;
reset-controller {
compatible = "ti,syscon-reset";
#reset-cells = <0x01>;
ti,reset-bits = <0x34 0x04 0x34 0x04 0x34 0x04 0x28>;
phandle = <0x07>;
};
};
ethernet@15100000 {
compatible = "mediatek,mt7981-eth";
reg = <0x00 0x15100000 0x00 0x80000>;
interrupts = <0x00 0xc4 0x04 0x00 0xc5 0x04 0x00 0xc6 0x04 0x00 0xc7 0x04>;
clocks = <0x0d 0x00 0x0d 0x01 0x0d 0x02 0x0d 0x03 0x0e 0x00 0x0e 0x01 0x0e 0x02 0x0e 0x03 0x0f 0x00 0x0f 0x01 0x0f 0x02 0x0f 0x03>;
clock-names = "fe\0gp2\0gp1\0wocpu0\0sgmii_tx250m\0sgmii_rx250m\0sgmii_cdr_ref\0sgmii_cdr_fb\0sgmii2_tx250m\0sgmii2_rx250m\0sgmii2_cdr_ref\0sgmii2_cdr_fb";
assigned-clocks = <0x08 0x60 0x08 0x61>;
assigned-clock-parents = <0x08 0x1b 0x08 0x22>;
mediatek,ethsys = <0x0d>;
mediatek,sgmiisys = <0x0e 0x0f>;
mediatek,infracfg = <0x10>;
#reset-cells = <0x01>;
#address-cells = <0x01>;
#size-cells = <0x00>;
status = "okay";
mac@0 {
compatible = "mediatek,eth-mac";
reg = <0x00>;
phy-mode = "2500base-x";
fixed-link {
speed = <0x9c4>;
full-duplex;
pause;
};
};
mac@1 {
compatible = "mediatek,eth-mac";
reg = <0x01>;
phy-mode = "gmii";
phy-handle = <0x11>;
};
mdio-bus {
#address-cells = <0x01>;
#size-cells = <0x00>;
ethernet-phy@0 {
compatible = "ethernet-phy-id03a2.9461";
reg = <0x00>;
phy-mode = "gmii";
nvmem-cells = <0x12>;
nvmem-cell-names = "phy-cal-data";
phandle = <0x11>;
};
phy@5 {
compatible = "ethernet-phy-id67c9.de0a";
reg = <0x05>;
reset-gpios = <0x0c 0x0e 0x01>;
reset-assert-us = <0x258>;
reset-deassert-us = <0x4e20>;
};
};
};
hnat@15000000 {
compatible = "mediatek,mtk-hnat_v4";
reg = <0x00 0x15100000 0x00 0x80000>;
resets = <0x0d 0x00>;
reset-names = "mtketh";
status = "okay";
mtketh-wan = "eth0";
mtketh-lan = "eth1";
mtketh-ppd = "eth1";
mtketh-max-gmac = <0x02>;
};
syscon@10060000 {
compatible = "mediatek,mt7981-sgmiisys_0\0syscon";
reg = <0x00 0x10060000 0x00 0x1000>;
pn_swap;
#clock-cells = <0x01>;
phandle = <0x0e>;
};
syscon@10070000 {
compatible = "mediatek,mt7981-sgmiisys_1\0syscon";
reg = <0x00 0x10070000 0x00 0x1000>;
#clock-cells = <0x01>;
phandle = <0x0f>;
};
topmisc@11d10000 {
compatible = "mediatek,mt7981-topmisc\0syscon";
reg = <0x00 0x11d10000 0x00 0x10000>;
#clock-cells = <0x01>;
phandle = <0x10>;
};
snfi@11005000 {
compatible = "mediatek,mt7986-snand";
reg = <0x00 0x11005000 0x00 0x1000 0x00 0x11006000 0x00 0x1000>;
reg-names = "nfi\0ecc";
interrupts = <0x00 0x79 0x04>;
clocks = <0x02 0x24 0x02 0x23 0x02 0x25>;
clock-names = "pad_clk\0nfi_clk\0nfi_hclk";
assigned-clocks = <0x08 0x4d 0x08 0x4c>;
assigned-clock-parents = <0x08 0x06 0x08 0x06>;
#address-cells = <0x01>;
#size-cells = <0x00>;
status = "disabled";
};
mmc@11230000 {
compatible = "mediatek,mt7986-mmc\0mediatek,mt7981-mmc";
reg = <0x00 0x11230000 0x00 0x1000 0x00 0x11c20000 0x00 0x1000>;
interrupts = <0x00 0x8f 0x04>;
clocks = <0x08 0x33 0x08 0x34 0x02 0x2b>;
assigned-clocks = <0x08 0x54 0x08 0x55>;
assigned-clock-parents = <0x08 0x02 0x08 0x1c>;
clock-names = "source\0hclk\0source_cg";
status = "okay";
pinctrl-names = "default\0state_uhs";
pinctrl-0 = <0x13>;
pinctrl-1 = <0x14>;
bus-width = <0x08>;
max-frequency = <0x3197500>;
cap-mmc-highspeed;
vmmc-supply = <0x15>;
non-removable;
};
wbsys@18000000 {
compatible = "mediatek,wbsys";
reg = <0x00 0x18000000 0x00 0x1000000>;
interrupts = <0x00 0xd5 0x04 0x00 0xd6 0x04 0x00 0xd7 0x04 0x00 0xd8 0x04>;
chip_id = <0x7981>;
};
wed_pcie@10003000 {
compatible = "mediatek,wed_pcie";
reg = <0x00 0x10003000 0x00 0x10>;
};
spi@1100a000 {
compatible = "mediatek,ipm-spi-quad";
reg = <0x00 0x1100a000 0x00 0x100>;
interrupts = <0x00 0x8c 0x04>;
clocks = <0x08 0x02 0x08 0x4e 0x02 0x26 0x02 0x28>;
clock-names = "parent-clk\0sel-clk\0spi-clk\0spi-hclk";
status = "disabled";
};
spi@1100b000 {
compatible = "mediatek,ipm-spi-single";
reg = <0x00 0x1100b000 0x00 0x100>;
interrupts = <0x00 0x8d 0x04>;
clocks = <0x08 0x02 0x08 0x4f 0x02 0x27 0x02 0x29>;
clock-names = "parent-clk\0sel-clk\0spi-clk\0spi-hclk";
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <0x16>;
};
spi@11009000 {
compatible = "mediatek,ipm-spi-quad";
reg = <0x00 0x11009000 0x00 0x100>;
interrupts = <0x00 0x8e 0x04>;
clocks = <0x08 0x02 0x08 0x4e 0x02 0x21 0x02 0x22>;
clock-names = "parent-clk\0sel-clk\0spi-clk\0spi-hclk";
status = "disabled";
};
consys@10000000 {
compatible = "mediatek,mt7981-consys";
reg = <0x00 0x10000000 0x00 0x8600000>;
memory-region = <0x17>;
};
xhci@11200000 {
compatible = "mediatek,mt7986-xhci\0mediatek,mtk-xhci";
reg = <0x00 0x11200000 0x00 0x2e00 0x00 0x11203e00 0x00 0x100>;
reg-names = "mac\0ippc";
interrupts = <0x00 0xad 0x04>;
phys = <0x18 0x03 0x0a 0x04>;
clocks = <0x19 0x19 0x19 0x19 0x19>;
clock-names = "sys_ck\0xhci_ck\0ref_ck\0mcu_ck\0dma_ck";
#address-cells = <0x02>;
#size-cells = <0x02>;
mediatek,u3p-dis-msk = <0x00>;
status = "okay";
};
usb-phy@11e10000 {
compatible = "mediatek,mt7986\0mediatek,generic-tphy-v2";
#address-cells = <0x02>;
#size-cells = <0x02>;
ranges;
status = "okay";
usb-phy@11e10000 {
reg = <0x00 0x11e10000 0x00 0x700>;
clocks = <0x19>;
clock-names = "ref";
#phy-cells = <0x01>;
status = "okay";
phandle = <0x18>;
};
usb-phy@11e10700 {
reg = <0x00 0x11e10700 0x00 0x900>;
clocks = <0x19>;
clock-names = "ref";
#phy-cells = <0x01>;
mediatek,syscon-type = <0x10 0x218 0x00>;
nvmem-cells = <0x1a 0x1b 0x1c>;
nvmem-cell-names = "intr\0rx_imp\0tx_imp";
status = "okay";
phandle = <0x0a>;
};
};
regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <0x325aa0>;
regulator-max-microvolt = <0x325aa0>;
regulator-boot-on;
regulator-always-on;
phandle = <0x15>;
};
clkitg {
compatible = "simple-bus";
bring-up {
compatible = "mediatek,clk-bring-up";
clocks = <0x05 0x00 0x05 0x01 0x05 0x02 0x05 0x03 0x05 0x04 0x05 0x05 0x05 0x06 0x05 0x07 0x09 0x00 0x1d 0x09 0x02 0x09 0x03 0x09 0x04 0x1d 0x09 0x06 0x09 0x07 0x1d 0x1d 0x1d 0x1d 0x09 0x0c 0x09 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x09 0x11 0x1d 0x1d 0x1d 0x1d 0x1d 0x09 0x17 0x09 0x18 0x09 0x1a 0x09 0x1b 0x09 0x1c 0x09 0x1d 0x09 0x1e 0x09 0x1f 0x09 0x20 0x09 0x21 0x1d 0x09 0x23 0x1d 0x1d 0x1d 0x1d 0x1d 0x1d 0x1d 0x1d 0x1d 0x02 0x0b 0x1d 0x1d 0x1d 0x1d 0x02 0x11 0x1d 0x1d 0x1d 0x1d 0x1d 0x02 0x17 0x1d 0x02 0x19 0x02 0x1a 0x02 0x1b 0x1d 0x1d 0x1d 0x1d 0x1d 0x1d 0x1d 0x1d 0x1d 0x1d 0x1d 0x1d 0x1d 0x1d 0x02 0x2a 0x02 0x2b 0x02 0x2c 0x02 0x2d 0x02 0x2e 0x1d 0x1d 0x02 0x31 0x02 0x32 0x02 0x33 0x02 0x34 0x02 0x35 0x02 0x36 0x02 0x37 0x1d 0x1d 0x1d 0x08 0x01 0x1d 0x08 0x05 0x08 0x06 0x08 0x07 0x08 0x04 0x08 0x09 0x08 0x0c 0x08 0x0f 0x08 0x10 0x08 0x12 0x08 0x14 0x08 0x15 0x08 0x16 0x08 0x17 0x08 0x19 0x08 0x1a 0x1d 0x08 0x1d 0x08 0x1e 0x08 0x21 0x1d 0x08 0x24 0x08 0x25 0x1d 0x08 0x29 0x08 0x26 0x08 0x2b 0x08 0x2a 0x1d 0x08 0x31 0x1d 0x1d 0x1d 0x08 0x56 0x08 0x37 0x08 0x3d 0x08 0x3e 0x08 0x3f 0x08 0x45 0x08 0x41 0x08 0x46 0x08 0x47 0x08 0x48 0x08 0x49 0x08 0x4a 0x08 0x3a 0x1d 0x1d 0x1d 0x1d 0x08 0x52 0x1d 0x1d 0x1d 0x08 0x56 0x08 0x57 0x08 0x58 0x08 0x59 0x08 0x5a 0x08 0x5b 0x08 0x5c 0x08 0x5d 0x08 0x5e 0x08 0x5f 0x1d 0x1d 0x08 0x62 0x08 0x5e 0x1d 0x08 0x64 0x08 0x56 0x08 0x69 0x08 0x6a 0x08 0x6b 0x08 0x6c>;
clock-names = "0\01\02\03\04\05\06\07\08\09\010\011\012\013\014\015\016\017\018\019\020\021\022\023\024\025\026\027\028\029\030\031\032\033\034\035\036\037\038\039\040\041\042\043\044\045\046\047\048\049\050\051\052\053\054\055\056\057\058\059\060\061\062\063\064\065\066\067\068\069\070\071\072\073\074\075\076\077\078\079\080\081\082\083\084\085\086\087\088\089\090\091\092\093\094\095\096\097\098\099\0100\0101\0102\0103\0104\0105\0106\0107\0108\0109\0110\0111\0112\0113\0114\0115\0116\0117\0118\0119\0120\0121\0122\0123\0124\0125\0126\0127\0128\0129\0130\0131\0132\0133\0134\0135\0136\0137\0138\0139\0140\0141\0142\0143\0144\0145\0146\0147\0148\0149\0150\0151\0152\0153\0154\0155\0156\0157\0158\0159\0160\0161\0162\0163\0164\0165\0166\0167\0168\0169\0170\0171\0172\0173\0174\0175\0176\0177\0178\0179\0180\0181\0182\0183";
};
};
efuse@11f20000 {
compatible = "mediatek,efuse";
reg = <0x00 0x11f20000 0x00 0x1000>;
#address-cells = <0x01>;
#size-cells = <0x01>;
calib@274 {
reg = <0x274 0x0c>;
phandle = <0x06>;
};
calib@8dc {
reg = <0x8dc 0x10>;
phandle = <0x12>;
};
usb3-rx-imp@8c8 {
reg = <0x8c8 0x01>;
bits = <0x00 0x05>;
phandle = <0x1b>;
};
usb3-tx-imp@8c8 {
reg = <0x8c8 0x02>;
bits = <0x05 0x05>;
phandle = <0x1c>;
};
usb3-intr@8c9 {
reg = <0x8c9 0x01>;
bits = <0x02 0x06>;
phandle = <0x1a>;
};
};
audio-controller@11210000 {
compatible = "mediatek,mt79xx-audio";
reg = <0x00 0x11210000 0x00 0x9000>;
interrupts = <0x00 0x6a 0x04>;
clocks = <0x02 0x12 0x02 0x13 0x02 0x14 0x02 0x15 0x02 0x16 0x08 0x65>;
clock-names = "aud_bus_ck\0aud_26m_ck\0aud_l_ck\0aud_aud_ck\0aud_eg2_ck\0aud_sel";
assigned-clocks = <0x08 0x65 0x08 0x66 0x08 0x67 0x08 0x68>;
assigned-clock-parents = <0x08 0x10 0x08 0x12 0x08 0x10 0x08 0x12>;
status = "disabled";
};
ice_debug {
compatible = "mediatek,mt7981-ice_debug\0mediatek,mt2701-ice_debug";
clocks = <0x02 0x18>;
clock-names = "ice_dbg";
};
chosen {
bootargs = "console=ttyS0,115200n1 loglevel=8 \t\t\t\tearlycon=uart8250,mmio32,0x11002000 \t\t\t\troot=PARTLABEL=rootfs rootwait rootfstype=squashfs,f2fs \t\t\t\tblock2mtd.block2mtd=/dev/mmcblk0p1,65536,log";
};
gl-hw {
compatible = "gl-hw-info";
model = "mt2500";
wan = "eth0";
lan = "eth1";
usb-port = "1-1";
flash_size = <0x2000>;
temperature = "/sys/devices/virtual/thermal/thermal_zone0/temp";
factory_data {
device_mac = "/dev/mmcblk0boot1\00x0a";
device_ddns = "/dev/mmcblk0boot1\00x10";
device_sn_bak = "/dev/mmcblk0boot1\00x20";
device_sn = "/dev/mmcblk0boot1\00x30";
country_code = "/dev/mmcblk0boot1\00x88";
};
};
gpio-keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <0x198>;
gpios = <0x0c 0x01 0x01>;
};
};
gpio-export {
compatible = "gpio-export";
usb_power {
gpio-export,name = "usb_power";
gpio-export,output = <0x01>;
gpios = <0x0c 0x0c 0x00>;
};
};
leds {
compatible = "gpio-leds";
led@0 {
label = "vpn";
gpios = <0x0c 0x1f 0x01>;
};
led@1 {
label = "white:system";
gpios = <0x0c 0x1e 0x01>;
};
led@2 {
label = "blue:system";
gpios = <0x0c 0x1d 0x01>;
default-state = "on";
};
};
};
is the Brume 2 (gl-mt2500) already working?? I would love to install openwrt23.05 on it.
You already have it or not?
If not then I recommend you go for NanoPi R4S rather than this one.
I already have his one.
The Brume 2 has no Openwrt support
I sold my gl-mt2500a and bought a NanoPi R4S instead.
Is there a specific reason why this device doesn't appear to be getting support any time soon (if ever)? The SoC itself is being supported, so I'm curious what's holding the Brume 2 back...
Master Snapshot available
That's a good news, however looking at price and hardware config, NanoPi R4S simply beats it.