@hecatae Any update on the build? 
Also if there's documentation somewhere on how to go about making the build to accommodate the hardware changes I would be happy to take a stab myself.
If you look at:
https://git.openwrt.org/?p=openwrt/openwrt.git;a=commit;h=2cb24b3f3cd89692f3c0bd137f3f560ada359bfa
A rbr50v2 dts is required, plus the other files need adapting.
rbx50 covers the rbr50 and rbs50, so rbx50v2 needs creating.
Adding myself to available testers for the v2. What can we do to help this along?
Would it be possible to create the RBS50 build exactly as it is configured but with one change, and that is to include the nand_macronix driver in the kernel?
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Pretty sure it's a device tree change that is required to get the correct driver etc. As long as there is a driver for that flash device? From what I understand it's not like autodetect storage like you're probably expecting from a desktop.
If someone is willing to learn how to make their own patch out of the willing testers. I'm happy to start to assist someone else making their own patch. I believe that would be much better in the long term as iterating the patch doesn't come down to me or another volunteer. If I happen to be in the build system Maybe I'll do something now that I may not have much work to do for the xdr3230 haha.
Anyway to start one should learn how to build and then start having fun modifying the source code?
It looks like we can probably already do a bulid test iterate. i.e. most of the steps can be skipped. But main thing is define the new firmware partitions? You look above with the factory bootlog? Perhaps obtain serial access for better testing?
One of these links below has already been posted but here you go for link dump.
Adding Device Link Dump
https://openwrt.org/docs/guide-developer/hw.hacking.first.steps
https://openwrt.org/docs/guide-developer/adding_new_device
https://openwrt.org/docs/guide-developer/add.new.device
https://openwrt.org/docs/guide-developer/defining-firmware-partitions
https://openwrt.org/docs/guide-developer/device-support-policies
Maybe this also has the code for v2? I haven't reviewed it.
The important one to start is get a build for the currently supported device. Then as per the above patch for the rbr50/rbs50v1 you can learn by example and start iterating.
build system link:
https://openwrt.org/docs/guide-developer/toolchain/use-buildsystem
1 Like
Thanks evs, I'll try to get this going
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Id recommend building 24.10-SNAPSHOT for the rbr50 or srr60, that would have the majority of what you need.
And then tweak from there
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@evs Thanks for the info dump. I'd love to get this working as I have a set of these (RBR50 and RBS50) that are no longer my primary network and I'd love to add them to my OpenWRT mesh system. These would be great for testing and I already have ssh access going so I can get the requisite information. Unfortunately I can't make heads or tails of the documentation on how to create/test a patch.
If you're willing to help walk me through it that would be super helpful. I'm happy to do the testing/iterating but don't really know where to start. Ideally if we could chat over something a bit more synchronous (e.g. Discord or Slack) that would be incredibly helpful.
I think I have a v2 on a shelf somewhere. I don't need it, as I picked up a few of the linksys mx4300's when they were 15 bucks on woot (and i'm also not maintaining the wifi at my ex's house anymore).
If you or someone else wants to spend the time to build this, I could mail/donate this device somewhere.
1 Like
Same. Are there developers that want one? Or updates on support for it?
Use the OFTC.net irc #openwrt channel.
I've now officially spent a whole day on this from scratch before i found this thread and I'm just going to post here on things I've found (maybe a slight repeat of some previous content) now here are the changes between RBR50 v1 (has OpenWRT DSA support) and v2(currently unsupported)
- No USB the board has depopulated everything related to USB port
- No BT radio (depop)
- Switch from Flash to NAND chip (MX30LF4G18AC-TI) for memory I believe from 4GB to 4Gb
- Some jumpers were removed
- the WiFi Power Amps are different chips seem to lower BOM count FEMs from Qorvo most likely GPIO controlled via the WiFi radio
Everything else appears to be the same,
Here's the chips that make up the most of it:
SoC IPQ4019
Ethernet QCA8075
WiFi QCA9984
NAND MX30LF4G18AC
My router runs Voxel's firmware a chaos calmer v15 openwrt variant based on qualcomm's SDK(?)
Where am I right now:
I've gotten ssh into the system and pulled files from the rom now I know which mtd parition the default mac addresses, WiFi calibration Etc are located thanks to ChatGPT for helping me down this rabbit hole thru it's hallucinations there was enough reality to help me see light at the end of this tunnel (fingers cossed)
effectivly we need to rebuild the image with an accurate nand parition mapping (need help checking my dts and stuff) and having the IPQ4019 switch to it's NAND controller instead of the emmc controller it uses in v1 orbi
the unit is also a dual firmware unit so I need to keep that in mind as i go about with this will keep this place posted with updates, also any pros out there who see this cry for help I appreciate any input
I am attempting to create a NAND node for the DTS from the MTD data i found putting them here
cat /proc/mtd
dev: size erasesize name
mtd0: 00100000 00020000 "0:SBL1"
mtd1: 00100000 00020000 "0:MIBIB"
mtd2: 00100000 00020000 "0:BOOTCONFIG"
mtd3: 00100000 00020000 "0:QSEE"
mtd4: 00100000 00020000 "0:QSEE_1"
mtd5: 00080000 00020000 "0:CDT"
mtd6: 00080000 00020000 "0:CDT_1"
mtd7: 00080000 00020000 "0:BOOTCONFIG1"
mtd8: 00080000 00020000 "0:APPSBLENV"
mtd9: 00200000 00020000 "0:APPSBL"
mtd10: 00200000 00020000 "0:APPSBL_1"
mtd11: 00080000 00020000 "0:ART"
mtd12: 00080000 00020000 "0:ART.bak"
mtd13: 00100000 00020000 "config"
mtd14: 00080000 00020000 "boarddata1"
mtd15: 00040000 00020000 "boarddata2"
mtd16: 00100000 00020000 "pot"
mtd17: 00080000 00020000 "boarddata1.bak"
mtd18: 00040000 00020000 "boarddata2.bak"
mtd19: 00500000 00020000 "language"
mtd20: 00080000 00020000 "cert"
mtd21: 09300000 00020000 "ntgrdata"
mtd22: 03200000 00020000 "firmware"
mtd23: 003c0000 00020000 "kernel"
mtd24: 02e40000 00020000 "rootfs"
mtd25: 00800000 00020000 "rootfs_data"
mtd26: 03200000 00020000 "firmware2"
mtd27: 003c0000 00020000 "kernel2"
mtd28: 02e40000 00020000 "rootfs2"
mtd29: 0f400000 00020000 "reserved"
mtd30: 0020f000 0001f000 "vol_traffic"
mtd31: 0020f000 0001f000 "vol_traffic.bak"
mtd32: 00516000 0001f000 "vol_devtable"
mtd33: 0009b000 0001f000 "vol_oopsdump"
mtd34: 01e08000 0001f000 "vol_circle"
mtd35: 02606000 0001f000 "vol_ntgr"
mtd36: 00516000 0001f000 "vol_ntgrcrydata"
mtd37: 0020f000 0001f000 "vol_rae"
mtd38: 00516000 0001f000 "vol_arlo"
mtd39: 02815000 0001f000 "vol_armor"
mtd40: 00117000 0001f000 "vol_jdx"
There's a bunch of stuff there about circle and armor I don't want to keep them around for now leaving them aside is fine I'm not sure if and how they would be included or ommited in the final DTS that I need to build it successfully at least for a initram image to get up
also throwing in the GPIO config as well incase
cat /sys/kernel/debug/gpio
GPIOs 0-69, platform/1000000.pinctrl, 1000000.pinctrl:
gpio0 : in 0 2mA keeper
gpio1 : in 0 2mA keeper
gpio2 : in 0 2mA keeper
gpio3 : in 0 2mA no pull
gpio4 : in 0 2mA keeper
gpio5 : in 0 2mA pull down
gpio6 : in 1 2mA keeper
gpio7 : in 1 2mA keeper
gpio8 : out 1 2mA no pull
gpio9 : out 1 2mA no pull
gpio10 : in 0 2mA keeper
gpio11 : in 0 2mA keeper
gpio12 : in 1 2mA no pull
gpio13 : in 1 2mA no pull
gpio14 : in 1 2mA no pull
gpio15 : in 1 2mA no pull
gpio16 : out 1 2mA pull down
gpio17 : out 1 2mA no pull
gpio18 : in 0 4mA keeper
gpio19 : in 1 2mA pull down
gpio20 : out 1 10mA no pull
gpio21 : out 1 10mA no pull
gpio22 : out 0 4mA keeper
gpio23 : out 0 4mA keeper
gpio24 : out 0 10mA keeper
gpio25 : out 0 10mA keeper
gpio26 : out 0 10mA keeper
gpio27 : out 0 10mA keeper
gpio28 : in 1 10mA keeper
gpio29 : in 1 10mA keeper
gpio30 : in 1 10mA keeper
gpio31 : in 1 10mA keeper
gpio32 : in 0 2mA keeper
gpio33 : in 0 2mA no pull
gpio34 : in 0 2mA keeper
gpio35 : in 0 2mA keeper
gpio36 : in 3 2mA pull down
gpio37 : in 0 2mA pull down
gpio38 : out 0 2mA pull down
gpio39 : in 0 2mA keeper
gpio40 : in 5 2mA pull down
gpio41 : out 0 2mA pull down
gpio42 : in 0 2mA pull down
gpio43 : in 0 2mA pull down
gpio44 : in 0 2mA pull down
gpio45 : in 0 10mA keeper
gpio46 : out 0 10mA keeper
gpio47 : out 0 2mA pull down
gpio48 : in 0 2mA pull down
gpio49 : in 0 4mA keeper
gpio50 : in 0 2mA keeper
gpio51 : in 0 2mA pull down
gpio52 : in 1 2mA keeper
gpio53 : in 1 2mA keeper
gpio54 : in 1 2mA pull down
gpio55 : in 1 2mA pull down
gpio56 : in 1 2mA pull down
gpio57 : in 1 2mA pull down
gpio58 : in 1 2mA keeper
gpio59 : in 1 2mA keeper
gpio60 : in 1 2mA pull down
gpio61 : in 1 2mA pull down
gpio62 : in 1 2mA pull down
gpio63 : in 1 2mA pull down
gpio64 : in 1 2mA pull down
gpio65 : in 1 2mA pull down
gpio66 : in 1 2mA pull down
gpio67 : in 1 2mA pull down
gpio68 : in 1 2mA pull down
gpio69 : in 1 2mA pull down
I think I have a DTS file that ChatGPT helped me put together that I need to verify once after I take a good nights sleep. I also Managed to take a look at the DTS from a stock version too pasting them in.
Any input from appreciated on the DTS file
My main questions:
Missing LED controller from TI that i saw on the board may be on i2c bus but not in stock DTS
Declaring NAND flash partitions if the NAND has a parition that describes it's paritions ?? I also want to leave out the bloat from from Netgear (armor, circle) i'd want OpenWRT to use that space instead. is there a tool that can help me with calculating the offsets for the new partitions (or do I need to wake up and do the math) ?
TIA
Stock DTS
/dts-v1/;
/ {
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "qcom,ipq40xx-apdk04.1\0qcom,ipq40xx";
flash_type = "NAND_FLASH";
interrupt-parent = <0x01>;
model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK04.1-C1";
qcom,board-id = <0x08 0x00>;
qcom,msm-id = <0x111 0x00>;
qcom,pmic-id = <0x00 0x00 0x00 0x00>;
aliases {
ethernet0 = "/soc/edma/gmac0";
ethernet1 = "/soc/edma/gmac1";
i2c0 = "/soc/i2c@78b7000";
i2c1 = "/soc/i2c@78b8000";
spi0 = "/soc/spi@78b5000";
spi1 = "/soc/spi@78b6000";
};
chosen {
bootargs-append = " clk_ignore_unused user_debug=0xff";
};
clocks {
gcc_sleep_clk_src {
#clock-cells = <0x00>;
clock-frequency = <0x7d00>;
compatible = "fixed-clock";
linux,phandle = <0x47>;
phandle = <0x47>;
};
xo {
#clock-cells = <0x00>;
clock-frequency = <0x2dc6c00>;
compatible = "fixed-clock";
};
};
cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
cpu@0 {
clock-frequency = <0x00>;
clocks = <0x02 0x09>;
compatible = "arm,cortex-a7";
device_type = "cpu";
enable-method = "qcom,arm-cortex-acc";
reg = <0x00>;
};
cpu@1 {
clock-frequency = <0x00>;
clocks = <0x02 0x09>;
compatible = "arm,cortex-a7";
device_type = "cpu";
enable-method = "qcom,arm-cortex-acc";
reg = <0x01>;
};
cpu@2 {
clock-frequency = <0x00>;
clocks = <0x02 0x09>;
compatible = "arm,cortex-a7";
device_type = "cpu";
enable-method = "qcom,arm-cortex-acc";
reg = <0x02>;
};
cpu@3 {
clock-frequency = <0x00>;
clocks = <0x02 0x09>;
compatible = "arm,cortex-a7";
device_type = "cpu";
enable-method = "qcom,arm-cortex-acc";
reg = <0x03>;
};
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
reserved-memory {
#address-cells = <0x01>;
#size-cells = <0x01>;
ranges;
rsvd1@87000000 {
no-map;
reg = <0x87000000 0x500000>;
};
rsvd2@87B00000 {
no-map;
reg = <0x87b00000 0x500000>;
};
wifi_dump@87500000 {
no-map;
reg = <0x87500000 0x600000>;
};
};
soc {
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "simple-bus";
ranges;
a7ss_base@b088000 {
compatible = "qcom,arm-cortex-acc";
reg = <0xb088000 0x1000>;
};
ad-hoc-bus {.... cut this out for now ...
};
clock-controller@1800000 {
#clock-cells = <0x01>;
#reset-cells = <0x01>;
compatible = "qcom,gcc-ipq40xx";
linux,phandle = <0x02>;
phandle = <0x02>;
reg = <0x1800000 0x60000>;
};
clock-controller@7700038 {
#clock-cells = <0x01>;
#reset-cells = <0x01>;
compatible = "qcom,adcc-ipq40xx";
reg = <0x7700038 0x1dc>;
status = "disabled";
};
counter {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x04>;
};
cpu_freq_ipq40xx {
clock-latency = <0x186a0>;
compatible = "qca,ipq40xx_freq";
qcom,cpufreq-table = <0xbb80 0x30d40 0x7a120 0xaece0>;
};
edma@c080000 {
compatible = "qcom,ess-edma";
interrupts = <0x00 0x41 0x01 0x00 0x42 0x01 0x00 0x43 0x01 0x00 0x44 0x01 0x00 0x45 0x01 0x00 0x46 0x01 0x00 0x47 0x01 0x00 0x48 0x01 0x00 0x49 0x01 0x00 0x4a 0x01 0x00 0x4b 0x01 0x00 0x4c 0x01 0x00 0x4d 0x01 0x00 0x4e 0x01 0x00 0x4f 0x01 0x00 0x50 0x01 0x00 0xf0 0x01 0x00 0xf1 0x01 0x00 0xf2 0x01 0x00 0xf3 0x01 0x00 0xf4 0x01 0x00 0xf5 0x01 0x00 0xf6 0x01 0x00 0xf7 0x01 0x00 0xf8 0x01 0x00 0xf9 0x01 0x00 0xfa 0x01 0x00 0xfb 0x01 0x00 0xfc 0x01 0x00 0xfd 0x01 0x00 0xfe 0x01 0x00 0xff 0x01>;
qcom,mdio_supported;
qcom,num_gmac = <0x02>;
qcom,page-mode = <0x00>;
qcom,rx_head_buf_size = <0x604>;
reg = <0xc080000 0x8000>;
gmac0 {
local-mac-address = [00 00 00 00 00 00];
qcom,forced_duplex = <0x01>;
qcom,forced_speed = <0x3e8>;
qcom,phy_mdio_addr = <0x00>;
qcom,poll_required = <0x01>;
vlan_tag = <0x02 0x02>;
};
gmac1 {
local-mac-address = [00 00 00 00 00 00];
vlan_tag = <0x01 0x3c>;
};
};
ess-psgmii@98000 {
compatible = "qcom,ess-psgmii";
psgmii_access_mode = "local bus";
reg = <0x98000 0x800>;
reset-names = "psgmii_rst";
resets = <0x02 0x4d>;
};
ess-switch@c000000 {
clock-names = "ess_clk";
clocks = <0x02 0x23>;
compatible = "qcom,ess-switch";
reg = <0xc000000 0x80000>;
reset-names = "ess_rst\0ess_mac1_clk_dis\0ess_mac2_clk_dis\0ess_mac3_clk_dis\0ess_mac4_clk_dis\0ess_mac5_clk_dis";
resets = <0x02 0x1d 0x02 0x4e 0x02 0x4f 0x02 0x50 0x02 0x51 0x02 0x52>;
switch_access_mode = "local bus";
switch_cpu_bmp = <0x01>;
switch_initvlas = <0x7c 0x54>;
switch_lan_bmp = <0x1e>;
switch_mac_mode = <0x00>;
switch_wan_bmp = <0x20>;
led_source@0 {
freq = "auto";
led = <0x03>;
mode = "normal";
source = <0x01>;
speed = "all";
};
led_source@1 {
freq = "auto";
led = <0x04>;
mode = "normal";
source = <0x04>;
speed = "all";
};
led_source@2 {
freq = "auto";
led = <0x05>;
mode = "normal";
source = <0x07>;
speed = "all";
};
led_source@3 {
freq = "auto";
led = <0x06>;
mode = "normal";
source = <0x0a>;
speed = "all";
};
led_source@4 {
freq = "auto";
led = <0x07>;
mode = "normal";
source = <0x0d>;
speed = "all";
};
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
qcom,ess-interface-select = <0x00>;
reg = <0x1953000 0x1000>;
};
gpio_keys {
compatible = "gpio-keys";
button@1 {
gpios = <0x51 0x12 0x01>;
label = "wps";
linux,code = <0x211>;
linux,input-type = <0x01>;
};
};
hsphy@a6000 {
compatible = "qca,baldur-usb3-hsphy";
linux,phandle = <0x4b>;
phandle = <0x4b>;
qca,emulation = <0x00>;
qca,host = <0x01>;
reg = <0xa6000 0x40>;
reg-names = "phy_base";
reset-names = "por_rst\0srif_rst";
resets = <0x02 0x0d 0x02 0x0e>;
status = "ok";
};
hsphy@a8000 {
compatible = "qca,baldur-usb2-hsphy";
linux,phandle = <0x4d>;
phandle = <0x4d>;
qca,emulation = <0x00>;
qca,host = <0x01>;
reg = <0xa8000 0x40>;
reg-names = "phy_base";
reset-names = "por_rst\0srif_rst";
resets = <0x02 0x0f 0x02 0x10>;
status = "ok";
};
i2c@78b7000 {
#address-cells = <0x01>;
#size-cells = <0x00>;
clock-names = "iface_clk\0core_clk";
clocks = <0x02 0x15 0x02 0x16>;
compatible = "qcom,i2c-msm-v2";
interrupt-names = "qup_irq\0bam_irq";
interrupts = <0x00 0x61 0x00 0x00 0xee 0x00>;
pinctrl-0 = <0x4f>;
pinctrl-1 = <0x4f>;
pinctrl-names = "i2c_active\0i2c_sleep";
qcom,bam-pipe-idx-cons = <0x08>;
qcom,bam-pipe-idx-prod = <0x09>;
qcom,clk-freq-in = <0x122ae10>;
qcom,clk-freq-out = <0x186a0>;
qcom,master-id = <0x00>;
qcom,noise-rjct-scl = <0x00>;
qcom,noise-rjct-sda = <0x00>;
reg = <0x78b7000 0x600 0x7884000 0x23000>;
reg-names = "qup_phys_addr\0bam_phys_addr";
status = "ok";
lcd_ts@40 {
compatible = "qca,gsl1680_ts";
reg = <0x40>;
status = "disabled";
};
qca_codec@12 {
compatible = "qca,ipq40xx-codec";
reg = <0x12>;
status = "disabled";
};
};
i2c@78b8000 {
#address-cells = <0x01>;
#size-cells = <0x00>;
clock-names = "iface_clk\0core_clk";
clocks = <0x02 0x15 0x02 0x18>;
compatible = "qcom,i2c-msm-v2";
interrupt-names = "qup_irq\0bam_irq";
interrupts = <0x00 0x62 0x00 0x00 0xee 0x00>;
qcom,bam-pipe-idx-cons = <0x0a>;
qcom,bam-pipe-idx-prod = <0x0b>;
qcom,clk-freq-in = <0x122ae10>;
qcom,clk-freq-out = <0x186a0>;
qcom,master-id = <0x00>;
qcom,noise-rjct-scl = <0x00>;
qcom,noise-rjct-sda = <0x00>;
reg = <0x78b8000 0x600 0x7884000 0x23000>;
reg-names = "qup_phys_addr\0bam_phys_addr";
status = "disabled";
};
interrupt-controller@b000000 {
#interrupt-cells = <0x03>;
compatible = "qcom,msm-qgic2";
interrupt-controller;
linux,phandle = <0x01>;
phandle = <0x01>;
reg = <0xb000000 0x1000 0xb002000 0x1000>;
};
ledc@1937000 {
compatible = "qca,ledc";
pinctrl-0 = <0x52>;
pinctrl-names = "default";
qcom,ledc_blink_indices = <0x00>;
qcom,ledc_blink_indices_cnt = <0x00>;
qcom,tcsr_ledc_values = <0x320193 0x14720800 0x20d 0x00 0x00 0xffffffff 0x00 0x07 0x7d0010 0x00 0x10482090 0x3fffdfc>;
reg = <0x1937000 0x20070>;
reg-names = "ledc_base_addr";
status = "ok";
};
mdio@90000 {
#address-cells = <0x01>;
#size-cells = <0x01>;
bias-disable;
compatible = "qcom,ipq40xx-mdio";
phy-reset-gpio = <0x51 0x2f 0x00>;
pinctrl-0 = <0x55>;
pinctrl-names = "default";
reg = <0x90000 0x64>;
status = "ok";
ethernet-phy@0 {
reg = <0x00>;
};
ethernet-phy@1 {
reg = <0x01>;
};
ethernet-phy@2 {
reg = <0x02>;
};
ethernet-phy@3 {
reg = <0x03>;
};
ethernet-phy@4 {
reg = <0x04>;
};
};
pinctrl@0x01000000 {
#gpio-cells = <0x02>;
#interrupt-cells = <0x02>;
compatible = "qcom,ipq40xx-pinctrl";
gpio-controller;
interrupt-controller;
interrupts = <0x00 0xd0 0x00>;
linux,phandle = <0x51>;
phandle = <0x51>;
reg = <0x1000000 0x300000>;
i2c_0_pinmux {
linux,phandle = <0x4f>;
phandle = <0x4f>;
mux {
bias-disable;
function = "blsp_i2c0";
pins = "gpio20\0gpio21";
};
};
led0_pinmux {
linux,phandle = <0x52>;
phandle = <0x52>;
mux_1 {
bias-pull-down;
function = "led0";
pins = "gpio36";
};
mux_2 {
bias-pull-down;
function = "led4";
pins = "gpio40";
};
};
mdio_pinmux {
linux,phandle = <0x55>;
phandle = <0x55>;
mux_1 {
bias-bus-hold;
function = "mdio0";
pins = "gpio6";
};
mux_2 {
bias-bus-hold;
function = "mdc";
pins = "gpio7";
};
};
sd_0_pinmux {
linux,phandle = <0x53>;
phandle = <0x53>;
sd0 {
drive-strength = <0x0a>;
function = "sdio0";
pins = "gpio23";
};
sd1 {
drive-strength = <0x0a>;
function = "sdio1";
pins = "gpio24";
};
sd2 {
drive-strength = <0x0a>;
function = "sdio2";
pins = "gpio25";
};
sd3 {
drive-strength = <0x0a>;
function = "sdio3";
pins = "gpio26";
};
sd4 {
drive-strength = <0x0a>;
function = "sdio4";
pins = "gpio29";
};
sd5 {
drive-strength = <0x0a>;
function = "sdio5";
pins = "gpio30";
};
sd6 {
drive-strength = <0x0a>;
function = "sdio6";
pins = "gpio31";
};
sd7 {
bias-disable;
drive-strength = <0x0a>;
function = "sdio7";
pins = "gpio32";
};
sdclk {
drive-strength = <0x10>;
function = "sdio_clk";
pins = "gpio27";
};
sdcmd {
drive-strength = <0x0a>;
function = "sdio_cmd";
pins = "gpio28";
};
};
serial0_pinmux {
linux,phandle = <0x48>;
phandle = <0x48>;
mux {
bias-disable;
function = "blsp_uart0";
pins = "gpio16\0gpio17";
};
pulldowns {
bias-pull-down;
pins = "gpio16";
};
};
serial1_pinmux {
linux,phandle = <0x49>;
phandle = <0x49>;
mux {
bias-disable;
function = "blsp_uart1";
pins = "gpio8\0gpio9";
};
};
spi_0_pinmux {
linux,phandle = <0x4a>;
phandle = <0x4a>;
mux {
bias-disable;
function = "blsp_spi0";
pins = "gpio12\0gpio13\0gpio14\0gpio15";
};
};
ts_0_pinmux {
mux_1 {
output-high;
pins = "gpio34";
};
mux_2 {
bias-pull-up;
input-enable;
pins = "gpio35";
};
};
uart1_pinmux {
linux,phandle = <0x57>;
phandle = <0x57>;
mux {
bias-disable;
function = "blsp_uart1";
pins = "gpio8\0gpio9\0gpio10\0gpio11";
};
};
};
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <0x01 0x07 0xf04>;
};
pwm {
clock-names = "core";
clocks = <0x02 0x14>;
compatible = "qca,ipq4019-pwm";
pwm-base-index = <0x00>;
status = "disabled";
used-pwm-indices = <0x01 0x01 0x01 0x01>;
};
qca,scm_restart_reason {
compatible = "qca,scm_restart_reason";
};
qcedev@8e20000 {
clock-names = "core_clk\0bus_clk\0iface_clk";
clocks = <0x02 0x22 0x02 0x21 0x02 0x20>;
compatible = "qcom,qcedev";
interrupts = <0x00 0xcf 0x00>;
qcom,bam-pipe-pair = <0x01>;
qcom,ce-device = <0x00>;
qcom,ce-hw-instance = <0x00>;
qcom,ce-hw-shared = <0x01>;
qcom,ce-opp-freq = <0x7735940>;
reg = <0x8e20000 0x20000 0x8e04000 0x20000>;
reg-names = "crypto-base\0crypto-bam-base";
status = "ok";
};
qcom,mdss_lcd_qpic_panel {
compatible = "qcom,mdss-qpic-panel";
label = "qpic lcd panel";
qcom,mdss-pan-bpp = <0x12>;
qcom,mdss-pan-res = <0x320 0x1e0>;
qcom,refresh_rate = <0x3c>;
status = "ok";
};
qcom,msm_qpic@7980000 {
compatible = "qcom,mdss_qpic";
interrupt-names = "lcdc_irq\0bam_irq";
interrupts = <0x00 0x6a 0x00 0x00 0x65 0x00>;
qcom,msm-bus,name = "mdss_qpic";
qcom,msm-bus,num-cases = <0x02>;
qcom,msm-bus,num-paths = <0x01>;
qcom,msm-bus,vectors-KBps = <0x5b 0x200 0x00 0x00 0x5b 0x200 0x61a80 0xc3500>;
reg = <0x7980000 0x24000>;
reg-names = "qpic_base";
status = "ok";
};
qcom,nand@7980000 {
clock-names = "iface_clk\0core_clk";
clocks = <0x02 0x2b 0x02 0x2c>;
compatible = "qcom,msm-nand";
interrupt-names = "bam_irq";
interrupts = <0x00 0x65 0x00>;
qcom,msm-bus,name = "qpic_nand";
qcom,msm-bus,num-cases = <0x02>;
qcom,msm-bus,num-paths = <0x01>;
qcom,msm-bus,vectors-KBps = <0x5b 0x200 0x00 0x00 0x5b 0x200 0x61a80 0xc3500>;
reg = <0x7980000 0x40000 0x7984000 0x1a000>;
reg-names = "nand_phys\0bam_phys";
status = "ok";
};
qcom,pcie@80000 {
#address-cells = <0x00>;
#interrupt-cells = <0x01>;
cell-index = <0x00>;
clkreq-gpio = <0x51 0x27 0x00>;
clock-names = "pcie_0_cfg_ahb_clk\0pcie_0_mstr_axi_clk\0pcie_0_slv_axi_clk";
clocks = <0x02 0x26 0x02 0x27 0x02 0x28>;
compatible = "qcom,msm_pcie";
interrupt-map = <0x00 0x01 0x00 0x8d 0x00 0x01 0x01 0x00 0x8e 0x00 0x02 0x01 0x00 0x8f 0x00 0x03 0x01 0x00 0x90 0x00 0x04 0x01 0x00 0x91 0x00 0x05 0x01 0x00 0x92 0x00 0x06 0x01 0x00 0x93 0x00 0x07 0x01 0x00 0x94 0x00 0x08 0x01 0x00 0x95 0x00 0x09 0x01 0x00 0x96 0x00 0x0a 0x01 0x00 0x97 0x00 0x0b 0x01 0x00 0x98 0x00>;
interrupt-map-mask = <0xffffffff>;
interrupt-names = "int_msi\0int_a\0int_b\0int_c\0int_d\0int_pls_pme\0int_pme_legacy\0int_pls_err\0int_aer_legacy\0int_pls_link_up\0int_pls_link_down\0int_bridge_flush_n\0int_wake";
interrupt-parent = <0x50>;
interrupts = <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c>;
linux,phandle = <0x50>;
max-clock-frequency-hz = <0x00 0x00 0x00>;
perst-gpio = <0x51 0x26 0x00>;
phandle = <0x50>;
qcom,ctrl-amt = <0x01>;
qcom,ep-latency = <0x0a>;
reg = <0x80000 0x2000 0x99000 0x800 0x40000000 0xf1d 0x40000f20 0xa8 0x40100000 0x1000 0x40200000 0x100000 0x40300000 0xd00000>;
reg-names = "parf\0phy\0dm_core\0elbi\0conf\0io\0bars";
reset-names = "pcie_rst_axi_m_ares\0pcie_rst_axi_s_ares\0pcie_rst_pipe_ares\0pcie_rst_axi_m_vmidmt_ares\0pcie_rst_axi_s_xpu_ares\0pcie_rst_parf_xpu_ares\0pcie_rst_phy_ares\0pcie_rst_axi_m_sticky_ares\0pcie_rst_pipe_sticky_ares\0pcie_rst_pwr_ares\0pcie_rst_ahb_res\0pcie_rst_phy_ahb_ares";
resets = <0x02 0x1c 0x02 0x1b 0x02 0x1a 0x02 0x19 0x02 0x18 0x02 0x17 0x02 0x16 0x02 0x15 0x02 0x14 0x02 0x13 0x02 0x12 0x02 0x11>;
status = "ok";
wake-gpio = <0x51 0x28 0x00>;
};
qcom,sps {
compatible = "qcom,msm_sps_4k";
qcom,device-type = <0x03>;
qcom,pipe-attr-ee;
};
qcrypto@8e20000 {
clock-names = "core_clk\0bus_clk\0iface_clk";
clocks = <0x02 0x22 0x02 0x21 0x02 0x20>;
compatible = "qcom,qcrypto";
interrupts = <0x00 0xcf 0x00>;
qcom,bam-pipe-pair = <0x01>;
qcom,ce-device = <0x00>;
qcom,ce-hw-instance = <0x00>;
qcom,ce-hw-shared = <0x01>;
qcom,ce-opp-freq = <0x7735940>;
reg = <0x8e20000 0x20000 0x8e04000 0x20000>;
reg-names = "crypto-base\0crypto-bam-base";
status = "ok";
};
regulator@0 {
compatible = "qcom,regulator-ipq40xx";
linux,phandle = <0x54>;
mask = <0x03>;
phandle = <0x54>;
reg = <0x1948000 0x04>;
regulator-max-microvolt = <0x2dc6c0>;
regulator-min-microvolt = <0x1b7740>;
regulator-name = "SD0 VccQ";
states = <0x2dc6c0 0x03 0x1b7740 0x01>;
};
restart@4ab000 {
compatible = "qcom,pshold";
reg = <0x4ab000 0x04>;
};
rng@0x00022000 {
clock-names = "core";
clocks = <0x02 0x2a>;
compatible = "qcom,prng";
reg = <0x22000 0x140>;
};
sdhci@7824000 {
bus-width = <0x08>;
cd-gpios = <0x51 0x16 0x01>;
clock-names = "core\0iface";
clocks = <0x02 0x2e 0x02 0x2d>;
compatible = "qcom,sdhci-msm-v4";
interrupts = <0x00 0x7b 0x00 0x00 0x8a 0x00>;
pinctrl-0 = <0x53>;
pinctrl-names = "default";
reg = <0x7824900 0x11c 0x7824000 0x800>;
sd-ldo-gpios = <0x51 0x21 0x01>;
status = "disabled";
vqmmc-supply = <0x54>;
};
serial@78af000 {
clock-names = "core\0iface";
clocks = <0x02 0x1a 0x02 0x15>;
compatible = "qcom,msm-uartdm-v1.4\0qcom,msm-uartdm";
interrupts = <0x00 0x6b 0x00>;
pinctrl-0 = <0x48>;
pinctrl-names = "default";
reg = <0x78af000 0x200>;
status = "ok";
};
serial@78b0000 {
clock-names = "core\0iface";
clocks = <0x02 0x1b 0x02 0x15>;
compatible = "qcom,msm-uartdm-v1.4\0qcom,msm-uartdm";
interrupts = <0x00 0x6c 0x00>;
pinctrl-0 = <0x49>;
pinctrl-names = "default";
reg = <0x78b0000 0x200>;
status = "ok";
};
spi@78b5000 {
#address-cells = <0x01>;
#size-cells = <0x00>;
clock-names = "core_clk\0iface_clk";
clocks = <0x02 0x17 0x02 0x15>;
compatible = "qcom,spi-qup-v2";
interrupt-names = "spi_irq\0spi_bam_irq";
interrupts = <0x00 0x5f 0x00 0x00 0xee 0x00>;
pinctrl-0 = <0x4a>;
pinctrl-names = "default";
qcom,bam-consumer-pipe-index = <0x04>;
qcom,bam-producer-pipe-index = <0x05>;
qcom,infinite-mode = <0x00>;
qcom,master-id = <0x00>;
qcom,use-bam;
reg = <0x78b5000 0x600 0x7884000 0x23000>;
reg-names = "spi_physical\0spi_bam_physical";
spi-max-frequency = <0x16e3600>;
status = "ok";
m25p80@0 {
#address-cells = <0x01>;
#size-cells = <0x01>;
compatible = "n25q128a11";
linux,modalias = "m25p80\0n25q128a11";
reg = <0x00>;
spi-max-frequency = <0x16e3600>;
use-default-sizes;
};
};
spi@78b6000 {
#address-cells = <0x01>;
#size-cells = <0x00>;
clock-names = "core_clk\0iface_clk";
clocks = <0x02 0x19 0x02 0x15>;
compatible = "qcom,spi-qup-v2";
interrupt-names = "spi_irq\0spi_bam_irq";
interrupts = <0x00 0x60 0x00 0x00 0xee 0x00>;
qcom,bam-consumer-pipe-index = <0x06>;
qcom,bam-producer-pipe-index = <0x07>;
qcom,infinite-mode = <0x00>;
qcom,master-id = <0x00>;
qcom,use-bam;
reg = <0x78b6000 0x600 0x7884000 0x23000>;
reg-names = "spi_physical\0spi_bam_physical";
spi-max-frequency = <0x16e3600>;
status = "disabled";
};
ssphy@0 {
compatible = "qca,uni-ssphy";
linux,phandle = <0x4c>;
phandle = <0x4c>;
qca,emulation = <0x00>;
qca,host = <0x01>;
reg = <0x9a000 0x800>;
reg-names = "phy_base";
reset-names = "por_rst";
resets = <0x02 0x0c>;
status = "ok";
};
ssphy@1 {
compatible = "qca,dummy-ssphy";
linux,phandle = <0x4e>;
phandle = <0x4e>;
status = "ok";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
qcom,wifi_glb_cfg = <0x41000000>;
reg = <0x1949000 0x100>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
qcom,usb-hsphy-mode-select = <0xe700e7>;
reg = <0x194b000 0x100>;
status = "ok";
};
tcsr@1957000 {
compatible = "qcom,tcsr";
qcom,wifi_noc_memtype_m0_m2 = <0x2222222>;
reg = <0x1957000 0x100>;
};
timer {
clock-frequency = <0x2dc6c00>;
compatible = "arm,armv7-timer";
interrupts = <0x01 0x02 0xf08 0x01 0x03 0xf08 0x01 0x04 0xf08 0x01 0x01 0xf08>;
};
uart@78b0000 {
#address-cells = <0x00>;
#interrupt-cells = <0x01>;
clock-names = "iface_clk\0core_clk";
clocks = <0x02 0x15 0x02 0x1b>;
compatible = "qcom,msm-hsuart-v14";
interrupt-map = <0x00 0x01 0x00 0x6c 0x00 0x01 0x01 0x00 0xee 0x00>;
interrupt-map-mask = <0xffffffff>;
interrupt-names = "core_irq\0bam_irq";
interrupt-parent = <0x56>;
interrupts = <0x00 0x01 0x02>;
linux,phandle = <0x56>;
phandle = <0x56>;
pinctrl-0 = <0x57>;
pinctrl-1 = <0x57>;
pinctrl-names = "default\0sleep";
qcom,bam-rx-ep-pipe-index = <0x03>;
qcom,bam-tx-ep-pipe-index = <0x02>;
qcom,master-id = <0x56>;
reg = <0x78b0000 0x200 0x7884000 0x23000>;
reg-names = "core_mem\0bam_mem";
status = "disabled";
};
usb2@6000000 {
#address-cells = <0x01>;
#size-cells = <0x01>;
clock-names = "master\0sleep\0mock_utmi";
clocks = <0x02 0x34 0x02 0x35 0x02 0x36>;
compatible = "qca,dwc3";
qca,host = <0x01>;
ranges;
reg = <0x60f8800 0x100>;
reg-names = "qscratch_base";
status = "ok";
dwc3@6000000 {
compatible = "snps,dwc3";
dr_mode = "host";
interrupts = <0x00 0x88 0x00>;
phy-names = "usb2-phy\0usb3-phy";
reg = <0x6000000 0xf8000>;
tx-fifo-resize;
usb-phy = <0x4d 0x4e>;
usb2-host-discon-mask = <0x100>;
usb2-host-discon-phy-misc-reg = <0x24>;
usb2-host-discon-quirk;
usb2-susphy-quirk;
};
};
usb3@8a00000 {
#address-cells = <0x01>;
#size-cells = <0x01>;
clock-names = "master\0sleep\0mock_utmi";
clocks = <0x02 0x37 0x02 0x38 0x02 0x39>;
compatible = "qca,dwc3";
qca,host = <0x01>;
ranges;
reg = <0x8af8800 0x100>;
reg-names = "qscratch_base";
status = "ok";
dwc3@8a00000 {
compatible = "snps,dwc3";
dr_mode = "host";
interrupts = <0x00 0x84 0x00>;
phy-names = "usb2-phy\0usb3-phy";
reg = <0x8a00000 0xf8000>;
tx-fifo-resize;
usb-phy = <0x4b 0x4c>;
usb2-host-discon-mask = <0x100>;
usb2-host-discon-phy-misc-reg = <0x24>;
usb2-host-discon-quirk;
usb2-susphy-quirk;
};
};
watchdog@b017000 {
clocks = <0x47>;
compatible = "qcom,kpss-wdt-ipq40xx";
interrupt-names = "bark_irq";
interrupts = <0x00 0x03 0x00>;
reg = <0xb017000 0x40>;
status = "ok";
timeout-sec = <0x0a>;
wdt_bark_time = <0x10>;
wdt_bite_time = <0x14>;
wdt_en = <0x08>;
wdt_res = <0x04>;
};
wifi@a000000 {
clock-names = "wifi_wcss_cmd\0wifi_wcss_ref\0wifi_wcss_rtc";
clocks = <0x02 0x3a 0x02 0x3b 0x02 0x3c>;
compatible = "qca,wifi-ipq40xx";
core-id = <0x00>;
interrupt-names = "msi0\0msi1\0msi2\0msi3\0msi4\0msi5\0msi6\0msi7\0msi8\0msi9\0msi10\0msi11\0msi12\0msi13\0msi14\0msi15\0legacy";
interrupts = <0x00 0x20 0x01 0x00 0x21 0x01 0x00 0x22 0x01 0x00 0x23 0x01 0x00 0x24 0x01 0x00 0x25 0x01 0x00 0x26 0x01 0x00 0x27 0x01 0x00 0x28 0x01 0x00 0x29 0x01 0x00 0x2a 0x01 0x00 0x2b 0x01 0x00 0x2c 0x01 0x00 0x2d 0x01 0x00 0x2e 0x01 0x00 0x2f 0x01 0x00 0xa8 0x00>;
qca,msi_addr = <0xb006040>;
qca,msi_base = <0x40>;
qcom,cal-len = <0x2f20>;
qcom,cal-offset = <0x1000>;
qcom,mtd-name = "0:ART";
reg = <0xa000000 0x200000>;
reset-names = "wifi_cpu_init\0wifi_radio_srif\0wifi_radio_warm\0wifi_radio_cold\0wifi_core_warm\0wifi_core_cold";
resets = <0x02 0x00 0x02 0x01 0x02 0x02 0x02 0x03 0x02 0x04 0x02 0x05>;
status = "ok";
wifi_led_num = <0x02>;
wifi_led_source = <0x00>;
};
wifi@a800000 {
clock-names = "wifi_wcss_cmd\0wifi_wcss_ref\0wifi_wcss_rtc";
clocks = <0x02 0x3d 0x02 0x3e 0x02 0x3f>;
compatible = "qca,wifi-ipq40xx";
core-id = <0x01>;
interrupt-names = "msi0\0msi1\0msi2\0msi3\0msi4\0msi5\0msi6\0msi7\0msi8\0msi9\0msi10\0msi11\0msi12\0msi13\0msi14\0msi15\0legacy";
interrupts = <0x00 0x30 0x01 0x00 0x31 0x01 0x00 0x32 0x01 0x00 0x33 0x01 0x00 0x34 0x01 0x00 0x35 0x01 0x00 0x36 0x01 0x00 0x37 0x01 0x00 0x38 0x01 0x00 0x39 0x01 0x00 0x3a 0x01 0x00 0x3b 0x01 0x00 0x3c 0x01 0x00 0x3d 0x01 0x00 0x3e 0x01 0x00 0x3f 0x01 0x00 0xa9 0x00>;
qca,msi_addr = <0xb006040>;
qca,msi_base = <0x50>;
qcom,cal-len = <0x2f20>;
qcom,cal-offset = <0x5000>;
qcom,mtd-name = "0:ART";
reg = <0xa800000 0x200000>;
reset-names = "wifi_cpu_init\0wifi_radio_srif\0wifi_radio_warm\0wifi_radio_cold\0wifi_core_warm\0wifi_core_cold";
resets = <0x02 0x06 0x02 0x07 0x02 0x08 0x02 0x09 0x02 0x0a 0x02 0x0b>;
status = "ok";
wifi_led_num = <0x01>;
wifi_led_source = <0x02>;
};
};
};
potentially new DTS
#include "qcom-ipq4019-orbi.dtsi"
/ {
model = "Netgear Orbi RBR50v2";
compatible = "netgear,rbr50v2", "qcom,ipq4019";
aliases {
led-boot = &ledc;
led-failsafe = &ledc;
led-running = &ledc;
led-upgrade = &ledc;
label-mac-device = ð0;
};
nvmem-cells {
caldata_wifi0: caldata_wifi0@1000 {
reg = <0x1000 0x1000>;
label = "wifi0 calibration data";
};
caldata_wifi1: caldata_wifi1@5000 {
reg = <0x5000 0x1000>;
label = "wifi1 calibration data";
};
caldata_wifi2: caldata_wifi2@9000 {
reg = <0x9000 0x1000>;
label = "wifi2 calibration data";
};
};
};
&ledc {
status = "okay";
/*
* This controls at least the power LED via the SoC PWM controller.
* Specific LED lines may need experimentation and trigger setup.
*/
};
&i2c_0 {
status = "okay";
/* both touch related are disabled but i suspect the led controller from TI is discovered later. on this bus*/
};
&nand {
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x0000000 0x100000>;
read-only;
};
/* Add all other partitions as in /proc/mtd... OR do i leave out the paritions for the netgear stuff i dont want like armor and circle I'd rather openwrt uses that space for something else*/
};
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 39 GPIO_ACTIVE_LOW>;
wifi2: wifi@0,0 {
compatible = "qcom,ath10k";
reg = <0x0000 0 0 0 0>;
nvmem-cells = <&caldata_wifi2>;
nvmem-cell-names = "calibration";
};
};
&mdio0 {
phy0: ethernet-phy@0 {
reg = <0>;
reset-gpios = <&tlmm 40 GPIO_ACTIVE_LOW>;
};
};
ð0 {
status = "okay";
phy-handle = <&phy0>;
};
ð1 {
status = "okay";
};
&wifi0 {
status = "okay";
nvmem-cells = <&caldata_wifi0>;
nvmem-cell-names = "calibration";
};
&wifi1 {
status = "okay";
nvmem-cells = <&caldata_wifi1>;
nvmem-cell-names = "calibration";
};
gpio-keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
wps {
label = "wps";
gpios = <&tlmm 16 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
Have you made any more progress here? Seems like you're very close to a working version!