Hi,
I have started to add information/work on Genexis XG6846B.
OEM wise it is now running a fork of OpenWRT called GenXOS (Iopsys from earlier Inteno)
https://openwrt.org/inbox/toh/openwrt/genexis_xg6846b
If anyone wants to contribute, please feel free to help out.
GPL: https://download.iopsys.eu/iopsys/opensdk/bcmopen-PANTHER-6.0-latest
Toolchain: https://download.iopsys.eu/iopsys/toolchain/crosstools-gcc-5.5-linux-4.1-uclibc-1.0.26-glibc-2.26-binutils-2.28.1-Rel1.10-full.tar.bz2
board_6846.c:
#if defined(CONFIG_BCM_KF_ARM_BCM963XX)
/*
<:copyright-BRCM:2013:DUAL/GPL:standard
Copyright (c) 2013 Broadcom
All Rights Reserved
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License, version 2, as published by
the Free Software Foundation (the "GPL").
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by
writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA.
:>
*/
#include <linux/of.h>
#include <linux/of_platform.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
static const char * const bcm63xx_dt_compat[] = {
"brcm,bcm96846",
NULL
};
MACHINE_START(BCM96846, "BCM96846")
.dt_compat = bcm63xx_dt_compat,
MACHINE_END
#endif //CONFIG_BCM_KF_ARM_BCM963XX
boardparms_6846.c:
#include "bp_defs.h"
#include "boardparms.h"
#include "bcmSpiRes.h"
extern BpCmdElem moca6802InitSeq[];
static bp_elem_t g_bcm968460sv[] = {
{bp_cpBoardId, .u.cp = "968460SV"},
{bp_ucPhyType0, .u.uc = BP_ENET_INTERNAL_PHY},
{bp_ucPhyAddress, .u.uc = 0x0},
{bp_usConfigType, .u.us = BP_ENET_CONFIG_MMAP},
{bp_ulPortMap, .u.ul = 0x1f},
{bp_ulPhyId0, .u.ul = 0x01 | MAC_IF_GMII},
{bp_usNetLed0, .u.us = BP_SERIAL_GPIO_0_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulPhyId1, .u.ul = 0x02 | MAC_IF_GMII},
{bp_usNetLed0, .u.us = BP_SERIAL_GPIO_1_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulPhyId2, .u.ul = 0x03 | MAC_IF_GMII},
{bp_usNetLed0, .u.us = BP_SERIAL_GPIO_2_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulPhyId3, .u.ul = 0x04 | MAC_IF_GMII},
{bp_usNetLed0, .u.us = BP_SERIAL_GPIO_3_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulPhyId4, .u.ul = 0x07 | MAC_IF_RGMII | PHY_EXTERNAL | PHY_INTEGRATED_VALID},
{bp_ulPortFlags, .u.ul = PORT_FLAG_TX_INTERNAL_DELAY},
{bp_usMiiMdc, .u.us = BP_GPIO_54_AH},
{bp_usMiiMdio, .u.us = BP_GPIO_55_AH},
{bp_ulMemoryConfig, .u.ul = BP_DDR_SPEED_800_11_11_11 | BP_DDR_TOTAL_SIZE_256MB| BP_DDR_DEVICE_WIDTH_16 | BP_DDR_TOTAL_WIDTH_16BIT},
{bp_usRogueOnuEn, .u.us = BP_GPIO_14_AH},
{bp_usPonLbe, .u.us = BP_GPIO_67_AL},
{bp_usGpioI2cScl, .u.us = BP_GPIO_68_AH},
{bp_usGpioI2cSda, .u.us = BP_GPIO_69_AH},
{bp_usUsbPwrFlt0, .u.us = BP_GPIO_74_AL},
{bp_usUsbPwrOn0, .u.us = BP_GPIO_75_AL},
{bp_usUsbPwrFlt1, .u.us = BP_GPIO_76_AL},
{bp_usUsbPwrOn1, .u.us = BP_GPIO_77_AL},
{bp_ucDspType0, .u.uc = BP_VOIP_DSP},
{bp_ucDspAddress, .u.uc = 0},
{bp_usGpioUart2Sdin, .u.us = BP_GPIO_14_AH},
{bp_usGpioUart2Sdout, .u.us = BP_GPIO_15_AH},
{bp_last}
};
static bp_elem_t g_bcm968460ref[] = {
{bp_cpBoardId, .u.cp = "968460REF"},
{bp_ucPhyType0, .u.uc = BP_ENET_INTERNAL_PHY},
{bp_ucPhyAddress, .u.uc = 0x0},
{bp_usConfigType, .u.us = BP_ENET_CONFIG_MMAP},
{bp_ulPortMap, .u.ul = 0x0f},
{bp_ulPhyId0, .u.ul = 0x01 | MAC_IF_GMII},
{bp_usNetLed0, .u.us = BP_GPIO_52_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulPhyId1, .u.ul = 0x02 | MAC_IF_GMII},
{bp_usNetLed0, .u.us = BP_GPIO_53_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulPhyId2, .u.ul = 0x03 | MAC_IF_GMII},
{bp_usNetLed0, .u.us = BP_GPIO_49_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulPhyId3, .u.ul = 0x04 | MAC_IF_GMII},
{bp_usNetLed0, .u.us = BP_GPIO_44_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulMemoryConfig, .u.ul = BP_DDR_SPEED_800_11_11_11 | BP_DDR_TOTAL_SIZE_256MB| BP_DDR_DEVICE_WIDTH_16 | BP_DDR_TOTAL_WIDTH_16BIT | BP_DDR_PCB_2LAYER},
{bp_usGpioPonTxEn, .u.us = BP_GPIO_40_AH},
{bp_usRogueOnuEn, .u.us = BP_GPIO_14_AH},
{bp_usExtIntrSesBtnWireless, .u.us = BP_EXT_INTR_0 | BP_EXT_INTR_TYPE_IRQ_LOW_LEVEL | BP_EXT_INTR_TYPE_IRQ_SENSE_EDGE},
{bp_usGpio_Intr, .u.us = BP_GPIO_23_AL},
{bp_usExtIntrResetToDefault, .u.us = BP_EXT_INTR_1 | BP_EXT_INTR_TYPE_IRQ_LOW_LEVEL | BP_EXT_INTR_TYPE_IRQ_SENSE_EDGE},
{bp_usGpio_Intr, .u.us = BP_GPIO_55_AL},
{bp_usPonLbe, .u.us = BP_GPIO_67_AL},
{bp_usGpioI2cScl, .u.us = BP_GPIO_68_AH},
{bp_usGpioI2cSda, .u.us = BP_GPIO_69_AH},
{bp_usUsbPwrFlt0, .u.us = BP_GPIO_74_AL},
{bp_usUsbPwrOn0, .u.us = BP_GPIO_75_AL},
{bp_usUsbPwrFlt1, .u.us = BP_GPIO_76_AL},
{bp_usUsbPwrOn1, .u.us = BP_GPIO_77_AL},
{bp_ucDspType0, .u.uc = BP_VOIP_DSP},
{bp_ucDspAddress, .u.uc = 0},
{bp_last}
};
static bp_elem_t g_bcm968460refp[] = {
{bp_cpBoardId, .u.cp = "968460REFP"},
{bp_InvSerdesRxPol, .u.us = pmd_polarity_invert},
{bp_InvSerdesTxPol, .u.us = pmd_polarity_invert},
{bp_usPmdMACEwakeEn, .u.us = BP_GPIO_4_AH},
{bp_usExtIntrPmdAlarm, .u.us = BP_EXT_INTR_2 | BP_EXT_INTR_TYPE_IRQ_HIGH_LEVEL | BP_EXT_INTR_TYPE_IRQ_SENSE_EDGE},
{bp_usGpio_Intr, .u.us = BP_GPIO_14_AH},
{bp_usGpioPmdReset, .u.us = BP_GPIO_40_AL},
{bp_usGpioPonTxEn, .u.us = BP_GPIO_NONE},
{bp_pmdFunc, .u.us = BP_PMD_APD_REG_DISABLED | BP_PMD_APD_TYPE_BOOST},
{bp_elemTemplate, .u.bp_elemp = g_bcm968460ref},
{bp_last}
};
static bp_elem_t g_bcm968461prw[] = {
{bp_cpBoardId, .u.cp = "968461PRW"},
{bp_ucPhyType0, .u.uc = BP_ENET_INTERNAL_PHY},
{bp_ucPhyAddress, .u.uc = 0x0},
{bp_usConfigType, .u.us = BP_ENET_CONFIG_MMAP},
{bp_ulPortMap, .u.ul = 0x0f},
{bp_ulPhyId0, .u.ul = 0x01 | MAC_IF_GMII},
{bp_usNetLed0, .u.us = BP_GPIO_52_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulPhyId1, .u.ul = 0x02 | MAC_IF_GMII},
{bp_usNetLed0, .u.us = BP_GPIO_53_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulPhyId2, .u.ul = 0x03 | MAC_IF_GMII},
{bp_usNetLed0, .u.us = BP_GPIO_49_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulPhyId3, .u.ul = 0x04 | MAC_IF_GMII},
{bp_usNetLed0, .u.us = BP_GPIO_44_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulMemoryConfig, .u.ul = BP_DDR_SPEED_800_11_11_11 | BP_DDR_TOTAL_SIZE_256MB| BP_DDR_DEVICE_WIDTH_16 | BP_DDR_TOTAL_WIDTH_16BIT | BP_DDR_PCB_2LAYER},
{bp_usExtIntrSesBtnWireless, .u.us = BP_EXT_INTR_0 | BP_EXT_INTR_TYPE_IRQ_LOW_LEVEL | BP_EXT_INTR_TYPE_IRQ_SENSE_EDGE},
{bp_usGpio_Intr, .u.us = BP_GPIO_23_AL},
{bp_usExtIntrResetToDefault, .u.us = BP_EXT_INTR_1 | BP_EXT_INTR_TYPE_IRQ_LOW_LEVEL | BP_EXT_INTR_TYPE_IRQ_SENSE_EDGE},
{bp_usGpio_Intr, .u.us = BP_GPIO_55_AL},
{bp_usPonLbe, .u.us = BP_GPIO_67_AL},
{bp_usGpioI2cScl, .u.us = BP_GPIO_68_AH},
{bp_usGpioI2cSda, .u.us = BP_GPIO_69_AH},
{bp_usUsbPwrFlt0, .u.us = BP_GPIO_74_AL},
{bp_usUsbPwrOn0, .u.us = BP_GPIO_75_AL},
{bp_usUsbPwrFlt1, .u.us = BP_GPIO_76_AL},
{bp_usUsbPwrOn1, .u.us = BP_GPIO_77_AL},
{bp_usGpioLedSesWireless, .u.us = BP_GPIO_5_AL},
{bp_InvSerdesRxPol, .u.us = pmd_polarity_invert},
{bp_InvSerdesTxPol, .u.us = pmd_polarity_invert},
{bp_usPmdMACEwakeEn, .u.us = BP_GPIO_4_AH},
{bp_usExtIntrPmdAlarm, .u.us = BP_EXT_INTR_2 | BP_EXT_INTR_TYPE_IRQ_HIGH_LEVEL | BP_EXT_INTR_TYPE_IRQ_SENSE_EDGE},
{bp_usGpio_Intr, .u.us = BP_GPIO_14_AH},
{bp_usGpioPmdReset, .u.us = BP_GPIO_40_AL},
{bp_pmdFunc, .u.us = BP_PMD_APD_REG_DISABLED | BP_PMD_APD_TYPE_BOOST},
{bp_ucDspType0, .u.uc = BP_VOIP_DSP},
{bp_ucDspAddress, .u.uc = 0},
{bp_last}
};
static bp_elem_t g_bcm968462ref[] = {
{bp_cpBoardId, .u.cp = "968462REF"},
{bp_ucPhyType0, .u.uc = BP_ENET_INTERNAL_PHY},
{bp_ucPhyAddress, .u.uc = 0x0},
{bp_usConfigType, .u.us = BP_ENET_CONFIG_MMAP},
{bp_ulPortMap, .u.ul = 0x0f},
{bp_ulPhyId0, .u.ul = 0x01 | MAC_IF_MII},
{bp_usOamIndex, .u.us = 3},
{bp_ucPhyDevName, .u.cp = "eth3"},
{bp_usNetLed0, .u.us = BP_GPIO_52_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_FAE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_FAE},
{bp_ulPhyId1, .u.ul = 0x02 | MAC_IF_MII},
{bp_usOamIndex, .u.us = 2},
{bp_ucPhyDevName, .u.cp = "eth2"},
{bp_usNetLed0, .u.us = BP_GPIO_53_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_FAE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_FAE},
{bp_ulPhyId2, .u.ul = 0x03 | MAC_IF_MII},
{bp_usOamIndex, .u.us = 1},
{bp_ucPhyDevName, .u.cp = "eth1"},
{bp_usNetLed0, .u.us = BP_GPIO_49_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_FAE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_FAE},
{bp_ulPhyId3, .u.ul = 0x04 | MAC_IF_GMII},
{bp_usOamIndex, .u.us = 0},
{bp_ucPhyDevName, .u.cp = "eth0"},
{bp_usNetLed0, .u.us = BP_GPIO_44_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulMemoryConfig, .u.ul = BP_DDR_SPEED_800_11_11_11 | BP_DDR_TOTAL_SIZE_512MB| BP_DDR_DEVICE_WIDTH_8 | BP_DDR_TOTAL_WIDTH_8BIT | BP_DDR_PCB_2LAYER},
{bp_usExtIntrResetToDefault, .u.us = BP_EXT_INTR_1 | BP_EXT_INTR_TYPE_IRQ_LOW_LEVEL | BP_EXT_INTR_TYPE_IRQ_SENSE_EDGE},
{bp_usGpio_Intr, .u.us = BP_GPIO_45_AL},
{bp_usGpioI2cScl, .u.us = BP_GPIO_68_AH},
{bp_usGpioI2cSda, .u.us = BP_GPIO_69_AH},
{bp_usUsbPwrFlt1, .u.us = BP_GPIO_76_AL},
{bp_usUsbPwrOn1, .u.us = BP_GPIO_77_AL},
{bp_usPonLbe, .u.us = BP_GPIO_67_AL},
{bp_InvSerdesRxPol, .u.us = pmd_polarity_invert},
{bp_InvSerdesTxPol, .u.us = pmd_polarity_invert},
{bp_usPmdMACEwakeEn, .u.us = BP_GPIO_4_AH},
{bp_usExtIntrPmdAlarm, .u.us = BP_EXT_INTR_2 | BP_EXT_INTR_TYPE_IRQ_HIGH_LEVEL | BP_EXT_INTR_TYPE_IRQ_SENSE_EDGE},
{bp_usGpio_Intr, .u.us = BP_GPIO_14_AH},
{bp_usGpioPmdReset, .u.us = BP_GPIO_40_AL},
{bp_pmdFunc, .u.us = BP_PMD_APD_REG_DISABLED | BP_PMD_APD_TYPE_BOOST},
{bp_usRogueOnuEn, .u.us = BP_GPIO_14_AH},
{bp_ucDspType0, .u.uc = BP_VOIP_DSP},
{bp_ucDspAddress, .u.uc = 0},
{bp_last}
};
static bp_elem_t g_bcm968462spw[] = {
{bp_cpBoardId, .u.cp = "968462SPW"},
{bp_ucPhyType0, .u.uc = BP_ENET_INTERNAL_PHY},
{bp_ucPhyAddress, .u.uc = 0x0},
{bp_usConfigType, .u.us = BP_ENET_CONFIG_MMAP},
{bp_ulPortMap, .u.ul = 0x0f},
{bp_ulPhyId0, .u.ul = 0x01 | MAC_IF_GMII},
{bp_usNetLed0, .u.us = BP_GPIO_52_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulPhyId1, .u.ul = 0x02 | MAC_IF_GMII},
{bp_usNetLed0, .u.us = BP_GPIO_53_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulPhyId2, .u.ul = 0x03 | MAC_IF_GMII},
{bp_usNetLed0, .u.us = BP_GPIO_49_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulPhyId3, .u.ul = 0x04 | MAC_IF_GMII},
{bp_usNetLed0, .u.us = BP_GPIO_44_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulMemoryConfig, .u.ul = BP_DDR_SPEED_800_11_11_11 | BP_DDR_TOTAL_SIZE_512MB| BP_DDR_DEVICE_WIDTH_8 | BP_DDR_TOTAL_WIDTH_8BIT | BP_DDR_PCB_2LAYER},
{bp_usExtIntrResetToDefault, .u.us = BP_EXT_INTR_1 | BP_EXT_INTR_TYPE_IRQ_LOW_LEVEL | BP_EXT_INTR_TYPE_IRQ_SENSE_EDGE},
{bp_usGpio_Intr, .u.us = BP_GPIO_45_AL},
{bp_usGpioI2cScl, .u.us = BP_GPIO_68_AH},
{bp_usGpioI2cSda, .u.us = BP_GPIO_69_AH},
{bp_usUsbPwrFlt1, .u.us = BP_GPIO_76_AL},
{bp_usUsbPwrOn1, .u.us = BP_GPIO_77_AL},
{bp_usPonLbe, .u.us = BP_GPIO_67_AL},
{bp_InvSerdesRxPol, .u.us = pmd_polarity_invert},
{bp_InvSerdesTxPol, .u.us = pmd_polarity_invert},
{bp_usPmdMACEwakeEn, .u.us = BP_GPIO_4_AH},
{bp_usExtIntrPmdAlarm, .u.us = BP_EXT_INTR_2 | BP_EXT_INTR_TYPE_IRQ_HIGH_LEVEL | BP_EXT_INTR_TYPE_IRQ_SENSE_EDGE},
{bp_usGpio_Intr, .u.us = BP_GPIO_14_AH},
{bp_usGpioPmdReset, .u.us = BP_GPIO_40_AL},
{bp_pmdFunc, .u.us = BP_PMD_APD_REG_DISABLED | BP_PMD_APD_TYPE_BOOST},
{bp_usRogueOnuEn, .u.us = BP_GPIO_14_AH},
{bp_ucDspType0, .u.uc = BP_VOIP_DSP},
{bp_ucDspAddress, .u.uc = 0},
{bp_last}
};
static bp_elem_t g_bcm968462xsv[] = {
{bp_cpBoardId, .u.cp = "968462XSV"},
{bp_ucPhyType0, .u.uc = BP_ENET_INTERNAL_PHY},
{bp_ucPhyAddress, .u.uc = 0x0},
{bp_usConfigType, .u.us = BP_ENET_CONFIG_MMAP},
{bp_ulPortMap, .u.ul = 0x0f},
{bp_ulPhyId0, .u.ul = 0x01 | MAC_IF_GMII},
{bp_usNetLed0, .u.us = BP_GPIO_52_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulPhyId1, .u.ul = 0x02 | MAC_IF_GMII},
{bp_usNetLed0, .u.us = BP_GPIO_53_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulPhyId2, .u.ul = 0x03 | MAC_IF_GMII},
{bp_usNetLed0, .u.us = BP_GPIO_49_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulPhyId3, .u.ul = 0x04 | MAC_IF_GMII},
{bp_usNetLed0, .u.us = BP_GPIO_44_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulMemoryConfig, .u.ul = BP_DDR_SPEED_800_11_11_11 | BP_DDR_TOTAL_SIZE_512MB| BP_DDR_DEVICE_WIDTH_8 | BP_DDR_TOTAL_WIDTH_8BIT},
{bp_usGpioI2cScl, .u.us = BP_GPIO_68_AH},
{bp_usGpioI2cSda, .u.us = BP_GPIO_69_AH},
{bp_usUsbPwrFlt1, .u.us = BP_GPIO_76_AL},
{bp_usUsbPwrOn1, .u.us = BP_GPIO_77_AL},
{bp_usRogueOnuEn, .u.us = BP_GPIO_14_AH},
{bp_usPonLbe, .u.us = BP_GPIO_67_AL},
{bp_usGpioWanSignalDetected, .u.us = BP_GPIO_15_AH},
{bp_last}
};
static bp_elem_t g_bcm968460rgw[] = {
{bp_cpBoardId, .u.cp = "968460RGW"},
{bp_ulMemoryConfig, .u.ul = BP_DDR_SPEED_800_11_11_11 | BP_DDR_TOTAL_SIZE_256MB| BP_DDR_DEVICE_WIDTH_16 | BP_DDR_TOTAL_WIDTH_16BIT},
{bp_usPcmSdin, .u.us = BP_GPIO_0_AH},
{bp_usPcmSdout, .u.us = BP_GPIO_1_AH},
{bp_usPcmClk, .u.us = BP_GPIO_2_AH},
{bp_usPcmFs, .u.us = BP_GPIO_3_AH},
{bp_usExtIntrResetToDefault, .u.us = BP_EXT_INTR_0 | BP_EXT_INTR_TYPE_IRQ_LOW_LEVEL | BP_EXT_INTR_TYPE_IRQ_SENSE_EDGE},
{bp_usGpio_Intr, .u.us = BP_GPIO_19_AL},
{bp_usGpioI2cScl, .u.us = BP_GPIO_68_AH},
{bp_usGpioI2cSda, .u.us = BP_GPIO_69_AH},
{bp_ucPhyType0, .u.uc = BP_ENET_INTERNAL_PHY},
{bp_ucPhyAddress, .u.uc = 0x0},
{bp_usConfigType, .u.us = BP_ENET_CONFIG_MMAP},
{bp_ulPortMap, .u.ul = 0x1f},
{bp_ulPhyId0, .u.ul = 0x01 | MAC_IF_GMII},
{bp_ulPhyId1, .u.ul = 0x02 | MAC_IF_GMII},
{bp_ulPhyId2, .u.ul = 0x03 | MAC_IF_GMII},
{bp_ulPhyId3, .u.ul = 0x04 | MAC_IF_GMII},
{bp_ulPhyId4, .u.ul = 0x07 | MAC_IF_RGMII | PHY_EXTERNAL | PHY_INTEGRATED_VALID},
{bp_ulPortFlags, .u.ul = PORT_FLAG_TX_INTERNAL_DELAY},
{bp_usMiiMdc, .u.us = BP_GPIO_54_AH},
{bp_usMiiMdio, .u.us = BP_GPIO_55_AH},
{bp_usPonLbe, .u.us = BP_GPIO_67_AL},
{bp_usUsbPwrFlt0, .u.us = BP_GPIO_74_AL},
{bp_usUsbPwrOn0, .u.us = BP_GPIO_75_AL},
{bp_usUsbPwrFlt1, .u.us = BP_GPIO_76_AL},
{bp_usUsbPwrOn1, .u.us = BP_GPIO_77_AL},
{bp_InvSerdesRxPol, .u.us = pmd_polarity_invert},
{bp_InvSerdesTxPol, .u.us = pmd_polarity_invert},
{bp_usPmdMACEwakeEn, .u.us = BP_GPIO_4_AH},
{bp_usExtIntrPmdAlarm, .u.us = BP_EXT_INTR_2 | BP_EXT_INTR_TYPE_IRQ_HIGH_LEVEL | BP_EXT_INTR_TYPE_IRQ_SENSE_EDGE},
{bp_usGpio_Intr, .u.us = BP_GPIO_14_AH},
{bp_usGpioPmdReset, .u.us = BP_GPIO_40_AL},
{bp_pmdFunc, .u.us = BP_PMD_APD_REG_DISABLED | BP_PMD_APD_TYPE_BOOST},
{bp_last}
};
static bp_elem_t g_bcm968462egr[] = {
{bp_cpBoardId, .u.cp = "968462EGR"},
{bp_ucPhyType0, .u.uc = BP_ENET_INTERNAL_PHY},
{bp_ucPhyAddress, .u.uc = 0x0},
{bp_usConfigType, .u.us = BP_ENET_CONFIG_MMAP},
{bp_ulPortMap, .u.ul = 0x0f},
{bp_ulPhyId0, .u.ul = 0x01 | MAC_IF_GMII},
{bp_usNetLed0, .u.us = BP_GPIO_52_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulPhyId1, .u.ul = 0x02 | MAC_IF_GMII},
{bp_usNetLed0, .u.us = BP_GPIO_53_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulPhyId2, .u.ul = 0x03 | MAC_IF_GMII},
{bp_usNetLed0, .u.us = BP_GPIO_49_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulPhyId3, .u.ul = 0x04 | MAC_IF_GMII},
{bp_usNetLed0, .u.us = BP_GPIO_44_AL},
{bp_ulNetLedLink, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_ulNetLedActivity, .u.ul = BP_NET_LED_SPEED_GBE},
{bp_InvSerdesRxPol, .u.us = pmd_polarity_invert},
{bp_InvSerdesTxPol, .u.us = pmd_polarity_invert},
{bp_usPmdMACEwakeEn, .u.us = BP_GPIO_4_AH},
{bp_usExtIntrPmdAlarm, .u.us = BP_EXT_INTR_2 | BP_EXT_INTR_TYPE_IRQ_HIGH_LEVEL | BP_EXT_INTR_TYPE_IRQ_SENSE_EDGE},
{bp_usGpio_Intr, .u.us = BP_GPIO_14_AH},
{bp_usGpioPmdReset, .u.us = BP_GPIO_40_AL},
{bp_pmdFunc, .u.us = BP_PMD_APD_REG_DISABLED | BP_PMD_APD_TYPE_BOOST},
{bp_usPcmSdin, .u.us = BP_GPIO_0_AH},
{bp_usPcmSdout, .u.us = BP_GPIO_1_AH},
{bp_usPcmClk, .u.us = BP_GPIO_2_AH},
{bp_usPcmFs, .u.us = BP_GPIO_3_AH},
{bp_ulMemoryConfig, .u.ul = BP_DDR_SPEED_800_11_11_11 | BP_DDR_TOTAL_SIZE_128MB| BP_DDR_DEVICE_WIDTH_8 | BP_DDR_TOTAL_WIDTH_8BIT | BP_DDR_PCB_2LAYER},
{bp_usExtIntrResetToDefault, .u.us = BP_EXT_INTR_1 | BP_EXT_INTR_TYPE_IRQ_LOW_LEVEL | BP_EXT_INTR_TYPE_IRQ_SENSE_EDGE},
{bp_usGpio_Intr, .u.us = BP_GPIO_45_AL},
{bp_usGpioI2cScl, .u.us = BP_GPIO_68_AH},
{bp_usGpioI2cSda, .u.us = BP_GPIO_69_AH},
{bp_usUsbPwrFlt1, .u.us = BP_GPIO_76_AL},
{bp_usUsbPwrOn1, .u.us = BP_GPIO_77_AL},
{bp_usGpioLedUSB2, .u.us = BP_SERIAL_GPIO_15_AL},
{bp_usGpioVoip1Led, .u.us = BP_SERIAL_GPIO_11_AL},
{bp_ucDspType0, .u.uc = BP_VOIP_DSP},
{bp_ucDspAddress, .u.uc = 0},
{bp_last}
};
bp_elem_t * g_BoardParms[] = {g_bcm968460sv, g_bcm968460ref, g_bcm968460refp, g_bcm968461prw, g_bcm968462ref, g_bcm968462spw, g_bcm968462xsv, g_bcm968460rgw, g_bcm968462egr, 0};
Have a look at the following pages. I think most of the work is done already.
That is for another model, this one is a much newer one, hence the XG6846B model, the one you are linking to is the XG6846
I managed to get U-Boot to start on the device, and from U-Boot I managed to get Linux to boot. Warning: all EXTREMELY basic from initramfs and bogus reports from dmesg etc. But you get to prompt and it even seems to recognize the NAND flash. I will try to post any progress I make on this web page, so others can use it as a base if I don't work on it.
https://dflund.se/~triad/krad/genexis-xg6846b/
Great job!
I managed to enable NAND support in U-Boot and browsed around in the volume (see my linked page). The binary U-Boot is updated and also pushed the sources. Maybe you can check if your device has the same flash layout with a 256KB "loader" partition and a 251MB "image" that can be mounted and inspected and further the partitions named e.g. "rootfs_0" and "rootfs_1" can be mounted and inspected.
New URL for device page, since the old was wrongly named:
https://openwrt.org/toh/genexis/xg6846b
Initial device tree and bindings and compatible strings and what not for BCM6846 and XG6846B submitted to the mailing list for inclusion into Linux v6.13:
https://lore.kernel.org/linux-arm-kernel/20241019-genexis-xg6846b-base-v3-0-8375a0e1f89f@linaro.org/
Hi @linusw ,
I am just here to say thank you. Long story short I have a few devices with the BCM96856.
I actually did not know you could bootstrap u-boot from a running bootloader. After spending some time and following your work I managed to boot u-boot.
I get lost with all the cpus from broadcom and their naming. I believe yours "bcm96846" and this one "bcm96856" are similar.
This is the boot log
----
BTRM
V1.0
R1.0
L1CD
MMUI
MMU9
DATA
ZBBS
MAIN
OTP?
OTPP
USBT
EMMC
IMG?
IMGL
UHD?
UHDP
RLO?
RLOP
UBI?
UBIP
PASS
----
HELO
5.0207p2-1.0.38-164.255
CPU0
L1CD
MMUI
MMUC
ZBBS
MAIN
SEND
Boot Strap Register: 0x530086f6
rom_emmc: emmc initialized!
rom_emmc: MCB from NVRAM: 0x00001527
NVRAM memcfg 0x1527
MCB chksum 0x7240c6dd, config 0x1527
MemsysInit hpg0_generic_aarch64 3.5.1.1 20171009
DDR3
8262BF80 80180000 801A0000 00000000 00000000 0030476E
MCB rev=0x00000501 Ref ID=0x0476E Sub Bld=0x003
Dram Timing 11-11-11
start of memsys_begin
mc_cfg_init(): Initialize the default values on mc_cfg
init_memc_dram_profile(): Initializing MEMC DRAM profile
---------------------------------------------------------------
MEMC DRAM profile (memc_dram_profile_struct) values:
dram_type = DDR3
====================================================
PART values:
part_speed_grade = 1600 CL11
part_size_Mbits = 8192 (DRAM size in MegaBits)
part_row_bits = 16 (number of row bits)
part_col_bits = 10 (number of column bits)
part_ba_bits = 3 (number of bank bits)
part_width_bits = 16 (DRAM width in bits)
NUMER OF PARTS:
part_num = 1 (Number of parts)
TOTAL values:
total_size_Mbits = 8192 (DRAM size in MegaBits)
total_cs_bits = 0 (number of cs bits, for dual_rank mode)
total_width_bits = 16 (DRAM width in bits)
total_burst_bytes = 16 (Number of bytes per DRAM access)
total_max_byte_addr = 0x3fffffff (Maximum/last DRAM byte address)
(Number of bits in total_max_byte_addr is 30)
(i.e. total_max_byte_addr goes from bit 0 to bit 29)
ddr_2T_mode = 0
ddr_hdp_mode = 1
large_page = 1
ddr_dual_rank = 0
cs_mode = 0
MEMC timing (memc_dram_timing_cfg_struct) values:
====================================================
MC_CHN_TIM_TIM1_0 register fields:
tCwl = 8
tRP = 11
tCL = 11
tRCD = 11
MC_CHN_TIM_TIM1_1 register fields:
tCCD_L = 4
tCCD = 4
tRRD_L = 6
tRRD = 6
MC_CHN_TIM_TIM1_2 register fields:
tFAW = 32
tRTP = 6
tRCr = 39
MC_CHN_TIM_TIM1_3 register fields:
tWTR_L = 6
tWTR = 6
tWR_L = 12
tWR = 12
MC_CHN_TIM_TIM2 register fields:
tR2R = 0
tR2W = 2
tW2R = 2
tW2W = 0
tAL = 0
tRFC = 280
====================================================
%1 SSC enabled
Poll PHY Status register
PHY Status= 1
Disable Auto-Refresh
[0x80180200] = 0x00000305
End of memsys_begin
Add/Ctl Alignment
Coarse Adj=0x087 deg, cmd steps=0x0D4
reg 0x801A0090 set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A0094 set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A0098 set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A009C set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A00A0 set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A00A4 set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A00A8 set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A00AC set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A00B0 set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A00B4 set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A00B8 set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A00BC set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A00C0 set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A00C4 set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A00C8 set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A00CC set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A00D0 set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A00D4 set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A00D8 set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A00DC set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A00E0 set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A00E4 set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A00E8 set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A00EC set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A00F0 set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A00F4 set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A00F8 set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A00FC set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A0100 set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A0108 set to VDL 0x051 with Fine Adj=0x01 deg
reg 0x801A010C set to VDL 0x051 with Fine Adj=0x01 deg
HP RX TRIM
itrim = 0x0
lstrim = 0x9
ZQ Cal HP PHY
R in Ohm
P: Finger=0x364 Term=0x7C Drv=0x27
N: Finger=0x336 Term=0x75 Drv=0x27
PLL Ref(Hz)=0x02FAF080 UI STEPS=0x06A
DDR CLK(MHz)=0x31B WL CLK dly(ps)=0x0C8 bitT(ps)=0x274 VDLsize(fs)=0x1724 CLK_VDL=0x022
start of memc_init
[0x80180004] = 0x0110061f
[0x80180234] = 0x00001101
Enable Auto-Refresh
[0x80180110] = 0x11100f0e
[0x80180114] = 0x15141312
[0x80180118] = 0x19181716
[0x8018011c] = 0x1d1c1b1a
[0x80180124] = 0x04000000
[0x80180128] = 0x08070605
[0x8018012c] = 0x00000a09
[0x80180134] = 0x000d0c0b
Writing to MC_CHN_CFG_CNFG reg; data=0x00000000
[0x80180100] = 0x00000000
cfg_memc_timing_ctrl() Called
[0x80180214] = 0x080b0b0b
[0x80180218] = 0x04040606
[0x8018021c] = 0x20000627
[0x80180220] = 0x06060c0c
[0x80180224] = 0x12000118
End of memc_init
start of pre_shmoo
[0x80180004] = 0xc110071f
end of pre_shmoo
SHMOO 28nm
801A0000 80180800 00000000 00020000 00000000
Shmoo WL
One UI Steps : 0x77
auto-clk result = 00B (filter=0C steps)
initial CLK shift = 022
final CLK shift = 00B
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111
00000000001111111111222222222233333333334444444444555555555566666666667777777777888888888899999999990000000000111111111
01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678
00 S----------------------------------------X-----------------------------------------------------------------------------
01 S--------------------------------------------------X-------------------------------------------------------------------
Shmoo RD En
FORCED WR ODT = 0x00001800
DQSN DRIVE PAD CONTROL (from) (to)
B0 00039ED5 00079ED5
B1 00039ED5 00079ED5
B0 RISE UI=1 VDL=1E PICK UI=2 VDL=1E
B1 RISE UI=1 VDL=31 PICK UI=2 VDL=31
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111
00000000001111111111222222222233333333334444444444555555555566666666667777777777888888888899999999990000000000111111111
01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678
00 --S----------------------++++-X+++++++++++++++-------------------------------------------------------------------------
01 --S----------------------------------------------X+++++++++++++++------------------------------------------------------
Shmoo RD DQ NP
DQS :
B0 VDL=6A ok
B1 VDL=6A ok
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111
00000000001111111111222222222233333333334444444444555555555566666666667777777777888888888899999999990000000000111111111
01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678
00 -----------------+++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++++------
01 ----------------++++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++++------
02 ----------------+++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++++-------
03 -----------+++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++++------------
04 ----------------++++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++++---------
05 --------------+++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++++---------
06 -------------++++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++++---------
07 -----------++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++---------------
08 -------------------+++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++---------
09 -----------------------++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++---
10 ----------------+++++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++++--------
11 ------------------+++++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++++------
12 ----------------------+++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++-----
13 --------------------++++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++++-----
14 ------------------++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++--------
15 ---------------------++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++-----
Shmoo RD DQ P
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111
00000000001111111111222222222233333333334444444444555555555566666666667777777777888888888899999999990000000000111111111
01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678
00 ----------------++++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++++------
01 --------------+++++++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++++++------
02 --------------++++++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++++++-------
03 ----------++++++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++++++-----------
04 ----------------++++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++++---------
05 --------------+++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++++---------
06 -------------++++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++++---------
07 ----------+++++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++++--------------
08 --------------------+++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++-------
09 ----------------------+++++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++++--
10 -----------------+++++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++++-------
11 ------------------+++++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++++------
12 ---------------------++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++-----
13 ---------------------++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++-----
14 ------------------++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++--------
15 ----------------------++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++----
Shmoo RD DQ N
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111
00000000001111111111222222222233333333334444444444555555555566666666667777777777888888888899999999990000000000111111111
01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678
00 -----------------++++++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++++++----
01 ----------------++++++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++++++-----
02 --------------+++++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++++++-----
03 -----------++++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++++-----------
04 ----------------+++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++++-------
05 --------------++++++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++++++-------
06 -------------++++++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++++++--------
07 ----------+++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++++-------------
08 -----------------++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++---------
09 -------------------++++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++++---
10 -------------++++++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++++++--------
11 -------------++++++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++++++-----
12 ---------------+++++++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++++++-----
13 ----------------+++++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++++++---
14 --------------++++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++++--------
15 -----------------++++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++++-----
RD DQS adjustments :
BL0: Start: 0x6A Final: 0x6A
BL1: Start: 0x6A Final: 0x6A
Shmoo WR DQ
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111
00000000001111111111222222222233333333334444444444555555555566666666667777777777888888888899999999990000000000111111111
01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678
00 ---------+++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++-------------------
01 ---------+++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++------------------
02 --------+++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++--------------------
03 ----+++++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++++--------------------
04 -----------+++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++---------------------
05 ---------++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++--------------------
06 --------+++++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++++----------------
07 ------++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++-----------------------
08 ----------------++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++--------------
09 ----------------++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++-------------
10 -------------++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++----------------
11 ---------------+++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++------------
12 -----------++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++-------------------
13 ----------------+++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++----------------
14 ----------++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++-------------------
15 ------------++++++++++++++++++++++++++++++++++++++++++++++X++++++++++++++++++++++++++++++++++++++++++++++--------------
Shmoo WR DM
WR DM
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111111111111
00000000001111111111222222222233333333334444444444555555555566666666667777777777888888888899999999990000000000111111111
01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678
00 ----+++++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++++--------------------
01 --------+++++++++++++++++++++++++++++++++++++++++++++X+++++++++++++++++++++++++++++++++++++++++++++--------------------
start of memsys_end
[0x80180004] = 0x8110071f
[0x80180010] = 0x0000000a
end of memsys_end
DDR test done successfully
rom:emmc: GPT init success!
...Searching emmcflash0.mdata1_1 for seq_num
Image 1 has Sequence number 031, committed: 1
...Searching emmcflash0.mdata2_1 for seq_num
Image 2 has Sequence number 030, committed: 1
Loaded cferam.000 (2338252 bytes) from latest image in emmcflash0.bootfs1 ...
rom_emmc: emmc_ready_boot
EMM5
Base: 5.2_07p2
CFE version 1.0.38-164.255 for BCM96856 (64bit,SP,LE)
Build Date: Wed Jul 17 18:02:18 CST 2024 (crazy_liang@621e48e3e73e)
Copyright (C) 2000-2015 Broadcom Corporation.
SEND
Boot Strap Register: 0x530086f6
Chip ID: BCM68360_B1, Broadcom B53 Dual Core: 1500MHz
RDP: 1400MHz
Total Memory: 1073741824 bytes (1024MB)
Initializing eMMC (v0.94). 2013.11.12.
GPT partitions exist, Updating cfe partitions!
[Booted from eMMC BOOT1 Partition]
EMMC Addr Mode: Sector, ReadBlkLen 512 bytes, WriteBlklen 512 bytes
EMMC device: Toshiba 008GB0 v0.0, Serial 0x9e8528f2, Size 3740MB
[eMMC Partition Information] :
Partition : Physical, Partitioned
- Data : 003728MB, 003507MB
- Boot1 : 000004MB, 004096KB
- Boot2 : 000004MB, 004096KB
CPU1
Error no gpio number defined for external interrupt 24579!
Dump Current setting of SWREGs
1.0D, reg=0x00, val=0xc690
1.0D, reg=0x01, val=0x0d06
1.0D, reg=0x02, val=0xcb12
1.0D, reg=0x03, val=0x5372
1.0D, reg=0x04, val=0x0000
1.0D, reg=0x05, val=0x0702
1.0D, reg=0x06, val=0xb000
1.0D, reg=0x07, val=0x0029
1.0D, reg=0x08, val=0x0c02
1.0D, reg=0x09, val=0x0071
1.8 , reg=0x00, val=0xc690
1.8 , reg=0x01, val=0x0d06
1.8 , reg=0x02, val=0xcb12
1.8 , reg=0x03, val=0x5370
1.8 , reg=0x04, val=0x0000
1.8 , reg=0x05, val=0x0702
1.8 , reg=0x06, val=0xb000
1.8 , reg=0x07, val=0x0029
1.8 , reg=0x08, val=0x0c02
1.8 , reg=0x09, val=0x0071
1.5 , reg=0x00, val=0xc690
1.5 , reg=0x01, val=0x0d06
1.5 , reg=0x02, val=0xcb12
1.5 , reg=0x03, val=0x5370
1.5 , reg=0x04, val=0x0000
1.5 , reg=0x05, val=0x0702
1.5 , reg=0x06, val=0xb000
1.5 , reg=0x07, val=0x0029
1.5 , reg=0x08, val=0x0c02
1.5 , reg=0x09, val=0x0071
1.0A, reg=0x00, val=0xc690
1.0A, reg=0x01, val=0x0d06
1.0A, reg=0x02, val=0xcb12
1.0A, reg=0x03, val=0x5370
1.0A, reg=0x04, val=0x0000
1.0A, reg=0x05, val=0x0702
1.0A, reg=0x06, val=0xb000
1.0A, reg=0x07, val=0x0029
1.0A, reg=0x08, val=0x0c02
1.0A, reg=0x09, val=0x0071
Take PMC out of reset
waiting for PMC finish booting
PMC rev: 3.1.9.427360 running
pmc_init:PMC using DQM mode
Board IP address : 192.168.1.1:ffffff00
Host IP address : 192.168.1.100
Gateway IP address :
Run from flash/host/tftp (f/h/c) : f
Default host run file name : vmlinux
Default host flash file name : bcm963xx_fs_kernel
Boot delay (0-9 seconds) : 1
Boot image (0=latest, 1=previous) : 0
Default host ramdisk file name :
Default ramdisk store address :
Default DTB file name :
Board Id : ET-HOMEBOX
Number of MAC Addresses (1-64) : 6
Base MAC Address : d4:86:60:b4:c1:b6
PSI Size (1-512) KBytes : 128
Enable Backup PSI [0|1] : 0
System Log Size (0-256) KBytes : 0
Auxillary File System Size Percent: 0
GPON Serial Number : "41-52-53-41-32-30-31-37-30-30-30-31"
GPON Password : "30-30-30-30-30-30-30-30-30-30"
XGS-PON Password : "30-30-30-30-30-30-30-30-30-30-30-30-30-30-30-30-30-30-30-30-30-30-30-30-30-30-30-30-30-3"
RNR_TBLS memory allocation (8-13) (MB) : 8
FPM_POOL memory allocation (MB) : 64
DHD 0 memory allocation (MB) : 14
DHD 1 memory allocation (MB) : 14
DHD 2 memory allocation (MB) : 0
Device Pin : "65883150"
WLan Feature : 0x00
Voice Board Configuration (0-2) : SI32280_ISI_CB
ARC Serial Number : "J2108013071"
ARC DECT RFPI : "0000222220"
ARC Manuf Model : "ET-HOMEBOX"
ARC Manuf HW Version : "01"
ARC Image Clone Flag [0|12|21] : "0"
ARC MP Test : "0"
ARC WLAN Country Code : "SA"
ARC WLAN Territory Code : "SA/01"
ARC Temp Boot Flag : "0"
*** Press any key to stop auto run (1 seconds) ***
Auto run second count down: 1
Toggle reset of XRDP core...
Toggle reset of XRDP core...
Parse board Params Start
SGMII PLL locked
XRDP INIT start
XRDP INIT FPM Address 000000003e000000
ddr base address is 0x000000003e000000
data_path_init_basic: Restore HW configuration
access_log_restore: 10021 entries processed
data_path_init_basic: Restore HW configuration done. rc=0
XRDP INIT Done
MAC and PHY Init Start
Detecting PHYs...
Lift PHY at address 7 out of Reset by GPIO:8 Active Low
MDIO Error: MDIO got failure status on phy 7
Loading firmware into detected PHYs...
PHYID: 0xae0251f1
51F1: CORE_SHD1C_09: 0x18 CORE_SHD1C_0D: 0x30 CORE_SHD1C_0E: 0xe CORE_EXP04: 0x0
PHYID: 0xae0251f1
51F1: CORE_SHD1C_09: 0x18 CORE_SHD1C_0D: 0x30 CORE_SHD1C_0E: 0xe CORE_EXP04: 0x0
PHYID: 0xae0251f1
51F1: CORE_SHD1C_09: 0x18 CORE_SHD1C_0D: 0x30 CORE_SHD1C_0E: 0xe CORE_EXP04: 0x0
PHYID: 0xae0251f1
51F1: CORE_SHD1C_09: 0x18 CORE_SHD1C_0D: 0x30 CORE_SHD1C_0E: 0xe CORE_EXP04: 0x0
Timed out waiting for command complete
Failed to execute cmd code: 0x8016
internal_open: Done
Creating CPU ring for queue number 16 with 512 packets descriptor=0x0000000001241250, size_of_entry 8
Done initializing Ring 16 Base=0x000000200124ab40 num of entries= 512 RDD Base=124ab40 descriptor=0x0000000001241250
Creating CPU ring for queue number 0 with 1024 packets descriptor=0x0000000001240950, size_of_entry 16
Done initializing Ring 0 Base=0x0000002001603700 num of entries= 1024 RDD Base=1603700 descriptor=0x0000000001240950
CPU ring init Done
No active ports
CFE> Port 0: EGPHY:GMII:0x1 - Link Up 1000 Mbps Full duplex
Setting as Active
web info: Waiting for connection on socket 0.
CFE>
CFE>
CFE> ldt bcm96856.dtb
Loading 192.168.1.100:bcm96856.dtb ...
cpu_tx_ring_init: TX ring initialized. PD ring at 0000000082c40780
Finished loading 4264 bytes
*** command status = 0
CFE> loadb n 0x03000000 192.168.1.100:u-boot.bin
Loading 192.168.1.100:u-boot.bin ...
Finished loading 395232 bytes
load 395232 bytes binary at 0x3000000 successfully.
*** command status = 0
CFE> go 0x03000000
/memory = 0x40000000 bytes @ 0x0
WARNING: Node's property /reserved-memory/dt_reserved_rdp1 is not defined
WARNING: Node's property /reserved-memory/dt_reserved_rdp2 is not defined
WARNING: Node's property /reserved-memory/dt_reserved_dhd0 is not defined
WARNING: Node's property /reserved-memory/dt_reserved_dhd1 is not defined
dtb_get_cpu_rel_addr failed to get the property
Setting ROOTFS: root=
Appending CFE version to dtb, ret:0
Appending NVRAM to dtb, ret:0
U-Boot 2024.10-rc4-g14459d5bc1e6-dirty (Nov 09 2024 - 01:29:05 +0400) Broadcom BCM6856
Model: Broadcom BCM96856 Reference Board
DRAM: 128 MiB
Core: 12 devices, 7 uclasses, devicetree: embed
MMC:
Loading Environment from nowhere... OK
In: serial@640
Out: serial@640
Err: serial@640
Model: Broadcom BCM96856 Reference Board
Net: No ethernet found.
=> clear
Unknown command 'clear' - try 'help'
=>
EDIT: No need for dtb loading
Indeed, the BCM6856 is another SoC in the BCMBCA family, as can be seen from David Regans recent patch series trying to pull all of the divergent NAND drivers together in U-Boot:
https://lore.kernel.org/u-boot/20241106210348.218507-1-dregan@broadcom.com/
The BCM9xxxx are names for reference design boards, so BCM96846 is the primary reference design for the BCM6846 chip and BCM96856 is the reference design for the BCM6856 chip.