@Plonk34 Sorry for this delay.
First of all I have to say, that all this devmem calls just a configuring for internal Ethernet switch MAC_5 port. Basing on previous investigation, there is a description of this setup https://github.com/Quallenauge/ralink_inic/blob/feature/lede_integration/Readme . It sets port 5 of internal switch to RGMII mode with clock 125MHz, 1G full duplex connected to external PHY wth addr 5 on mdio bus. Physically it connected to rt3883 with fake mdio address. Currently x200 ethernet driver support all this settings out of the box with fixed link phy specified as phy. Only one thing didn't exist in the driver - setting PCDU_5. We can find description for this register in original sources here https://github.com/uwehermann/easybox-904-xdsl-firmware/blob/master/linux/linux-2.6.32.32/include/switch_api/ifxmips_sw_reg.h
As we can see this register is responsible for Clock Delay settings. This means, that we have to add additional delay parameters to device tree and handle them in the driver.
May be this description is little bit muddied, please, do not hesitate and ask for more detailed description.
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