Setup MT7621 & MT7530 to connect external PHY on RGMII

[Alehanter337]

Hey!
I need to link a board with a 10BaseT1L chip and a board with an MT7621 processor.
They are connected via RGMII, I was able to achieve initialization of the chip in the Linux kernel, however, there is no communication between two such devices (a bunch of 10BEYST1L and MT7621).
10BEYST1L chip is soldered on register 7.
Here are my DTS on the router and DTSI on the processor.

There is also an error: MT7621 send RX_CLK on half-amplitude and no TX at all.

Here is debug info when kernel booting

[    3.654336] mt7530 mdio-bus:1f: MT7530 adapts as multi-chip module
[    3.660868] mt7530 mdio-bus:1f: port not matched with tagging CPU port
[    3.685936] mt7530 mdio-bus:1f: no interrupt support
[    3.698186] mt7530 mdio-bus:1f lan0 (uninitialized): PHY [mt7530-0:00] driver [MediaTek MT7530 PHY] (irq=POLL)
[    3.711156] mt7530 mdio-bus:1f lan3 (uninitialized): PHY [mt7530-0:01] driver [MediaTek MT7530 PHY] (irq=POLL)
[    3.723882] mt7530 mdio-bus:1f lan2 (uninitialized): PHY [mt7530-0:02] driver [MediaTek MT7530 PHY] (irq=POLL)
[    3.736674] mt7530 mdio-bus:1f lan1 (uninitialized): PHY [mt7530-0:03] driver [MediaTek MT7530 PHY] (irq=POLL)
[    3.749427] mt7530 mdio-bus:1f wan (uninitialized): PHY [mt7530-0:04] driver [MediaTek MT7530 PHY] (irq=POLL)
[    3.759383] mtk_soc_eth 1e100000.ethernet wan: error -17 registering interface wan
[    3.768513] mt7530 mdio-bus:1f: configuring for fixed/rgmii link mode

my7621.dtsi

/dts-v1/;

#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/clock/mt7621-clk.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "mediatek,mt7621-soc";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "mips,mips1004Kc";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "mips,mips1004Kc";
			reg = <1>;
		};
	};

	cpuintc: cpuintc {
		#address-cells = <0>;
		#interrupt-cells = <1>;
		interrupt-controller;
		compatible = "mti,cpu-interrupt-controller";
	};

	aliases {
		serial0 = &uartlite;
	};

	chosen {
		bootargs = "console=ttyS0,57600";
	};

	pll: pll {
		compatible = "mediatek,mt7621-pll", "syscon";

		#clock-cells = <1>;
		clock-output-names = "cpu", "bus";
	};

	sysclock: sysclock {
		#clock-cells = <0>;
		compatible = "fixed-clock";

		/* FIXME: there should be way to detect this */
		clock-frequency = <50000000>;
	};

	palmbus: palmbus@1E000000 {
		compatible = "palmbus";
		reg = <0x1E000000 0x100000>;
		ranges = <0x0 0x1E000000 0x0FFFFF>;

		#address-cells = <1>;
		#size-cells = <1>;

		sysc: sysc@0 {
			compatible = "mtk,mt7621-sysc";
			reg = <0x0 0x100>;
		};

		wdt: wdt@100 {
			compatible = "mediatek,mt7621-wdt";
			reg = <0x100 0x100>;
		};

		gpio: gpio@600 {
			#gpio-cells = <2>;
			#interrupt-cells = <2>;
			compatible = "mediatek,mt7621-gpio";
			gpio-controller;
			interrupt-controller;
			reg = <0x600 0x100>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
		};

		i2c: i2c@900 {
			compatible = "mediatek,mt7621-i2c";
			reg = <0x900 0x100>;

			clocks = <&sysclock>;

			resets = <&rstctrl 16>;
			reset-names = "i2c";

			#address-cells = <1>;
			#size-cells = <0>;

			status = "disabled";

			pinctrl-names = "default";
			pinctrl-0 = <&i2c_pins>;
		};

		i2s: i2s@a00 {
			compatible = "mediatek,mt7621-i2s";
			reg = <0xa00 0x100>;

			clocks = <&sysclock>;

			resets = <&rstctrl 17>;
			reset-names = "i2s";

			interrupt-parent = <&gic>;
			interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;

			txdma-req = <2>;
			rxdma-req = <3>;

			dmas = <&gdma 4>,
				<&gdma 6>;
			dma-names = "tx", "rx";

			status = "disabled";
		};

		systick: systick@500 {
			compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
			reg = <0x500 0x10>;

			resets = <&rstctrl 28>;
			reset-names = "intc";

			interrupt-parent = <&gic>;
			interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
		};

		memc: memc@5000 {
			compatible = "mtk,mt7621-memc";
			reg = <0x5000 0x1000>;
		};

		cpc: cpc@1fbf0000 {
			compatible = "mtk,mt7621-cpc";
			reg = <0x1fbf0000 0x8000>;
		};

		mc: mc@1fbf8000 {
			compatible = "mtk,mt7621-mc";
			reg = <0x1fbf8000 0x8000>;
		};

		uartlite: uartlite@c00 {
			compatible = "ns16550a";
			reg = <0xc00 0x100>;

			clock-frequency = <50000000>;

			interrupt-parent = <&gic>;
			interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;

			reg-shift = <2>;
			reg-io-width = <4>;
			no-loopback-test;
		};

		uartlite2: uartlite2@d00 {
			compatible = "ns16550a";
			reg = <0xd00 0x100>;

			clock-frequency = <50000000>;

			interrupt-parent = <&gic>;
			interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;

			reg-shift = <2>;
			reg-io-width = <4>;

			pinctrl-names = "default";
			pinctrl-0 = <&uart2_pins>;

			status = "disabled";
		};

		uartlite3: uartlite3@e00 {
			compatible = "ns16550a";
			reg = <0xe00 0x100>;

			clock-frequency = <50000000>;

			interrupt-parent = <&gic>;
			interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;

			reg-shift = <2>;
			reg-io-width = <4>;

			pinctrl-names = "default";
			pinctrl-0 = <&uart3_pins>;

			status = "disabled";
		};

		spi0: spi@b00 {
			status = "disabled";

			compatible = "ralink,mt7621-spi";
			reg = <0xb00 0x100>;

			clocks = <&pll MT7621_CLK_BUS>;

			resets = <&rstctrl 18>;
			reset-names = "spi";

			#address-cells = <1>;
			#size-cells = <0>;

			pinctrl-names = "default";
			pinctrl-0 = <&spi_pins>;
		};

		gdma: gdma@2800 {
			compatible = "ralink,rt3883-gdma";
			reg = <0x2800 0x800>;

			resets = <&rstctrl 14>;
			reset-names = "dma";

			interrupt-parent = <&gic>;
			interrupts = <0 13 4>;

			#dma-cells = <1>;
			#dma-channels = <16>;
			#dma-requests = <16>;

			status = "disabled";
		};

		hsdma: hsdma@7000 {
			compatible = "mediatek,mt7621-hsdma";
			reg = <0x7000 0x1000>;

			resets = <&rstctrl 5>;
			reset-names = "hsdma";

			interrupt-parent = <&gic>;
			interrupts = <0 11 4>;

			#dma-cells = <1>;
			#dma-channels = <1>;
			#dma-requests = <1>;

			status = "disabled";
		};
	};

	pinctrl: pinctrl {
		compatible = "ralink,rt2880-pinmux";
		pinctrl-names = "default";
		pinctrl-0 = <&state_default>;

		state_default: pinctrl0 {
		};

		i2c_pins: i2c_pins {
			i2c_pins {
				groups = "i2c";
				function = "i2c";
			};
		};

		spi_pins: spi_pins {
			spi_pins {
				groups = "spi";
				function = "spi";
			};
		};

		uart1_pins: uart1 {
			uart1 {
				groups = "uart1";
				function = "uart1";
			};
		};

		uart2_pins: uart2 {
			uart2 {
				groups = "uart2";
				function = "uart2";
			};
		};

		uart3_pins: uart3 {
			uart3 {
				groups = "uart3";
				function = "uart3";
			};
		};

		rgmii1_pins: rgmii1 {
			rgmii1 {
				groups = "rgmii1";
				function = "rgmii1";
			};
		};

		rgmii2_pins: rgmii2 {
			rgmii2 {
				groups = "rgmii2";
				function = "rgmii2";
			};
		};

		mdio_pins: mdio {
			mdio {
				groups = "mdio";
				function = "mdio";
			};
		};

		pcie_pins: pcie {
			pcie {
				groups = "pcie";
				function = "gpio";
			};
		};

		nand_pins: nand {
			spi-nand {
				groups = "spi";
				function = "nand1";
			};

			sdhci-nand {
				groups = "sdhci";
				function = "nand2";
			};
		};

		sdhci_pins: sdhci {
			sdhci {
				groups = "sdhci";
				function = "sdhci";
			};
		};
	};

	rstctrl: rstctrl {
		compatible = "ralink,rt2880-reset";
		#reset-cells = <1>;
	};

	clkctrl: clkctrl {
		compatible = "ralink,rt2880-clock";
		#clock-cells = <1>;
	};

	sdhci: sdhci@1E130000 {
		status = "disabled";

		compatible = "ralink,mt7620-sdhci";
		reg = <0x1E130000 0x4000>;

		interrupt-parent = <&gic>;
		interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;

		pinctrl-names = "default";
		pinctrl-0 = <&sdhci_pins>;
	};

	xhci: xhci@1E1C0000 {
		#address-cells = <1>;
		#size-cells = <0>;

		compatible = "mediatek,mt8173-xhci";
		reg = <0x1e1c0000 0x1000
		       0x1e1d0700 0x0100>;
		reg-names = "mac", "ippc";

		clocks = <&sysclock>;
		clock-names = "sys_ck";

		interrupt-parent = <&gic>;
		interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;

		/*
		 * Port 1 of both hubs is one usb slot and referenced here.
		 * The binding doesn't allow to address individual hubs.
		 * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
		 */
		xhci_ehci_port1: port@1 {
			reg = <1>;
			#trigger-source-cells = <0>;
		};

		/*
		 * Only the second usb hub has a second port. That port serves
		 * ehci and ohci.
		 */
		ehci_port2: port@2 {
			reg = <2>;
			#trigger-source-cells = <0>;
		};
	};

	gic: interrupt-controller@1fbc0000 {
		compatible = "mti,gic";
		reg = <0x1fbc0000 0x2000>;

		interrupt-controller;
		#interrupt-cells = <3>;

		mti,reserved-cpu-vectors = <7>;

		timer {
			compatible = "mti,gic-timer";
			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
			clocks = <&pll MT7621_CLK_CPU>;
		};
	};

	nficlock: nficlock {
		#clock-cells = <0>;
		compatible = "fixed-clock";

		clock-frequency = <125000000>;
	};

	nand: nand@1e003000 {
		status = "disabled";

		compatible = "mediatek,mt7621-nfc";
		reg = <0x1e003000 0x800
			0x1e003800 0x800>;
		reg-names = "nfi", "ecc";

		clocks = <&nficlock>;
		clock-names = "nfi_clk";
	};

	ethsys: syscon@1e000000 {
		compatible = "mediatek,mt7621-ethsys",
			     "syscon";
		reg = <0x1e000000 0x1000>;
		#clock-cells = <1>;
	};

	ethernet: ethernet@1e100000 {
		compatible = "mediatek,mt7621-eth";
		reg = <0x1e100000 0x10000>;

		clocks = <&sysclock>;
		clock-names = "ethif";

		#address-cells = <1>;
		#size-cells = <0>;

		resets = <&rstctrl 6 &rstctrl 23>;
		reset-names = "fe", "eth";

		interrupt-parent = <&gic>;
		interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;

		mediatek,ethsys = <&ethsys>;

		gmac0: mac@0 {
			compatible = "mediatek,eth-mac";
			reg = <0>;
			phy-mode = "rgmii";

			fixed-link {
				speed = <1000>;
				full-duplex;
				pause;
			};
		};


		gmac1: mac@1 {
			compatible = "mediatek,eth-mac";
			reg = <1>;
			phy-mode = "rgmii-txid";
			//phy-handle = <&ephy5>;
		};


		mdio: mdio-bus {
			#address-cells = <1>;
			#size-cells = <0>;
			/*
			ephy5: ethernet-phy@7 {
				reg = <7>;
			};	
			*/
			switch0: switch@1f {
				compatible = "mediatek,mt7621";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x1f>;
				mediatek,mcm;
				resets = <&rstctrl 2>;
				reset-names = "mcm";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					port@0 {
						status = "okay";
						reg = <0>;
						label = "lan0";
					};

					port@1 {
						status = "okay";
						reg = <1>;
						label = "lan1";
					};

					port@2 {
						status = "okay";
						reg = <2>;
						label = "lan2";
					};

					port@3 {
						status = "okay";
						reg = <3>;
						label = "lan3";
					};

					port@4 {
						status = "okay";
						reg = <4>;
						label = "lan4";
					};
					
					port@5 {
						reg = <5>;
						label = "adin1100";
						phy-mode = "rgmii";
						ethernet = <&gmac1>;	
						//phy-handle = <&ephy5>;
					};
					

					port@6 {
						reg = <6>;
						label = "cpu";
						ethernet = <&gmac0>;
						phy-mode = "rgmii";

						fixed-link {
							speed = <1000>;
							full-duplex;
							pause;
						};
					};
				};
			};
		};
	};

	gsw: gsw@1e110000 {
		compatible = "mediatek,mt7621-gsw";
		reg = <0x1e110000 0x8000>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
	};

	pcie: pcie@1e140000 {
		compatible = "mediatek,mt7621-pci";
		reg = <0x1e140000 0x100     /* host-pci bridge registers */
			0x1e142000 0x100    /* pcie port 0 RC control registers */
			0x1e143000 0x100    /* pcie port 1 RC control registers */
			0x1e144000 0x100>;  /* pcie port 2 RC control registers */
		#address-cells = <3>;
		#size-cells = <2>;

		pinctrl-names = "default";
		pinctrl-0 = <&pcie_pins>;

		device_type = "pci";

		bus-range = <0 255>;
		ranges = <
			0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
			0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
		>;

		interrupt-parent = <&gic>;
		interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
				GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
				GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;

		status = "disabled";

		resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
		reset-names = "pcie0", "pcie1", "pcie2";
		clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
		clock-names = "pcie0", "pcie1", "pcie2";
		phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
		phy-names = "pcie-phy0", "pcie-phy2";

		reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;

		pcie0: pcie@0,0 {
			reg = <0x0000 0 0 0 0>;
			#address-cells = <3>;
			#size-cells = <2>;
			ranges;
			bus-range = <0x00 0xff>;
		};

		pcie1: pcie@1,0 {
			reg = <0x0800 0 0 0 0>;
			#address-cells = <3>;
			#size-cells = <2>;
			ranges;
			bus-range = <0x00 0xff>;
		};

		pcie2: pcie@2,0 {
			reg = <0x1000 0 0 0 0>;
			#address-cells = <3>;
			#size-cells = <2>;
			ranges;
			bus-range = <0x00 0xff>;
		};
	};

	pcie0_phy: pcie-phy@1e149000 {
		compatible = "mediatek,mt7621-pci-phy";
		reg = <0x1e149000 0x0700>;
		#phy-cells = <1>;
	};

	pcie2_phy: pcie-phy@1e14a000 {
		compatible = "mediatek,mt7621-pci-phy";
		reg = <0x1e14a000 0x0700>;
		#phy-cells = <1>;
	};
};

mt7621_xiaomi_mi-router-3-pro.dts

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

#include "mt7621.dtsi"

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	compatible = "xiaomi,mi-router-3-pro", "mediatek,mt7621-soc";
	model = "Xiaomi Mi Router 3 Pro";

	aliases {
		led-boot = &led_status_yellow;
		led-failsafe = &led_status_red;
		led-running = &led_status_blue;
		led-upgrade = &led_status_yellow;
		label-mac-device = &gmac0;
	};

	chosen {
		bootargs = "console=ttyS0,115200n8";
	};

	leds {
		compatible = "gpio-leds";

		led_status_red: status_red {
			label = "red:status";
			gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
		};

		led_status_blue: status_blue {
			label = "blue:status";
			gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
		};

		led_status_yellow: status_yellow {
			label = "yellow:status";
			gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
		};

		wan_amber {
			label = "amber:wan";
			gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "dsa-0.0:04:1Gbps";
		};

		lan3_amber {
			label = "amber:lan3";
			gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "dsa-0.0:03:1Gbps";
		};

		lan2_amber {
			label = "amber:lan2";
			gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "dsa-0.0:02:1Gbps";
		};

		lan1_amber {
			label = "amber:lan1";
			gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "dsa-0.0:01:1Gbps";
		};
	};

	keys {
		compatible = "gpio-keys";

		reset {
			label = "reset";
			gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RESTART>;
		};
	};

	reg_usb_vbus: regulator {
		compatible = "regulator-fixed";
		regulator-name = "usb_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio 12 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};
};

&xhci {
	vbus-supply = <&reg_usb_vbus>;
};

&nand {
	status = "okay";

	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;

		partition@0 {
			label = "Bootloader";
			reg = <0x0 0x40000>;
			read-only;
		};

		partition@40000 {
			label = "Config";
			reg = <0x40000 0x40000>;
		};

		partition@80000 {
			label = "Bdata";
			reg = <0x80000 0x40000>;
			read-only;
		};

		factory: partition@c0000 {
			label = "factory";
			reg = <0x0c0000 0x40000>;
			read-only;
		};

		partition@100000 {
			label = "crash";
			reg = <0x100000 0x40000>;
		};

		partition@140000 {
			label = "crash_syslog";
			reg = <0x140000 0x80000>;
		};

		partition@1c0000 {
			label = "reserved0";
			reg = <0x1c0000 0x40000>;
			read-only;
		};

		/* We keep stock xiaomi firmware (kernel0) here */
		partition@200000 {
			label = "kernel_stock";
			reg = <0x200000 0x400000>;
		};

		partition@600000 {
			label = "kernel";
			reg = <0x600000 0x400000>;
		};

		partition@a00000 {
			label = "ubi";
			reg = <0xa00000 0xf580000>;
		};
	};
};

&pcie {
	status = "okay";
};

&pcie0 {
	wifi@0,0 {
		compatible = "mediatek,mt76";
		reg = <0x0000 0 0 0 0>;
		mediatek,mtd-eeprom = <&factory 0x0000>;
		ieee80211-freq-limit = <2400000 2500000>;
	};
};

&pcie1 {
	wifi@0,0 {
		compatible = "mediatek,mt76";
		reg = <0x0000 0 0 0 0>;
		mediatek,mtd-eeprom = <&factory 0x8000>;
		ieee80211-freq-limit = <5000000 6000000>;
	};
};

&gmac0 {
	nvmem-cells = <&macaddr_factory_e006>;
	nvmem-cell-names = "mac-address";
};

&gmac1 {
	status = "okay";
	label = "wan";
	phy-handle = <&ephy5>;
	nvmem-cells = <&macaddr_factory_e000>;
	nvmem-cell-names = "mac-address";
};

&mdio {
	ephy5: ethernet-phy@7 {
		reg = <7>;
	};
};

&switch0 {
	ports {
		port@1 {
			status = "okay";
			label = "lan3";
		};

		port@2 {
			status = "okay";
			label = "lan2";
		};

		port@3 {
			status = "okay";
			label = "lan1";
		};
		
		port@4 {
			status = "okay";
			label = "wan";
		};
		
		port@5 {
			status = "okay";
			label = "adin1100";
		};
	};
};

&state_default {
	gpio {
		groups = "jtag", "uart2", "uart3", "wdt";
		function = "gpio";
	};
};

&factory {
	compatible = "nvmem-cells";
	#address-cells = <1>;
	#size-cells = <1>;

	macaddr_factory_e000: macaddr@e000 {
		reg = <0xe000 0x6>;
	};

	macaddr_factory_e006: macaddr@e006 {
		reg = <0xe006 0x6>;
	};
};```

[123serge123]

Did you try example 3 from Documentation/devicetree/bindings/net/dsa/mt7530.txt?:

&eth {
	gmac0: mac@0 {
		compatible = "mediatek,eth-mac";
		reg = <0>;
		phy-mode = "rgmii";

		fixed-link {
			speed = <1000>;
			full-duplex;
			pause;
		};
	};

	mdio: mdio-bus {
		#address-cells = <1>;
		#size-cells = <0>;

		/* External phy */
		ephy5: ethernet-phy@7 {
			reg = <7>;
		};

		mt7530: switch@1f {
			compatible = "mediatek,mt7621";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x1f>;
			pinctrl-names = "default";
			mediatek,mcm;

			resets = <&rstctrl 2>;
			reset-names = "mcm";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					label = "lan0";
				};

				port@1 {
					reg = <1>;
					label = "lan1";
				};

				port@2 {
					reg = <2>;
					label = "lan2";
				};

				port@3 {
					reg = <3>;
					label = "lan3";
				};

				port@4 {
					reg = <4>;
					label = "lan4";
				};

				port@5 {
					reg = <5>;
					label = "lan5";
					phy-mode = "rgmii";
					phy-handle = <&ephy5>;
				};

				cpu_port0: port@6 {
					reg = <6>;
					label = "cpu";
					ethernet = <&gmac0>;
					phy-mode = "rgmii";

					fixed-link {
						speed = <1000>;
						full-duplex;
						pause;
					};
				};
			};
		};
	};
};

[Alehanter337]

Yes. Don't work. Now watch a gpio pins, think that outs of RX and TX are swapped on board.

[123serge123]

@Alehanter337

Don't work.

It's less than nothing
port@5 can't connect to 10BaseT1L chip?
Which phy driver do you use? Generci PHY driver may work incorrectly with unsupported phy device. At least fail to set rgmii/rgmii-txid/rgmii-rxid modes. In this case no traffic between port@5 and 10BaseT1L chip but ethtool can read/write data to phy device.

[Alehanter337]

Chip called ADIN1100. Using linux 5.4 with integrated driver of ADIN1100. PHYAD of chip is 7.Ethtool read data from port@5.
Driver is probing and working, ifconfig show interface of chip, link led diode is blinking when i connect 2 boards, but RX packets have no increment

[123serge123]

It's very possible that there isn't rgmii synchronization. Good article about RGMII timing.
For tuning synchro one or both side of connection (MAC and PHY) must support configuring internal delays.
To tune PHY-to-MAC direction with rx internal delay:

		port@5 {
					reg = <5>;
					label = "lan5";
					phy-mode = "rgmii-rxid";
					phy-handle = <&ephy5>;
				};

OR (exclusive!!!) tx internal delay at PHY side:

		ephy5: ethernet-phy@7 {
			phy-mode = "rgmii-txid";
			adi,tx-internal-delay-ps = <2>;
			reg = <7>;
		};

The same for MAC-to-PHY direction.
MAC tx internal delay:

	port@5 {
					reg = <5>;
					label = "lan5";
					phy-mode = "rgmii-txid";
					phy-handle = <&ephy5>;
				};

or PHY rx internal delay:

		ephy5: ethernet-phy@7 {
			phy-mode = "rgmii-rxid";
			adi,rx-internal-delay-ps = <2>;
			reg = <7>;
		};

Only one side of connection need insert delay.
But if another side don't support tuning or you are unsure that it work correctly than delay setting may be made at one side.
For example:
delay tuning only at PHY side

	ephy5: ethernet-phy@7 {
			phy-mode = "rgmii-id";
			adi,rx-internal-delay-ps = <2>;
			adi,tx-internal-delay-ps = <2>;
			reg = <7>;
		};

and stay phy-mode = "rgmii"; of MAC side untouched.
And vice versus
Only set rgmii mode for PHY:

ephy5: ethernet-phy@7 {
			phy-mode = "rgmii";
			reg = <7>;
		};

and set correct delays for MAC by changing phy-mode to rgmii-rxid/rgmii-txid/rgmii-id for rx/tx/both rx and tx delays.
BTW did you set phy-mode = "rgmii"; of your PHY explicitly (no delays configuration)?