Requesting OpenWrt support for HiLink RM65

Axkman · October 19, 2024, 2:54pm

Producer: https://www.hlktech.com/en/Goods-230.html
RM65 router development kits (with antenna's, heatsink, powerplug etc) offered on aliexpress for around 68 euros.

Pictures:

Uart:
On the side of the board are TX,RX,GND pins. Don't have to solder.
Baudrate: 115200 8n1

Specifications:

SoC: MediaTek MT7981B 2x Cortex-A53 running at 1,3GHz
Flash: 128MB Macronix SPI NAND
RAM: 256MB DDR3
Switch: MediaTek MT7531AE
Ethernet: 5x 100/1000 Mbps from switch + 1x 100/1000 Mbps from soc (wan).
WiFi: MediaTek MT7976C 2x2 2.4GHz 3x3 5GHz
Antenna: 2x 2.4 GHz, 3x 5GHz
Leds: Power (red), wifi2g (blue) wifi5g (blue), gbewantx (yellow), gbewanrx yellow, lan 1-5 (yellow)
Button: Reset, WPS
Power: DC 12V 1A +- 5 watt power consumption

DTS file mt7981b-rm65.dts:

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2022 MediaTek Inc.
 * Author: Sam.Shih <sam.shih@mediatek.com>
 */

/dts-v1/;
#include "mt7981b-rm65.dtsi"

/ {
	model = "Hilink RM65";
	compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory {    /* 256MB ram = 0x10000000 */
		reg = <0 0x40000000 0 0x10000000>;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	reg_5v: regulator-5v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-5V";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-boot-on;
		regulator-always-on;
	};

	gpio-keys {
		compatible = "gpio-keys";
		reset {
			label = "reset";
			linux,code = <KEY_RESTART>;
			gpios = <&pio 1 GPIO_ACTIVE_LOW>;
		};
		wps {
			label = "wps";
			linux,code = <KEY_WPS_BUTTON>;
			gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
		};
	};
	
	leds {
		compatible = "gpio-leds";
			gbe_led0 {
				label = "gbe0";
				gpios = <&pio 8 GPIO_ACTIVE_LOW>;
			};

			gbe_led1 {
				label = "gbe1";
				gpios = <&pio 13 GPIO_ACTIVE_LOW>;
			};
			
			wf2g_led {
				label = "wf2g1";
				gpios = <&pio 34 GPIO_ACTIVE_LOW>;
			};
			
			wf5g_led {
				label = "wf5g1";
				gpios = <&pio 35 GPIO_ACTIVE_LOW>;
			};
	};
};

&eth {
        status = "okay";
 
 	gmac0: mac@0 {
		compatible = "mediatek,eth-mac";
		reg = <0>;
		phy-mode = "2500base-x";

		fixed-link {
			speed = <2500>;
			full-duplex;
			pause;
		};
	};

	gmac1: mac@1 {
		compatible = "mediatek,eth-mac";
		reg = <1>;
		phy-mode = "gmii";
		phy-handle = <&phy0>;
	};
};

&mdio_bus {

	phy0: ethernet-phy@0 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <0>;
		phy-mode = "gmii";
		phy-is-integrated;
		nvmem-cells = <&phy_calibration>;
		nvmem-cell-names = "phy-cal-data";
	};

	switch: switch@1f {
		compatible = "mediatek,mt7531";
		reg = <31>;
		interrupt-controller;
		#interrupt-cells = <1>;
		interrupt-parent = <&pio>;
		interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
		reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
	};
};

&switch {
	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			reg = <0>;
			label = "lan1";
		};

		port@1 {
			reg = <1>;
			label = "lan2";
		};

		port@2 {
			reg = <2>;
			label = "lan3";
		};

		port@3 {
			reg = <3>;
			label = "lan4";
		};

		port@4 {
			reg = <4>;
			label = "lan5";
		};

/*		sw_p5: port@5 {      in mt7981-rfb.dts
			reg = <5>;
			label = "lan5";
			status = "disabled";
		};
*/
		port@6 {
			reg = <6>;
			label = "cpu";
			ethernet = <&gmac0>;
			phy-mode = "2500base-x";

			fixed-link {
				speed = <2500>;
				full-duplex;
				pause;
			};
		};
	};
};

&crypto {
	status = "okay";
};

&pio {
	spi0_flash_pins: spi0-pins {
		mux {
			function = "spi";
			groups = "spi0", "spi0_wp_hold";
		};
		conf-pu {
			pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
			drive-strength = <MTK_DRIVE_8mA>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
		};
		conf-pd {
			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
			drive-strength = <MTK_DRIVE_8mA>;
			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
		};
	};

};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_flash_pins>;
	cs-gpios = <0>, <0>;		/* weet niet of deze regel nodig is */
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";
	
	spi_nand: spi_nand@0 {
		#address-cells = <1>;
	/*	compatible = "ethernet-phy-id03a2.9461";	*/
	/*	compatible = "ethernet-phy-id67c9.de0a";	*/
	/* 1gb	compatible = "ethernet-phy-ieee802.3-c22";	*/
	/* 2.5gb compatible = "ethernet-phy-ieee802.3-c45";	*/

		#size-cells = <1>;
		compatible = "spi-nand";
		reg = <1>;
		spi-max-frequency = <10000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "BL2";
				reg = <0x00000 0x0100000>;
				read-only;
			};

			partition@100000 {
				label = "u-boot-env";
				reg = <0x0100000 0x0080000>;
			};

			factory: partition@180000 {
				label = "Factory";
				reg = <0x180000 0x0200000>;
			};

			partition@380000 {
				label = "FIP";
				reg = <0x380000 0x0200000>;
			};

			partition@580000 {
				label = "ubi";
				reg = <0x580000 0x4000000>;
			};
		};
	};
};

&xhci {
	vusb33-supply = <&reg_3p3v>;
	vbus-supply = <&reg_5v>;
	status = "okay";
};

&wifi {
	status = "okay";

	mediatek,mtd-eeprom = <&factory 0x0>;
};

&uart0 {
	status = "okay";
};

&usb_phy {
	status = "okay";
};

&watchdog {type or paste code here
	status = "okay";
};

DTSI file mkt7981b-rm65.dtsi:

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (c) 2020 MediaTek Inc.
 * Author: Sam.Shih <sam.shih@mediatek.com>
 * Author: Jianhui Zhao <zhaojh329@gmail.com>
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/clock/mediatek,mt7981-clk.h>
#include <dt-bindings/reset/mt7986-resets.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mux/mux.h>

/ {
/*	compatible = "mediatek,mt7981";		*/
/* disabled above line otherwise compiling kept complaining about a lot of other dts files  */

	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x1>;
		};
	};

	pwm: pwm@10048000 {
		compatible = "mediatek,mt7981-pwm";
		reg = <0 0x10048000 0 0x1000>;
		#pwm-cells = <2>;
		clocks = <&infracfg CLK_INFRA_PWM_STA>,
			 <&infracfg CLK_INFRA_PWM_HCK>,
			 <&infracfg CLK_INFRA_PWM1_CK>,
			 <&infracfg CLK_INFRA_PWM2_CK>,
			 <&infracfg CLK_INFRA_PWM3_CK>;
		clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
	};

	fan: pwm-fan {
		compatible = "pwm-fan";
		/* cooling level (0, 1, 2, 3, 4, 5, 6, 7) : (0%/25%/37.5%/50%/62.5%/75%/87.5%/100% duty) */
		cooling-levels = <0 63 95 127 159 191 223 255>;
		#cooling-cells = <2>;
		status = "disabled";
	};

	thermal-zones {
		cpu_thermal: cpu-thermal {
			polling-delay-passive = <1000>;
			polling-delay = <1000>;
			thermal-sensors = <&thermal 0>;
			trips {
				cpu_trip_active_highest: active-highest {
					temperature = <70000>;
					hysteresis = <2000>;
					type = "active";
				};

				cpu_trip_active_high: active-high {
					temperature = <60000>;
					hysteresis = <2000>;
					type = "active";
				};

				cpu_trip_active_med: active-med {
					temperature = <50000>;
					hysteresis = <2000>;
					type = "active";
				};

				cpu_trip_active_low: active-low {
					temperature = <45000>;
					hysteresis = <2000>;
					type = "active";
				};

				cpu_trip_active_lowest: active-lowest {
					temperature = <40000>;
					hysteresis = <2000>;
					type = "active";
				};
			};

			cooling-maps {
				cpu-active-highest {
					/* active: set fan to cooling level 7 */
					cooling-device = <&fan 7 7>;
					trip = <&cpu_trip_active_highest>;
				};

				cpu-active-high {
					/* active: set fan to cooling level 5 */
					cooling-device = <&fan 5 5>;
					trip = <&cpu_trip_active_high>;
				};

				cpu-active-med {
					/* active: set fan to cooling level 3 */
					cooling-device = <&fan 3 3>;
					trip = <&cpu_trip_active_med>;
				};

				cpu-active-low {
					/* active: set fan to cooling level 2 */
					cooling-device = <&fan 2 2>;
					trip = <&cpu_trip_active_low>;
				};

				cpu-active-lowest {
					/* active: set fan to cooling level 1 */
					cooling-device = <&fan 1 1>;
					trip = <&cpu_trip_active_lowest>;
				};
			};
		};
	};

	thermal: thermal@1100c800 {
		#thermal-sensor-cells = <1>;
		compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
		reg = <0 0x1100c800 0 0x800>;
		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg CLK_INFRA_THERM_CK>,
			 <&infracfg CLK_INFRA_ADC_26M_CK>;
		clock-names = "therm", "auxadc";
		mediatek,auxadc = <&auxadc>;
		mediatek,apmixedsys = <&apmixedsys>;
		nvmem-cells = <&thermal_calibration>;
		nvmem-cell-names = "calibration-data";
	};

	auxadc: adc@1100d000 {
		compatible = "mediatek,mt7981-auxadc",
			     "mediatek,mt7986-auxadc",
			     "mediatek,mt7622-auxadc";
		reg = <0 0x1100d000 0 0x1000>;
		clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
			 <&infracfg CLK_INFRA_ADC_FRC_CK>;
		clock-names = "main", "32k";
		#io-channel-cells = <1>;
	};

	wdma: wdma@15104800 {
		compatible = "mediatek,wed-wdma";
		reg = <0 0x15104800 0 0x400>,
		      <0 0x15104c00 0 0x400>;
	};

	ap2woccif: ap2woccif@151a5000 {
		compatible = "mediatek,ap2woccif";
		reg = <0 0x151a5000 0 0x1000>,
		      <0 0x151ad000 0 0x1000>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* 64 KiB reserved for ramoops/pstore */
		ramoops@42ff0000 {
			compatible = "ramoops";
			reg = <0 0x42ff0000 0 0x10000>;
			record-size = <0x1000>;
		};

		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
		secmon_reserved: secmon@43000000 {
			reg = <0 0x43000000 0 0x30000>;
			no-map;
		};

		wmcpu_emi: wmcpu-reserved@47c80000 {
			reg = <0 0x47c80000 0 0x100000>;
			no-map;
		};

		wo_emi0: wo-emi@47d80000 {
			reg = <0 0x47d80000 0 0x40000>;
			no-map;
		};

		wo_data: wo-data@47dc0000 {
			reg = <0 0x47dc0000 0 0x240000>;
			no-map;
		};
	};

	psci {
		compatible  = "arm,psci-0.2";
		method      = "smc";
	};

	trng {
		compatible = "mediatek,mt7981-rng";
	};

	clk40m: oscillator@0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <40000000>;
		clock-output-names = "clkxtal";
	};

	infracfg: infracfg@10001000 {
		compatible = "mediatek,mt7981-infracfg", "syscon";
		reg = <0 0x10001000 0 0x1000>;
		#clock-cells = <1>;
	};

	topckgen: topckgen@1001B000 {
		compatible = "mediatek,mt7981-topckgen", "syscon";
		reg = <0 0x1001B000 0 0x1000>;
		#clock-cells = <1>;
	};

	apmixedsys: apmixedsys@1001E000 {
		compatible = "mediatek,mt7981-apmixedsys", "mediatek,mt7986-apmixedsys", "syscon";
		reg = <0 0x1001E000 0 0x1000>;
		#clock-cells = <1>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		clock-frequency = <13000000>;
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;

	};

	watchdog: watchdog@1001c000 {
		compatible = "mediatek,mt7986-wdt",
			     "mediatek,mt6589-wdt";
		reg = <0 0x1001c000 0 0x1000>;
		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
		#reset-cells = <1>;
		status = "disabled";
	};

	gic: interrupt-controller@c000000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		interrupt-controller;
		reg = <0 0x0c000000 0 0x40000>,  /* GICD */
		      <0 0x0c080000 0 0x200000>; /* GICR */

		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	uart0: serial@11002000 {
		compatible = "mediatek,mt6577-uart";
		reg = <0 0x11002000 0 0x400>;
		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg CLK_INFRA_UART0_SEL>,
			<&infracfg CLK_INFRA_UART0_CK>;
		clock-names = "baud", "bus";
		assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
				  <&infracfg CLK_INFRA_UART0_SEL>;
		assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
					 <&topckgen CLK_TOP_UART_SEL>;
		pinctrl-0 = <&uart0_pins>;
		pinctrl-names = "default";
		status = "disabled";
	};

	uart1: serial@11003000 {
		compatible = "mediatek,mt6577-uart";
		reg = <0 0x11003000 0 0x400>;
		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg CLK_INFRA_UART1_SEL>,
			<&infracfg CLK_INFRA_UART1_CK>;
		clock-names = "baud", "bus";
		assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
				  <&infracfg CLK_INFRA_UART1_SEL>;
		assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
					 <&topckgen CLK_TOP_UART_SEL>;
		status = "disabled";
	};

	uart2: serial@11004000 {
		compatible = "mediatek,mt6577-uart";
		reg = <0 0x11004000 0 0x400>;
		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg CLK_INFRA_UART2_SEL>,
			<&infracfg CLK_INFRA_UART2_CK>;
		clock-names = "baud", "bus";
		assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
				  <&infracfg CLK_INFRA_UART2_SEL>;
		assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
					 <&topckgen CLK_TOP_UART_SEL>;
		status = "disabled";
	};

	i2c0: i2c@11007000 {
		compatible = "mediatek,mt7981-i2c";
		reg = <0 0x11007000 0 0x1000>,
		      <0 0x10217080 0 0x80>;
		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
		clock-div = <1>;
		clocks = <&infracfg CLK_INFRA_I2C0_CK>,
			 <&infracfg CLK_INFRA_AP_DMA_CK>,
			 <&infracfg CLK_INFRA_I2C_MCK_CK>,
			 <&infracfg CLK_INFRA_I2C_PCK_CK>;
		clock-names = "main", "dma", "arb", "pmic";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	pcie: pcie@11280000 {
		compatible = "mediatek,mt7981-pcie",
			     "mediatek,mt7986-pcie";
		device_type = "pci";
		reg = <0 0x11280000 0 0x4000>;
		reg-names = "pcie-mac";
		#address-cells = <3>;
		#size-cells = <2>;
		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
		bus-range = <0x00 0xff>;
		ranges = <0x82000000 0 0x20000000
			  0x0 0x20000000 0 0x10000000>;
		status = "disabled";

		clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
			 <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
			 <&infracfg CLK_INFRA_IPCIER_CK>,
			 <&infracfg CLK_INFRA_IPCIEB_CK>;

		phys = <&u3port0 PHY_TYPE_PCIE>;
		phy-names = "pcie-phy";

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie_intc 0>,
				<0 0 0 2 &pcie_intc 1>,
				<0 0 0 3 &pcie_intc 2>,
				<0 0 0 4 &pcie_intc 3>;
		pcie_intc: interrupt-controller {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <1>;
		};
	};

	crypto: crypto@10320000 {
		compatible = "inside-secure,safexcel-eip97";
		reg = <0 0x10320000 0 0x40000>;
		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "ring0", "ring1", "ring2", "ring3";
		clocks = <&topckgen CLK_TOP_EIP97B>;
		clock-names = "top_eip97_ck";
		assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
		assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
	};

	pio: pinctrl@11d00000 {
		compatible = "mediatek,mt7981-pinctrl";
		reg = <0 0x11d00000 0 0x1000>,
		      <0 0x11c00000 0 0x1000>,
		      <0 0x11c10000 0 0x1000>,
		      <0 0x11d20000 0 0x1000>,
		      <0 0x11e00000 0 0x1000>,
		      <0 0x11e20000 0 0x1000>,
		      <0 0x11f00000 0 0x1000>,
		      <0 0x11f10000 0 0x1000>,
		      <0 0x1000b000 0 0x1000>;
		reg-names = "gpio", "iocfg_rt", "iocfg_rm",
			    "iocfg_rb", "iocfg_lb", "iocfg_bl",
			    "iocfg_tm", "iocfg_tl", "eint";
		gpio-controller;
		#gpio-cells = <2>;
		gpio-ranges = <&pio 0 0 56>;
		interrupt-controller;
		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		#interrupt-cells = <2>;

		mdio_pins: mdc-mdio-pins {
			mux {
				function = "eth";
				groups = "smi_mdc_mdio";
			};
		};

		uart0_pins: uart0-pins {
			mux {
				function = "uart";
				groups = "uart0";
			};
		};

		wifi_dbdc_pins: wifi-dbdc-pins {
			mux {
				function = "eth";
				groups = "wf0_mode1";
			};
			conf {
				pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
				       "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
				       "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
				       "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
				       "WF_CBA_RESETB", "WF_DIG_RESETB";
				drive-strength = <4>;
			};
		};
	};

	ethsys: syscon@15000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "mediatek,mt7981-ethsys",
			     "mediatek,mt7986-ethsys",
			     "syscon";
		reg = <0 0x15000000 0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	wed: wed@15010000 {
		compatible = "mediatek,mt7981-wed",
			     "mediatek,mt7986-wed",
			     "syscon";
		reg = <0 0x15010000 0 0x1000>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
		memory-region = <&wo_emi0>, <&wo_data>;
		memory-region-names = "wo-emi", "wo-data";
		mediatek,wo-ccif = <&wo_ccif0>;
		mediatek,wo-ilm = <&wo_ilm0>;
		mediatek,wo-dlm = <&wo_dlm0>;
		mediatek,wo-cpuboot = <&wo_cpuboot>;
	};

	eth: ethernet@15100000 {
		compatible = "mediatek,mt7981-eth";
		reg = <0 0x15100000 0 0x80000>;
		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&ethsys CLK_ETH_FE_EN>,
			<&ethsys CLK_ETH_GP2_EN>,
			<&ethsys CLK_ETH_GP1_EN>,
			<&ethsys CLK_ETH_WOCPU0_EN>,
			<&sgmiisys0 CLK_SGM0_TX_EN>,
			<&sgmiisys0 CLK_SGM0_RX_EN>,
			<&sgmiisys0 CLK_SGM0_CK0_EN>,
			<&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
			<&sgmiisys1 CLK_SGM1_TX_EN>,
			<&sgmiisys1 CLK_SGM1_RX_EN>,
			<&sgmiisys1 CLK_SGM1_CK1_EN>,
			<&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
			<&topckgen CLK_TOP_SGM_REG>,
			<&topckgen CLK_TOP_NETSYS_SEL>,
			<&topckgen CLK_TOP_NETSYS_500M_SEL>;
		clock-names = "fe", "gp2", "gp1", "wocpu0",
					"sgmii_tx250m", "sgmii_rx250m",
					"sgmii_cdr_ref", "sgmii_cdr_fb",
					"sgmii2_tx250m", "sgmii2_rx250m",
					"sgmii2_cdr_ref", "sgmii2_cdr_fb",
					"sgmii_ck", "netsys0", "netsys1";
		assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
				  <&topckgen CLK_TOP_SGM_325M_SEL>;
		assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
					 <&topckgen CLK_TOP_CB_SGM_325M>;
		mediatek,ethsys = <&ethsys>;
		mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
		mediatek,infracfg = <&topmisc>;
		mediatek,wed = <&wed>;
		#reset-cells = <1>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";

		mdio_bus: mdio-bus {
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	wo_dlm0: syscon@151e8000 {
		compatible = "mediatek,mt7986-wo-dlm", "syscon";
		reg = <0 0x151e8000 0 0x2000>;
	};

	wo_ilm0: syscon@151e0000 {
		compatible = "mediatek,mt7986-wo-ilm", "syscon";
		reg = <0 0x151e0000 0 0x8000>;
	};

	wo_cpuboot: syscon@15194000 {
		compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
		reg = <0 0x15194000 0 0x1000>;
	};

	wo_ccif0: syscon@151a5000 {
		compatible = "mediatek,mt7986-wo-ccif", "syscon";
		reg = <0 0x151a5000 0 0x1000>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
	};

	sgmiisys0: syscon@10060000 {
		compatible = "mediatek,mt7981-sgmiisys_0", "mediatek,mt7986-sgmiisys_0", "syscon";
		reg = <0 0x10060000 0 0x1000>;
		mediatek,pnswap;
		#clock-cells = <1>;
	};

	sgmiisys1: syscon@10070000 {
		compatible = "mediatek,mt7981-sgmiisys_1", "mediatek,mt7986-sgmiisys_1", "syscon";
		reg = <0 0x10070000 0 0x1000>;
		#clock-cells = <1>;
	};

	topmisc: topmisc@11d10000 {
		compatible = "mediatek,mt7981-topmisc", "syscon";
		reg = <0 0x11d10000 0 0x10000>;
		#clock-cells = <1>;
	};

	snand: snfi@11005000 {
		compatible = "mediatek,mt7986-snand";
		reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
		reg-names = "nfi", "ecc";
		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
			 <&infracfg CLK_INFRA_NFI1_CK>,
			 <&infracfg CLK_INFRA_NFI_HCK_CK>;
		clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
		assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
				  <&topckgen CLK_TOP_NFI1X_SEL>;
		assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
					 <&topckgen CLK_TOP_CB_M_D8>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	mmc0: mmc@11230000 {
		compatible = "mediatek,mt7986-mmc",
					"mediatek,mt7981-mmc";
		reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg CLK_INFRA_MSDC_CK>,
			 <&infracfg CLK_INFRA_MSDC_HCK_CK>,
			 <&infracfg CLK_INFRA_MSDC_66M_CK>,
			 <&infracfg CLK_INFRA_MSDC_133M_CK>;
		assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
				  <&topckgen CLK_TOP_EMMC_400M_SEL>;
		assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
					 <&topckgen CLK_TOP_CB_NET2_D2>;
		clock-names = "source", "hclk", "axi_cg", "ahb_cg";
		status = "disabled";
	};

	wed_pcie: wed_pcie@10003000 {
		compatible = "mediatek,wed_pcie";
		reg = <0 0x10003000 0 0x10>;
	};

	spi0: spi@1100a000 {
		compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0 0x1100a000 0 0x100>;
		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&topckgen CLK_TOP_CB_M_D2>,
			 <&topckgen CLK_TOP_SPI_SEL>,
			 <&infracfg CLK_INFRA_SPI0_CK>,
			 <&infracfg CLK_INFRA_SPI0_HCK_CK>;

		clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
		status = "disabled";
	};

	spi1: spi@1100b000 {
		compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0 0x1100b000 0 0x100>;
		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&topckgen CLK_TOP_CB_M_D2>,
			 <&topckgen CLK_TOP_SPIM_MST_SEL>,
			 <&infracfg CLK_INFRA_SPI1_CK>,
			 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
		clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
		status = "disabled";
	};

	spi2: spi@11009000 {
		compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0 0x11009000 0 0x100>;
		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&topckgen CLK_TOP_CB_M_D2>,
			 <&topckgen CLK_TOP_SPI_SEL>,
			 <&infracfg CLK_INFRA_SPI2_CK>,
			 <&infracfg CLK_INFRA_SPI2_HCK_CK>;
		clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
		status = "disabled";
	};

	consys: consys@10000000 {
		compatible = "mediatek,mt7981-consys";
		reg = <0 0x10000000 0 0x8600000>;
		memory-region = <&wmcpu_emi>;
	};

	xhci: usb@11200000 {
		compatible = "mediatek,mt7986-xhci",
			     "mediatek,mtk-xhci";
		reg = <0 0x11200000 0 0x2e00>,
		      <0 0x11203e00 0 0x0100>;
		reg-names = "mac", "ippc";
		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
			 <&infracfg CLK_INFRA_IUSB_CK>,
			 <&infracfg CLK_INFRA_IUSB_133_CK>,
			 <&infracfg CLK_INFRA_IUSB_66M_CK>,
			 <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
		clock-names = "sys_ck",
			      "ref_ck",
			      "mcu_ck",
			      "dma_ck",
			      "xhci_ck";
		phys = <&u2port0 PHY_TYPE_USB2>,
		       <&u3port0 PHY_TYPE_USB3>;
		vusb33-supply = <&reg_3p3v>;
		status = "disabled";
	};

	usb_phy: usb-phy@11e10000 {
		compatible = "mediatek,mt7981",
			     "mediatek,generic-tphy-v2";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0x11e10000 0x1700>;
		status = "disabled";

		u2port0: usb-phy@0 {
			reg = <0x0 0x700>;
			clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
			clock-names = "ref";
			#phy-cells = <1>;
		};

		u3port0: usb-phy@700 {
			reg = <0x700 0x900>;
			clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
			clock-names = "ref";
			#phy-cells = <1>;
			mediatek,syscon-type = <&topmisc 0x218 0>;
			status = "okay";
		};
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};

	efuse: efuse@11f20000 {
		compatible = "mediatek,mt7981-efuse",
			     "mediatek,efuse";
		reg = <0 0x11f20000 0 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;
		status = "okay";

		thermal_calibration: thermal-calib@274 {
			reg = <0x274 0xc>;
		};

		phy_calibration: phy-calib@8dc {
			reg = <0x8dc 0x10>;
		};

		comb_rx_imp_p0: usb3-rx-imp@8c8 {
			reg = <0x8c8 1>;
			bits = <0 5>;
		};

		comb_tx_imp_p0: usb3-tx-imp@8c8 {
			reg = <0x8c8 2>;
			bits = <5 5>;
		};

		comb_intr_p0: usb3-intr@8c9 {
			reg = <0x8c9 1>;
			bits = <2 6>;
		};
	};

	afe: audio-controller@11210000 {
		compatible = "mediatek,mt79xx-audio";
		reg = <0 0x11210000 0 0x9000>;
		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
			 <&infracfg CLK_INFRA_AUD_26M_CK>,
			 <&infracfg CLK_INFRA_AUD_L_CK>,
			 <&infracfg CLK_INFRA_AUD_AUD_CK>,
			 <&infracfg CLK_INFRA_AUD_EG2_CK>,
			 <&topckgen CLK_TOP_AUD_SEL>;
		clock-names = "aud_bus_ck",
			      "aud_26m_ck",
			      "aud_l_ck",
			      "aud_aud_ck",
			      "aud_eg2_ck",
			      "aud_sel";
		assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
				  <&topckgen CLK_TOP_A1SYS_SEL>,
				  <&topckgen CLK_TOP_AUD_L_SEL>,
				  <&topckgen CLK_TOP_A_TUNER_SEL>;
		assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
					 <&topckgen CLK_TOP_APLL2_D4>,
					 <&topckgen CLK_TOP_CB_APLL2_196M>,
					 <&topckgen CLK_TOP_APLL2_D4>;
		status = "disabled";
	};

	ice: ice_debug {
		compatible = "mediatek,mt7981-ice_debug",
			   "mediatek,mt2701-ice_debug";
		clocks = <&infracfg CLK_INFRA_DBG_CK>;
		clock-names = "ice_dbg";
	};

	wifi: wifi@18000000 {
		compatible = "mediatek,mt7981-wmac";
		resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
		reset-names = "consys";
		pinctrl-0 = <&wifi_dbdc_pins>;
		pinctrl-names = "dbdc";
		clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
			 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
		clock-names = "mcu", "ap2conn";
		reg = <0 0x18000000 0 0x1000000>,
		      <0 0x10003000 0 0x1000>,
		      <0 0x11d10000 0 0x1000>;
		interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
		memory-region = <&wmcpu_emi>;
		status = "disabled";
	};
};

Changes to target/linux/mediatek/filogic/base-files/etc/board.d/02_network file:

	hilink,rm65|\

above asus,tuf-ax6000)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5" eth1
lines.

Changes to filogic.mk under TARGET_DEVICES += mediatek_mt7988a-rfb line:

define Device/hilink_rm65
  DEVICE_VENDOR := Hilink
  DEVICE_MODEL := RM65 development kit
  DEVICE_DTS := mt7981b-rm65
  SUPPORTED_DEVICES += mediatek,mt7981-rfb
  DEVICE_DTS_DIR := ../dts
  DEVICE_DTC_FLAGS := --pad 4096
  DEVICE_DTS_LOADADDR := 0x43f00000
  DEVICE_PACKAGES := kmod-mt7981-firmware kmod-usb3 e2fsprogs f2fsck mkf2fs mt7981-wo-firmware
  KERNEL_LOADADDR := 0x44000000
  KERNEL := kernel-bin | gzip
  KERNEL_INITRAMFS := kernel-bin | lzma | \
	fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
  KERNEL_INITRAMFS_SUFFIX := .itb
  KERNEL_IN_UBI := 1
  UBOOTENV_IN_UBI := 1
  IMAGES := sysupgrade.itb
  IMAGE_SIZE := $$(shell expr 64 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m
  IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | pad-rootfs | append-metadata
endef
TARGET_DEVICES += hilink_rm65

Standard running on Openwrt 21.02.7 with modifications from mediatek.
To be able to run Openwrt 23.05.5 on it bootloader has to be upgraded.
See this url: https://forum.openwrt.org/t/mediatek-mt7981-rfb-replace-openwrt-snapshot-21-02-with-newer-snapshot-or-stable-version-of-openwrt/175376/5

First stage:
Download bootloader files from:
[https://downloads.openwrt.org/releases/23.05.5/targets/mediatek/filogic/openwrt-23.05.5-mediatek-filogic-mediatek_mt7981-rfb-spim-nand-bl31-uboot.fip](https://downloads.openwrt.org/releases/23.05.5/targets/mediatek/filogic/openwrt-23.05.5-mediatek-filogic-mediatek_mt7981-rfb-spim-nand-bl31-uboot.fip)
[https://downloads.openwrt.org/releases/23.05.5/targets/mediatek/filogic/openwrt-23.05.5-mediatek-filogic-mediatek_mt7981-rfb-spim-nand-preloader.bin](https://downloads.openwrt.org/releases/23.05.5/targets/mediatek/filogic/openwrt-23.05.5-mediatek-filogic-mediatek_mt7981-rfb-spim-nand-preloader.bin)

Have a FTPD server ready at PC hosting the bootloader files.
Make sure the TCPIP adress of router and PC fall into same network adress range.
(for example router on 192.168.2.254 and PC on 192.168.2.10. But can choose adress range freely)

Connect USB->UART device to RM65 router UART pins (TX,RX,GND dont connect VCC)
start terminal program on pc to watch UART output

Start up router
Press key to interrupt bootsequence

Upgrade BL2 bootloader file
(mt981-rfb-spim-nand-preloader.bin)
dont reboot RM65 router yet.

Upgrade BL31 bootloader file
(mt7981-rfb-spim-nand-bl31-uboot.fip)
when finished reboot router.

Second stage:
Reboot the router and press key during bootup to get into bootloader shell.

Download Openwrt 23.05.5 initram.itb and sysupgrade files:
[https://downloads.openwrt.org/releases/23.05.5/targets/mediatek/filogic/openwrt-23.05.5-mediatek-filogic-mediatek_mt7981-rfb-initramfs.itb](https://downloads.openwrt.org/releases/23.05.5/targets/mediatek/filogic/openwrt-23.05.5-mediatek-filogic-mediatek_mt7981-rfb-initramfs.itb)
[https://downloads.openwrt.org/releases/23.05.5/targets/mediatek/filogic/openwrt-23.05.5-mediatek-filogic-mediatek_mt7981-rfb-squashfs-sysupgrade.itb](https://downloads.openwrt.org/releases/23.05.5/targets/mediatek/filogic/openwrt-23.05.5-mediatek-filogic-mediatek_mt7981-rfb-squashfs-sysupgrade.itb)
Having TFTPD server ready which can serve the "initramfs.itb" ramdisk kernel file for initial startup.
(IP addresses choosen here is 192.168.2.1 for RM65 router and 192.168.2.10 for PC, can choose freely)

Then copy paste the following lines in bootloader shell:
ubi detach ubi;mtd erase ubi;ubi part ubi;ubi create ubootenv 126976;ubi create ubootenv2 126976;setenv serverip 192.168.2.10;setenv ipaddr 192.168.2.1;setenv loadaddr '0x46000000';setenv bootconf 'config-1#';setenv bootcmd 'ubi read $loadaddr fit;bootm $loadaddr#$bootconf';setenv bootfile 'initramfs.itb';saveenv;saveenv;tftpboot;bootm $loadaddr#$bootconf

This will re-create partition scheme and setup bootloader environmental values and saving it to nvram and then load up initramfs.itb from TFTP server and then boot from it.

Third stage:
If everything went well, then the router is now starting up from Openwrt 23-05.5 ramdisk.
This is only ramdisk, the process of really installing the Openwrt-23 firmware will be next.

When loaded you can go to Luci interface on 192.168.2.254
and then go to administration -> upgrade firmware
and choose your sysupgrade.itb firmware file (mt7981-rfb-spim-nand compatible .itb files) to upload it to the router.
Please uncheck "keep configuration settings" because for first upgrade its better to reset its settings.

Then after the RM65 router restarts, it should start up with Openwrt 23-05.5 installed.
To get lan port 5 working and leds configured, compile the firmware with the mt7981b-rm65.dts and mt7981b-rm65.dtsi.

frollic · October 19, 2024, 3:27pm

You own one, we don't https://openwrt.org/docs/guide-developer/adding_new_device

Axkman · October 19, 2024, 4:34pm

Ehh your link is about getting openwrt firmware working on a device.
I already got openwrt working on the router, this topic is just an attempt of me to request that Openwrt adds the device. Like a device commit.

Is this not the right place for it? If no, where should I do it?

Thank you!

frollic · October 19, 2024, 4:51pm

That's still for you to do.

https://openwrt.org/submitting-patches

protectivedad · February 27, 2025, 5:42pm

I'd like to say thanks for taking the time to post this. I picked up one of these and was looking at getting openwrt 24.10 running on it. I noticed your instructions on updating the BL2 and FIP partitions. Why does this need to be done? openwrt 24.10 version of the files are different then 23.05 version. Perhaps if I new why I was upgrading them I'd know the answer to my other questions. Do I need to use the 24.10 BL2/FIP with openwrt 24.10? Do I need to change them each update?

I looked at the link you provided they just mention:

What features are on the HLK-RM65 that need the bootloader updated?

daniel · February 27, 2025, 6:10pm

Because the vendor bootloader is different from the one used for MediaTek's MT7981B reference board -- it's also actually a different device, this is "HiLink RM65" and not "MediaTek MT7981B Reference Board". The existing vendor bootloader can easily be supported, but someone needs to create a proper image for that actual hardware, ie. create the Device Tree, create default network settings and generate an image compatible with the vendor firmware and bootloader, write a nice commit message and documentation, submit it to the mainling list or open a pull-request on Github.

You can look at any other commit about adding support for an MT7981-based router, many are very very similar:

github.com/openwrt/openwrt

mediatek: filogic: add support for Tenbay WR3000K

committed 05:45PM - 22 Dec 24 UTC

jian-yu

+273 -1

Tenbay WR3000K is an 802.11ax (Wi-Fi 6) router, based on MediaTek MT7981B. - So…C: MetiaTek MT7981B - RAM: Hynex H5TQ2G863GFR 512MiB - Flash: Winbond W25N01GVZEIG 128MiB - Wi-Fi: MediaTek MT7976C (2.4GHz/5GHz, 802.11ax, 2x2 MIMO, AX3000) - MediaTek MT7915E: 2.4GHz and 5GHz - Ethernet: 1x 10/100/1000 Mbps WAN + 3x 10/100/1000 Mbps LAN - Switch: MediaTek MT7531AE - UART: J4 (115200 baud) - LEDs: Power - Buttons: Reset, WPS - PWR: 12V/1A DC, 5.5×2.1 connector | Vendor | OpenWrt Interface | Address | Notes | |---------|-------------------|---------------|------------------------------------------------| | WAN | wan | Label MAC | Stored MAC in factory + offset 4, label MAC is Stored MAC - 2 | | LAN | br-lan | Label MAC+1 | | | 2.4GHz | phy0-ap0 | Label MAC + 2 | | | 5GHz | phy1-ap0 | Label MAC + 3 | | - 0x000000000000-0x000000100000 : "BL2" - 0x000000100000-0x000000180000 : "u-boot-env" - 0x000000180000-0x000000380000 : "Factory" - 0x000000380000-0x000000580000 : "FIP" - 0x000000580000-0x000003580000 : "ubi" - 0x000003580000-0x000006580000 : "ubi1" - 0x000006580000-0x0000065a0000 : "Product" - 0x0000065a0000-0x000007580000 : "Custom" - The original partition-Ubi partition-Ubi1 is an AB dual system, and Openwrt only uses Ubi. So flash requires modifying the uboot variable `boot_from=ubi` to ensure that it only starts from Ubi. - The Product and Custom partitions are original and only exist to align with the original layout; they are not used by OpenWrt. - id: 0, kernel - id: 1, rootfs - id: 2, rootfs_data - **USB-to-TTL Serial Adapter** (e.g., CH340 or CP2102). - **Dupont Wires** (male-to-male, 3 wires). - **PC/Laptop** with a serial communication tool. - Screwdriver (to open the router case). 1. **OpenWrt Firmware**: - Download the appropriate `wr3000k-<build_time>-mediatek-filogic-tenbay_wr3000k-squashfs-sysupgrade.bin` firmware file for your router from the [OpenWrt website](https://openwrt.org/). 2. **Serial Communication Tool**: - Windows: PuTTY, Tera Term. - Linux/Mac: Minicom, screen. 3. (Optional) **TFTP Server**: - Install a TFTP server like Tftpd64 or tftp-hpa. --- 1. Open the router casing and locate the **TX, RX, and GND** pins. 2. Connect the router pins to the USB-to-TTL adapter as follows: - **TX (router)** → **RX (adapter)** - **RX (router)** → **TX (adapter)** - **GND (router)** → **GND (adapter)** 3. Do **not** connect the VCC pin to avoid damage. - **Baud rate**: 115200 - **Data bits**: 8 - **Stop bits**: 1 - **Parity**: None - **Flow control**: None --- 1. Power on the router and observe the serial terminal output. 2. When prompted (e.g., `Hit any key to stop autoboot: 3`), press the '/' key quickly to interrupt the boot process. 3. You will see the U-Boot Boot Menu: ```plaintext *** U-Boot Boot Menu *** 1. Factory mode 2. Startup system (Default) 3. Upgrade firmware 4. Upgrade ATF BL2 5. Upgrade ATF FIP 6. Upgrade single image 7. Load image 0. U-Boot console Press UP/DOWN to move, ENTER to select, ESC/CTRL+C to quit ``` 4. Select Option 0 by typing 0 and pressing Enter. 5. Input into ```plaintext MT7981> setenv boot_from ubi MT7981> saveenv Saving Environment to MTD... Erasing on MTD device 'nmbm0'... OK Writing to MTD device 'nmbm0'... OK OK MT7981> printenv baudrate=115200 boot_from=ubi ... ``` the above indicates system will start from *ubi*. and then type ```plaintext MT7981> reset ``` will boot from *ubi* 1. Power on the router and observe the serial terminal output. 2. When prompted (e.g., `Hit any key to stop autoboot: 3`), press the '/' key quickly to interrupt the boot process. 3. You will see the U-Boot Boot Menu: ```plaintext *** U-Boot Boot Menu *** 1. Factory mode 2. Startup system (Default) 3. Upgrade firmware 4. Upgrade ATF BL2 5. Upgrade ATF FIP 6. Upgrade single image 7. Load image 0. U-Boot console Press UP/DOWN to move, ENTER to select, ESC/CTRL+C to quit ``` 4. Choose Option 3: Upgrade Firmware Enter Upgrade Mode Select Option 3 by typing 3 and pressing Enter. Upgrade Methods You will be prompted to choose between: ```plaintext *** Upgrading Firmware *** Run image after upgrading? (Y/n): y Available load methods: 0 - TFTP client (Default) 1 - Xmodem 2 - Ymodem 3 - Kermit 4 - S-Record 5 - RAM Select (enter for default): 0 Input U-Boot's IP address: 192.168.1.1 Input TFTP server's IP address: 192.168.1.10 Input IP netmask: 255.255.255.0 Input file name: wr3000k-<build_time>-mediatek-filogic-tenbay_wr3000k-squashfs-sysupgrade.bin ``` Type Enter to proceed. The router will erase the old firmware and write the new one. Signed-off-by: Jianyu Zhuang <xzjianyu@gmail.com> Link: https://github.com/openwrt/openwrt/pull/17172 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

github.com/openwrt/openwrt

mediatek/filogic: add Keenetic KN-3811 support

committed 06:52PM - 08 Dec 24 UTC

Linaro1985

+390 -0

Specification: * Mediatek MT7981BA * 256 MB SPI-NAND * 512 MB DDR4 RAM * MT7…976CN DBDC AX Wi-Fi * MediaTek MT7531AE (3x LAN Gigabit ports) + Internal Gbe Phy (1x WAN Gigabit port) * 4x LED (power, internet, fn, wifi) * 3x buttons (wps, fn, reset) * 1x USB 3.0 port Serial Interface: * 3 Pins GND, RX, TX * Settings: 115200, 8N1 Notes: * The device supports dual boot mode * Fn led reassigned to wlan 2.4 Flash instruction: The only way to flash OpenWrt image is to use tftp recovery mode in U-Boot: 1. Configure PC with static IP 192.168.1.2/24 and tftp server. 2. Rename "openwrt-mediatek-filogic-keenetic_kn-3811-squashfs-factory.bin" to "KN-3811_recovery.bin" and place it in tftp server directory. 3. Connect PC with ethernet port, press the reset button, power up the device and keep button pressed until status led start blinking. 4. Device will download file from server, write it to flash and reboot. Signed-off-by: Maxim Anisimov <maxim.anisimov.ua@gmail.com> Link: https://github.com/openwrt/openwrt/pull/17135 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

protectivedad · February 27, 2025, 8:09pm

I thought it was a requirement because of a newer kernel or something and the bootloader needed to be updated. From what you say if I understand correctly if I want to use the "wrong" (reference board) firmware I need to write the "wrong" BL2/FIP, but if I create a proper firmware I don't need to change the BL2/FIP.

Thanks for the examples. I will look through the source for the MT7981B and see if I can put something together.