News came out today about a raspberry pi5 that will sport:
a) 4 arm a76 cores (with some cryptography acceleration, and dedicated 512KB cache per core, plus some unified L3 cache)*
b) faster SD cards
c) offer an easier access to a single lane PCIe2.0 slot (some breakout solution needed to actually use this for a PCIe card like a (multiport) NIC)
d) still comes with a built-in gigabit ethernet port
e) offers higher memory speeds
f) might offer two USB3 ports
g) will also cost more than its predecessor and consume more power.
I think this will make a great basis again for a wired-only OpenWrt router that hopefully is reasonably available. It will also be closer to more modern arm networking SBCs narrowing the gap (not leap frogging the competition). If one likes raspberries that IMHO is great news.
EDIT: German source I git this information from:
*) Not wanting to insult the a76, a competent core and a clear step up from the already nice a72 in the pi4, but the core design is from 2018 and there are already two successor generations; I would love to learn what caused the decision for the 76, maybe the design of the pi5 was started when the 76 was hot and new or maybe the 77 and 78 are too power hungry...
Jeff Geerling says the 1x lane can run at PCIe 3.0 speeds with a boot config setting. Now why it's not set that way by default, I have no idea. Maybe the FPC can't deal with that, or there's EMI concerns, etc.
The SoC apparently has 5 lanes, 4 of those goes to that "southbridge" that provides the Gigabit Ethernet and USB ports. My speculation is that they will have a CM5 with all the PCIe lanes broken out.
But that is one of the points, the base pi5 will have a (non-standard) PCIe port, that with an appropriate adapter will allow to connect multiport ethernet NICs so offering a way to a non-USB router. However unless the prices fall fast this is going to be close in price and likely power consumption to x86 low end solutions, but that is a different question...
Cost (licensing, manufacture), availability, kernel support, design lead time, thermal requirements, physicals space requirements, marketing requirements (how much faster than Pi4)…
It’s a big decision and all of them will have been factors. I’m surprised that they ended up requiring active cooling as that seemed to be a pretty key feature of the Pi family, they’re also ratcheting up the cost with each generation. It will probably be a reason for me not to upgrade.
That is hopefully the case, but a newer smaller process will also tend to increase thermal density (power dissipation over smaller area) and hence might still have different throttling properties as an older larger process. But I guess numbers will come out in time (well before I will be in the market again for a SBC).
[Yawn] Wake me up when they make one with dual RJ-45 ports,,, I would happily trade a pair of USB ports (even if it was the pair of USB 3 ones, meaning, I would be left with USB 2 only) for a second RJ-45...
Once they make a CM5, that will be really interesting to see what sort of router-like carrier boards appear.
Imagine if the carrier board allowed the attaching of, say, a 4-port 2.5 GbE switch (through the PCI 2.0), or some really decent antennas making use of one of the USB 3 connections. Then the 1GbE port could be the WAN port.
That new southbridge chip allows the sort of throughput that a much more modern router would want.
I really like the idea of just taking out the MicroSD card and backing it up/restoring the whole thing in bulk. Or flashing the eMMC (if it has one), through a USB connection (and it would follow that the router would need to be normally kept in a physically secure place). No more uploading firmware files through serial connections, tftp, or sketchy web interfaces; these are really not fun ways to install OpenWRT.
But the physical sizes are such that it might still be necessary to ditch a pair of USB ports to make room for a single RJ-45... There are two stacked pairs if USB ports, and each pair is about the size of an RJ-45...
The specs itself are fine, not magnificent, but fine.
What's not at all fine, are:
SOC on the top of the PCB, instead of moving it to the bottom, where it could be passively cooled with contact to a metal case
non-standard PCIe connecter (either M.2, mini-PCIe or regular PCIe angled to the side would have been fine), this just means extra costs for the special adapter
they've now designed their own PMIC, 'great' - but USB-PD with 5V/ 5A is not great, aside from it being non-standard again, the voltage drop will continue being a problem (which is why their own power supplies are delivering 5.1V, not 5.0V…), this would have been an opportunity to use a 12V barrel plug or at least more common USB-PD voltage/ current combinations.
not using a (vertical) CR2032 battery holder, instead of opting to a 2-pin solution (again, more expensive batteries, instead of using standard components - at least this one is less of a problem than the PCIe connector).
Especially the non-standard PCIe connector and the CPU/ SOC location on the top (cooling with any added hats, including the PCIe one, is virtually impossible) are major design defects.
Prices on the street and availability are probably to be seen, given recent history I wouldn't hold high hopes for that.
that with a bit of additional spacing active cooling and HATs can work together all the while avoiding thermal throttling.
Here is a plot with measurements under different conditions (from the article above):
Bright green is the relevant curve. Not terribly elegant, but IMHO not a show stopper.
I guess this is simply a race against system power consumption... at one point it will become more feasible t increase the voltage again instead of the current. For the pi5 the promise is that it will work with older raspberry usb-c power supplies, albeit with some trade-offs (powering USB devices and CPU frequency IIRC), which might have carried the day this round, but if consumption increases again I guess that is a point worth revisiting...
I would simply hope that the RK3588's development moving fast enough to be in standard kernel support, so that NanoPi R6S/R6C can have full support, even the Pi5 might have the possibility to expand to dual 2.5G with CM5, the size, speed and the cost won't be able to compete with R6S/R6C at all