I looked a little more into the PHY's reset hardware.
When comparing the PCB between EAP225 v3 and v4, there is clearly visible, that GPIO 11 is missing in v4.
Pinout of the SoC
Picture of the SoC in EAP225 v4
. GPIO11 is the pad in the centerline of the 3
at the white silkscreen marking C370
.
There is no outgoing trace visible.
Picture of the SoC in EAP225 v3
from FCC (Page 7). GPIO 11 has an outgoing trace.
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What I think would be possible:
Using the Supervisor Circuit to reset the PHY as well on a reboot.
The PHY's Reset Pullup is connected to the RESET output of the Supervisor Circuit PT7A7514W
. The reset will be pulled down for 200ms in case, the voltage drops below an threshold, or the Watchdog input
is triggered. This Input can be triggered by the SoC using GPIO 3 & 4 which are probably connected to a tri-state buffer in front of the Watchdog input
. The GPIO 3 & 4 are described in target/linux/ath79/dts/qca956x.dtsi
.
Connections:
GPIO3 - R293 - tri-state buffer - PT7A7514W
GPIO4 - R292 - (tri-state buffer) - R288 - VCC (pullup)
My knowledge on the device tree is somewhat limited, so I don't know if this reset behavior is already happening or possible.