Most likely because you did not pass the correct initvals
Exactly. But I have no idea what is wrong. Public datasheet didn't help me.
Most likely there is a debug tool in the stock firmware which lets you print out values of registers used by the driver.
I'm working on adding support for the EnGenius ESR600, which has an Atheros AR8327 (not AR8337) with MT7620A, and I'm having the same issue with two of the ports being non-functional. Ports 1,2, and 5 work... ports 3 and 4 do not. However -- booting with the stock U-Boot all the ports do work. I've used the U-Boot "mdio.r/mdio.w" commands to dump the AR8327 registers after U-Boot has initialized them for a tftpboot, and there are no differences that would explain this behavior. You can work from the datasheet register address to the mdio commands to read them with this trivial shell script:
#!/bin/sh
regaddr=$1
regaddr=$((regaddr >> 1))
r1=$((regaddr & 0x1E))
regaddr=$((regaddr >> 5))
r2=$((regaddr & 7))
regaddr=$((regaddr >> 3))
page=$((regaddr & 0x1FF))
printf 'mdio.w %d 0 %d\n' 0x18 $page
printf 'mdio.r %d %d\n' $((0x10 | r2)) $((r1 + 1))
printf 'mdio.r %d %d\n' $((0x10 | r2)) $r1
So the output given 0x80 (port1 status register) is:
mdio.w 24 0 0
mdio.r 18 1
mdio.r 18 0
Did anyone make any progress on figuring out the dead port issue??
hello i have patch where working all 5 port on lava lr25g001 and archer c5 v4 https://drive.google.com/file/d/14wF9qCgdTH9chfsr7ezU-u8Nas46Vl7X/view?usp=sharing
Thanks for that patch. At first reading it feels as though the code that's conditional on the mediatek,phy_init="disable" flag could be conditional on the "mediatek,mdio-mode". The engenius_esr600, lava_lr-25g001, and the edimax_ew-747x series are the only DTS files that use the mdio-mode=1 setting (I guess there may be other non-DTS based routers though).
+++ openwrt_lava/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7620.c 2018-11-29 21:21:10.349436742 +0300
@@ -88,6 +88,7 @@ static void mt7620_hw_init(struct mt7620
{
u32 i;
u32 val;
+ int init_phy4 = 1;
u32 is_BGA = (rt_sysc_r32(0x0c) >> 16) & 1;
rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
@@ -96,6 +97,11 @@ static void mt7620_hw_init(struct mt7620
/* Enable MIB stats */
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
+ if(!gsw->phy_init) {
+ init_phy4 = 0;
+ goto no_phy_init;
+ }
+
if (mdio_mode) {
u32 val;
@@ -184,6 +190,7 @@ static void mt7620_hw_init(struct mt7620
_mt7620_mii_write(gsw, 2, 16, 0x1515);
_mt7620_mii_write(gsw, 3, 16, 0x0f0f);
+no_phy_init:
/* CPU Port6 Force Link 1G, FC ON */
mtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
@@ -191,6 +198,8 @@ static void mt7620_hw_init(struct mt7620
mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
/* setup port 4 */
+ if (!init_phy4)
+ return;
if (gsw->port4 == PORT4_EPHY) {
u32 val = rt_sysc_r32(SYSC_REG_CFG1);
@@ -245,6 +254,7 @@ static int mt7620_gsw_probe(struct platf
{
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
const char *port4 = NULL;
+ const char *phy_init = NULL;
struct mt7620_gsw *gsw;
struct device_node *np = pdev->dev.of_node;
@@ -257,6 +267,11 @@ static int mt7620_gsw_probe(struct platf
return PTR_ERR(gsw->base);
gsw->dev = &pdev->dev;
+ gsw->phy_init = 1;
+
+ of_property_read_string(np, "mediatek,phy_init", &phy_init);
+ if (phy_init && !strcmp(phy_init, "disable"))
+ gsw->phy_init = 0;
of_property_read_string(np, "mediatek,port4", &port4);
if (port4 && !strcmp(port4, "ephy"))
diff -ruNp openwrt/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7620.h openwrt_lava/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7620.h
--- openwrt/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7620.h 2018-11-29 20:18:16.601341759 +0300
+++ openwrt_lava/target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/gsw_mt7620.h 2018-11-29 21:21:10.349436742 +0300
@@ -102,6 +102,7 @@ struct mt7620_gsw {
void __iomem *base;
int irq;
int port4;
+ int phy_init;
unsigned long int autopoll;
};
Yeah, that's the piece I identified as being relevant to my ESR600. I haven't had a chance to try it out yet though. I may get to it tomorrow.
Looked over the existing code and what this patch does, and realized you could get almost the same effect by adding, in the DTS,
&gsw {
mediatek,port4="gmac";
};
which will skip the port4 init when the ethernet device also has mediatek,mdio-mode set.
The important difference between your patch and just doing the above is that you skip the setup of global page 0 and 2, so it doesn't execute
/* global page 0 */
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x8000);
_mt7620_mii_write(gsw, gsw->ephy_base + 0, 30, 0xa000);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 30, 0xa000);
_mt7620_mii_write(gsw, gsw->ephy_base + 2, 30, 0xa000);
_mt7620_mii_write(gsw, gsw->ephy_base + 3, 30, 0xa000);
_mt7620_mii_write(gsw, gsw->ephy_base + 0, 4, 0x05e1);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 4, 0x05e1);
_mt7620_mii_write(gsw, gsw->ephy_base + 2, 4, 0x05e1);
_mt7620_mii_write(gsw, gsw->ephy_base + 3, 4, 0x05e1);
/* global page 2 */
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0xa000);
_mt7620_mii_write(gsw, gsw->ephy_base + 0, 16, 0x1111);
_mt7620_mii_write(gsw, gsw->ephy_base + 1, 16, 0x1010);
_mt7620_mii_write(gsw, gsw->ephy_base + 2, 16, 0x1515);
_mt7620_mii_write(gsw, gsw->ephy_base + 3, 16, 0x0f0f);
so it would be interesting to know why those writes stop things from working. I tried moving them up into the tail of the preceding if/else so they're skipped if the ethernet is in mdio-mode, and that worked fine. But it leaves me wondering if we're just benefiting from not touching the PHYs after the stock U-Boot has set them up...
fixes and cleanup of MT7620 ethernet driver now in master, ready to backport after testing
it fixes the problem of some ports not working with AR8327 or other Atheros switches