Hi all,
HELP!
I have followed the guide here:
Including the git page section.
I can get into RAM openwrt but once i complete the scp and sysupgrade it finishes with a reboot that goes back to linksys firmware. (see the below)
Is there anything I am doing wrong?
I have connected all four UART wires to get the terminal to function correctly or I got a whitenoise instead.
Running sysupgrade terminal info:
root@OpenWrt:/# sysupgrade -n -F -v /tmp/sysupgrade.bin
Mon Jul 15 22:17:01 UTC 2024 upgrade: Commencing upgrade. Closing all shell sessions.
Watchdog handover: fd=3
- watchdog -
Watchdog does not have CARDRESET support
Mon Jul 15 22:17:02 UTC 2024 upgrade: Sending TERM to remaining processes ...
Mon Jul 15 22:17:06 UTC 2024 upgrade: Sending KILL to remaining processes ...
[ 184.187169] stage2 (2653): drop_caches: 3
Mon Jul 15 22:17:12 UTC 2024 upgrade: Switching to ramdisk...
Mon Jul 15 22:17:15 UTC 2024 upgrade: Performing system upgrade...
[ 186.864704] do_stage2 (2653): drop_caches: 3
Unlocking firmware ...
Writing from <stdin> to firmware ...
Mon Jul 15 22:18:07 UTC 2024 upgrade: Upgrade completed
Mon Jul 15 22:18:08 UTC 2024 upgrade: Rebooting system...
umount: can't unmount /dev: Resource busy
umoun[ 239.657214] reboot: Restarting system
t: can't unmount /tmp: Resource busy
===================================================================
MT7621 stage1 code Mar 12 2015 14:43:30 (ASIC)
CPU=500000000 HZ BUS=166666666 HZ
==================================================================
Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x31100000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-800Mhz ===
PLL3 FB_DL: 0x13, 1/0 = 557/467 4D000000
PLL4 FB_DL: 0x1b, 1/0 = 556/468 6D000000
PLL2 FB_DL: 0x1c, 1/0 = 540/484 71000000
do DDR setting..[01F40000]
Apply DDR3 Setting...(use customer AC)
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120
--------------------------------------------------------------------------------
0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0007:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0008:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0009:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
000F:| 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
0010:| 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
0011:| 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
0012:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0013:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DRAMC_DQSCTL1[0e0]=14000000
DRAMC_DQSGCTL[124]=80000000
rank 0 coarse = 16
rank 0 fine = 56
B:| 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0
opt_dle value:8
DRAMC_DDR2CTL[07c]=C287220D
DRAMC_PADCTL4[0e4]=000022B3
DRAMC_DQIDLY1[210]=09080808
DRAMC_DQIDLY2[214]=07070706
DRAMC_DQIDLY3[218]=08070704
DRAMC_DQIDLY4[21c]=08070B07
DRAMC_R0DELDLY[018]=00003130
==================================================================
RX DQS perbit delay software calibration
==================================================================
1.0-15 bit dq delay value
==================================================================
bit| 0 1 2 3 4 5 6 7 8 9
--------------------------------------
0 | 7 6 7 9 5 7 7 7 3 5
10 | 6 7 7 9 6 7
--------------------------------------
==================================================================
2.dqs window
x=pass dqs delay value (min~max)center
y=0-7bit DQ of every group
input delay:DQS0 =48 DQS1 = 49
==================================================================
bit DQS0 bit DQS1
0 (1~94)47 8 (1~95)48
1 (1~92)46 9 (1~94)47
2 (1~93)47 10 (1~96)48
3 (1~95)48 11 (2~95)48
4 (1~94)47 12 (1~97)49
5 (1~96)48 13 (1~94)47
6 (1~96)48 14 (1~96)48
7 (1~96)48 15 (1~95)48
==================================================================
3.dq delay value last
==================================================================
bit| 0 1 2 3 4 5 6 7 8 9
--------------------------------------
0 | 8 8 8 9 6 7 7 7 4 7
10 | 7 8 7 11 7 8
==================================================================
==================================================================
TX perbyte calibration
==================================================================
DQS loop = 15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqsdly_pass[0]=15, finish count=1
dqs_perbyte_dly.last_dqsdly_pass[1]=15, finish count=2
DQ loop=15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqdly_pass[0]=15, finish count=1
dqs_perbyte_dly.last_dqdly_pass[1]=15, finish count=2
byte:0, (DQS,DQ)=(8,8)
byte:1, (DQS,DQ)=(8,8)
DRAMC_DQODLY1[200]=88888888
DRAMC_DQODLY2[204]=88888888
20,data:88
[EMI] DRAMC calibration passed
===================================================================
MT7621 stage1 code done
CPU=500000000 HZ BUS=166666666 HZ
===================================================================
U-Boot 1.1.3 (Jan 12 2016 - 14:20:42)
Board: Ralink APSoC DRAM: 128 MB
relocate_code Pointer at: 87f1c000
LINUX started...
THIS IS ASIC