The platform is Freescale's Layerscape ARM - I think LS1043. Secure Boot is enabled, but that hasn't stopped others in other situations.
I have an MX67. In FCC filings, the MX68W has much more stuff on it. @coliflower88, could you please tear down your board and give us some more detailed photos than those from the FCC release?
Other notes:
There's an FPGA on the MX6{7,8}{,W}, which it shares with the MS120. It looks like this is used to verify flash? This might be the way "in" to the platform, though it may also be why the platform will be difficult to defeat.
Here's a reddit thread examining this series.
Microsemi M2S005 FPGA = "Aikido" (合気道)
The FPGA and its role on these boards are called "Aikido" by Cisco (not just Meraki). This FPGA ("SmartFusion2 Aikido Security Chip") is integral in securing the boot process.
-
You can read about Aikido on the MS120-8 -- "Kelpie" -- here.
-
You can compare Meraki's MS120 U-Boot with the u-boot-marvell release they forked from for details about what's changed; this'll include the implementation of Aikido.
-
You can read Microsemi's documentation on the use of this Microsemi FPGA for implementing Secure Boot.
-
You can read Microsemi's documentation on best-practices for the SmartFusion2 line of FPGA SoCs; it does discuss potential attacks.
-
You can read Microsemi's documentation about the "Tamper" tamper-detection core available on the M2S005. Perhaps they haven't configured the Tamper core.
-
You can read Microsemi's documentation about the JTAG interface present and available for these SmartFusion2 FPGA SoCs.
-
You can read this EmbeddedComputing article to better understand the role this Microsemi SmartFusion2 FPGA SoC has in securing the boot chain.
Attacking "Aikido"
- Here is a paper from 2017 discussing some methods of attack against platforms which implement Secure Boot using an FPGA. Note that it doesn't provide a proof-of-concept for our Microsemi FPGA, but it discusses that:
Microsemi on the contrary offers non-volatile FPGA SoCs, which means that the FPGA is ready to be used directly after power-up and there is no configuration of the FPGA from external memory as is the case with standard SRAM-based FPGA SoCs from Xilinx and Altera. Hence, the threat [posed by a compromise FPGA] is imminent from the very start of the system.
To summarize the above cases, whenever the FPGA is configured early during the boot sequence, and this is often the case, a secure boot process can be compromised by a malicious core in the FPGA ...