And OpenWrt?
Also, to which UNIPHY is RTL connected to?
root@OpenWrt:/# cat /sys/kernel/debug/clk/clk_summary
enable prepare protect duty hardware
clock count count count rate accuracy phase cycle enable
-------------------------------------------------------------------------------------------------------
uniphy2_gcc_tx_clk 1 1 0 312500000 0 0 50000 Y
nss_port6_tx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port6_tx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy2_port6_tx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port6_tx_clk 1 1 0 125000000 0 0 50000 Y
uniphy2_gcc_rx_clk 1 1 0 312500000 0 0 50000 Y
nss_port6_rx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port6_rx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy2_port6_rx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port6_rx_clk 1 1 0 125000000 0 0 50000 Y
uniphy1_gcc_tx_clk 1 1 0 312500000 0 0 50000 Y
nss_port5_tx_clk_src 1 1 0 312500000 0 0 50000 Y
nss_port5_tx_div_clk_src 3 3 0 312500000 0 0 50000 Y
gcc_uniphy1_port5_tx_clk 1 1 0 312500000 0 0 50000 Y
gcc_uniphy0_port5_tx_clk 1 1 0 312500000 0 0 50000 Y
gcc_nss_port5_tx_clk 1 1 0 312500000 0 0 50000 Y
uniphy1_gcc_rx_clk 1 1 0 312500000 0 0 50000 Y
nss_port5_rx_clk_src 1 1 0 312500000 0 0 50000 Y
nss_port5_rx_div_clk_src 3 3 0 312500000 0 0 50000 Y
gcc_uniphy1_port5_rx_clk 1 1 0 312500000 0 0 50000 Y
gcc_uniphy0_port5_rx_clk 1 1 0 312500000 0 0 50000 Y
gcc_nss_port5_rx_clk 1 1 0 312500000 0 0 50000 Y
uniphy0_gcc_tx_clk 4 4 0 125000000 0 0 50000 Y
nss_port1_tx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port1_tx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy0_port1_tx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port1_tx_clk 1 1 0 125000000 0 0 50000 Y
nss_port2_tx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port2_tx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy0_port2_tx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port2_tx_clk 1 1 0 125000000 0 0 50000 Y
nss_port3_tx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port3_tx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy0_port3_tx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port3_tx_clk 1 1 0 125000000 0 0 50000 Y
nss_port4_tx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port4_tx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy0_port4_tx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port4_tx_clk 1 1 0 125000000 0 0 50000 Y
uniphy0_gcc_rx_clk 4 4 0 125000000 0 0 50000 Y
nss_port1_rx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port1_rx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy0_port1_rx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port1_rx_clk 1 1 0 125000000 0 0 50000 Y
nss_port2_rx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port2_rx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy0_port2_rx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port2_rx_clk 1 1 0 125000000 0 0 50000 Y
nss_port3_rx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port3_rx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy0_port3_rx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port3_rx_clk 1 1 0 125000000 0 0 50000 Y
nss_port4_rx_clk_src 1 1 0 125000000 0 0 50000 Y
nss_port4_rx_div_clk_src 2 2 0 125000000 0 0 50000 Y
gcc_uniphy0_port4_rx_clk 1 1 0 125000000 0 0 50000 Y
gcc_nss_port4_rx_clk 1 1 0 125000000 0 0 50000 Y
pcie20_phy1_pipe_clk 1 1 0 125000000 0 0 50000 Y
pcie1_pipe_clk_src 1 1 0 125000000 0 0 50000 Y
gcc_pcie1_pipe_clk 1 1 0 125000000 0 0 50000 Y
pcie20_phy0_pipe_clk 1 1 0 250000000 0 0 50000 Y
pcie0_pipe_clk_src 1 1 0 250000000 0 0 50000 Y
gcc_pcie0_pipe_clk 1 1 0 250000000 0 0 50000 Y
usb3phy_0_cc_pipe_clk 1 1 0 125000000 0 0 50000 Y
usb0_pipe_clk_src 1 1 0 125000000 0 0 50000 Y
gcc_usb0_pipe_clk 1 1 0 125000000 0 0 50000 Y
usb3phy_1_cc_pipe_clk 1 1 0 125000000 0 0 50000 Y
usb1_pipe_clk_src 1 1 0 125000000 0 0 50000 Y
gcc_usb1_pipe_clk 1 1 0 125000000 0 0 50000 Y
bias_pll_nss_noc_clk 1 1 0 416500000 0 0 50000 Y
nss_noc_bfdcd_clk_src 1 1 0 416500000 0 0 50000 Y
nss_noc_clk_src 2 2 0 416500000 0 0 50000 Y
gcc_ubi1_nc_axi_clk 0 0 0 416500000 0 0 50000 N
gcc_ubi1_axi_clk 0 0 0 416500000 0 0 50000 N
gcc_ubi0_nc_axi_clk 0 0 0 416500000 0 0 50000 N
gcc_ubi0_axi_clk 0 0 0 416500000 0 0 50000 N
gcc_nss_noc_clk 1 1 0 416500000 0 0 50000 Y
gcc_mem_noc_nss_axi_clk 1 1 0 416500000 0 0 50000 Y
bias_pll_cc_clk 1 1 0 300000000 0 0 50000 Y
nss_ppe_clk_src 15 15 0 300000000 0 0 50000 Y
gcc_crypto_ppe_clk 0 0 0 300000000 0 0 50000 N
gcc_port6_mac_clk 1 1 0 300000000 0 0 50000 Y
gcc_port5_mac_clk 1 1 0 300000000 0 0 50000 Y
gcc_port4_mac_clk 1 1 0 300000000 0 0 50000 Y
gcc_port3_mac_clk 1 1 0 300000000 0 0 50000 Y
gcc_port2_mac_clk 1 1 0 300000000 0 0 50000 Y
gcc_port1_mac_clk 1 1 0 300000000 0 0 50000 Y
gcc_nssnoc_ppe_clk 1 1 0 300000000 0 0 50000 Y
gcc_nssnoc_ppe_cfg_clk 1 1 0 300000000 0 0 50000 Y
gcc_nss_ppe_ipe_clk 1 1 0 300000000 0 0 50000 Y
gcc_nss_ppe_clk 1 1 0 300000000 0 0 50000 Y
gcc_nss_ppe_cfg_clk 1 1 0 300000000 0 0 50000 Y
gcc_nss_ppe_btq_clk 1 1 0 300000000 0 0 50000 Y
gcc_nss_edma_clk 1 1 0 300000000 0 0 50000 Y
gcc_nss_edma_cfg_clk 1 1 0 300000000 0 0 50000 Y
nss_ppe_cdiv_clk_src 1 1 0 75000000 0 0 50000 Y
gcc_nss_ptp_ref_clk 1 1 0 75000000 0 0 50000 Y
xo 18 18 0 19200000 0 0 50000 Y
a53pll 1 1 0 1382400000 0 0 50000 Y
apcs_alias0_clk_src 1 1 0 1382400000 0 0 50000 Y
apcs_alias0_core_clk 1 1 0 1382400000 0 0 50000 Y
pcie0_rchng_clk_src 1 1 0 19200000 0 0 50000 Y
gcc_pcie0_rchng_clk 1 1 0 19200000 0 0 50000 Y
gp3_clk_src 0 0 0 19200000 0 0 50000 N
gcc_gp3_clk 0 0 0 19200000 0 0 50000 N
gp2_clk_src 0 0 0 19200000 0 0 50000 N
gcc_gp2_clk 0 0 0 19200000 0 0 50000 N
gp1_clk_src 0 0 0 19200000 0 0 50000 N
gcc_gp1_clk 0 0 0 19200000 0 0 50000 N
ubi_mpt_clk_src 0 0 0 19200000 0 0 50000 N
gcc_ubi1_mpt_clk 0 0 0 19200000 0 0 50000 N
gcc_ubi0_mpt_clk 0 0 0 19200000 0 0 50000 N
nss_ubi1_clk_src 0 0 0 19200000 0 0 50000 N
nss_ubi1_div_clk_src 0 0 0 19200000 0 0 50000 Y
gcc_ubi1_core_clk 0 0 0 19200000 0 0 50000 N
nss_ubi0_clk_src 0 0 0 19200000 0 0 50000 N
nss_ubi0_div_clk_src 0 0 0 19200000 0 0 50000 Y
gcc_ubi0_core_clk 0 0 0 19200000 0 0 50000 N
nss_ce_clk_src 0 0 0 19200000 0 0 50000 N
gcc_ubi1_ahb_clk 0 0 0 19200000 0 0 50000 N
gcc_ubi0_ahb_clk 0 0 0 19200000 0 0 50000 N
gcc_nssnoc_ubi1_ahb_clk 0 0 0 19200000 0 0 50000 N
gcc_nssnoc_ubi0_ahb_clk 0 0 0 19200000 0 0 50000 N
gcc_nssnoc_ce_axi_clk 0 0 0 19200000 0 0 50000 N
gcc_nssnoc_ce_apb_clk 0 0 0 19200000 0 0 50000 N
gcc_nss_csr_clk 0 0 0 19200000 0 0 50000 N
gcc_nss_ce_axi_clk 0 0 0 19200000 0 0 50000 N
gcc_nss_ce_apb_clk 0 0 0 19200000 0 0 50000 N
gcc_xo_clk_src 5 5 0 19200000 0 0 50000 Y
gcc_uniphy2_sys_clk 1 1 0 19200000 0 0 50000 Y
gcc_uniphy1_sys_clk 1 1 0 19200000 0 0 50000 Y
gcc_uniphy0_sys_clk 1 1 0 19200000 0 0 50000 Y
gcc_cmn_12gpll_sys_clk 1 1 0 19200000 0 0 50000 Y
gcc_nssnoc_qosgen_ref_clk 0 0 0 19200000 0 0 50000 N
gcc_xo_div4_clk_src 0 0 0 4800000 0 0 50000 Y
gcc_nssnoc_timeout_ref_clk 0 0 0 4800000 0 0 50000 N
usb1_mock_utmi_clk_src 1 1 0 19200000 0 0 50000 Y
gcc_usb1_mock_utmi_clk 1 1 0 19200000 0 0 50000 Y
usb1_aux_clk_src 1 1 0 19200000 0 0 50000 Y
gcc_usb1_aux_clk 1 1 0 19200000 0 0 50000 Y
usb0_mock_utmi_clk_src 1 1 0 19200000 0 0 50000 Y
gcc_usb0_mock_utmi_clk 1 1 0 19200000 0 0 50000 Y
usb0_aux_clk_src 1 1 0 19200000 0 0 50000 Y
gcc_usb0_aux_clk 1 1 0 19200000 0 0 50000 Y
sdcc2_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_sdcc2_apps_clk 0 0 0 19200000 0 0 50000 N
pcie1_aux_clk_src 1 1 0 19200000 0 0 50000 Y
gcc_pcie1_aux_clk 2 2 0 19200000 0 0 50000 Y
pcie1_axi_clk_src 3 3 0 19200000 0 0 50000 Y
gcc_sys_noc_pcie1_axi_clk 1 1 0 19200000 0 0 50000 Y
gcc_pcie1_axi_s_clk 1 1 0 19200000 0 0 50000 Y
gcc_pcie1_axi_m_clk 1 1 0 19200000 0 0 50000 Y
pcie0_aux_clk_src 1 1 0 19200000 0 0 50000 Y
gcc_pcie0_aux_clk 1 1 0 19200000 0 0 50000 Y
pcie0_axi_clk_src 4 4 0 19200000 0 0 50000 Y
gcc_pcie0_axi_s_bridge_clk 1 1 0 19200000 0 0 50000 Y
gcc_sys_noc_pcie0_axi_clk 1 1 0 19200000 0 0 50000 Y
gcc_pcie0_axi_s_clk 1 1 0 19200000 0 0 50000 Y
gcc_pcie0_axi_m_clk 1 1 0 19200000 0 0 50000 Y
nss_crypto_pll_main 1 1 0 1190400000 0 0 50000 Y
nss_crypto_pll 1 1 0 595200000 0 0 50000 Y
nss_crypto_clk_src 1 1 0 595200000 0 0 50000 Y
gcc_nssnoc_crypto_clk 0 0 0 595200000 0 0 50000 N
gcc_nss_crypto_clk 1 1 0 595200000 0 0 50000 Y
ubi32_pll_main 0 0 0 1497600000 0 0 50000 N
ubi32_pll 0 0 0 1497600000 0 0 50000 Y
gpll6_main 1 1 0 1080000000 0 0 50000 Y
gpll6 0 0 0 1080000000 0 0 50000 Y
sdcc1_ice_core_clk_src 0 0 0 308571428 0 0 50000 N
gcc_sdcc1_ice_core_clk 0 0 0 308571428 0 0 50000 N
gpll6_out_main_div2 0 0 0 540000000 0 0 50000 Y
gpll4_main 1 1 0 1200000000 0 0 50000 Y
gpll4 0 0 0 1200000000 0 0 50000 Y
gpll2_main 1 1 0 1152000000 0 0 50000 Y
gpll2 0 0 0 1152000000 0 0 50000 Y
sdcc1_apps_clk_src 0 0 0 384000000 0 0 50000 N
gcc_sdcc1_apps_clk 0 0 0 384000000 0 0 50000 N
blsp1_uart6_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_blsp1_uart6_apps_clk 0 0 0 19200000 0 0 50000 N
blsp1_uart4_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_blsp1_uart4_apps_clk 0 0 0 19200000 0 0 50000 N
blsp1_uart3_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_blsp1_uart3_apps_clk 0 0 0 19200000 0 0 50000 N
blsp1_uart2_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_blsp1_uart2_apps_clk 0 0 0 19200000 0 0 50000 N
blsp1_uart1_apps_clk_src 0 0 0 19200000 0 0 50000 N
gcc_blsp1_uart1_apps_clk 0 0 0 19200000 0 0 50000 N
gpll0_main 1 1 0 800000000 0 0 50000 Y
gpll0_out_main_div2 0 0 0 400000000 0 0 50000 Y
blsp1_qup5_spi_apps_clk_src 0 0 0 12500000 0 0 50000 N
gcc_blsp1_qup5_spi_apps_clk 0 0 0 12500000 0 0 50000 N
gpll0 8 8 0 800000000 0 0 50000 Y
usb1_master_clk_src 2 2 0 133333333 0 0 50000 Y
gcc_usb1_master_clk 1 1 0 133333333 0 0 50000 Y
gcc_sys_noc_usb1_axi_clk 1 1 0 133333333 0 0 50000 Y
usb0_master_clk_src 2 2 0 133333333 0 0 50000 Y
gcc_usb0_master_clk 1 1 0 133333333 0 0 50000 Y
gcc_sys_noc_usb0_axi_clk 1 1 0 133333333 0 0 50000 Y
crypto_clk_src 1 1 0 160000000 0 0 50000 Y
gcc_crypto_clk 1 1 0 160000000 0 0 50000 Y
nss_imem_clk_src 1 1 0 400000000 0 0 50000 Y
gcc_nss_imem_clk 1 1 0 400000000 0 0 50000 Y
system_noc_bfdcd_clk_src 2 2 0 266666666 0 0 50000 Y
system_noc_clk_src 1 1 0 266666666 0 0 50000 Y
gcc_nssnoc_snoc_clk 1 1 0 266666666 0 0 50000 Y
pcnoc_bfdcd_clk_src 2 2 0 100000000 0 0 50000 Y
pcnoc_clk_src 13 14 0 100000000 0 0 50000 Y
gcc_crypto_axi_clk 1 1 0 100000000 0 0 50000 Y
gcc_crypto_ahb_clk 1 2 0 100000000 0 0 50000 Y
gcc_uniphy2_ahb_clk 1 1 0 100000000 0 0 50000 Y
gcc_uniphy1_ahb_clk 1 1 0 100000000 0 0 50000 Y
gcc_uniphy0_ahb_clk 1 1 0 100000000 0 0 50000 Y
gcc_mdio_ahb_clk 2 2 0 100000000 0 0 50000 Y
gcc_cmn_12gpll_ahb_clk 1 1 0 100000000 0 0 50000 Y
gcc_nss_cfg_clk 0 0 0 100000000 0 0 50000 N
gcc_sdcc2_ahb_clk 0 0 0 100000000 0 0 50000 N
gcc_sdcc1_ahb_clk 0 0 0 100000000 0 0 50000 N
gcc_usb1_phy_cfg_ahb_clk 2 2 0 100000000 0 0 50000 Y
gcc_usb0_phy_cfg_ahb_clk 2 2 0 100000000 0 0 50000 Y
gcc_pcie1_ahb_clk 2 2 0 100000000 0 0 50000 Y
gcc_pcie0_ahb_clk 1 1 0 100000000 0 0 50000 Y
gcc_qpic_clk 0 0 0 100000000 0 0 50000 N
gcc_qpic_ahb_clk 0 1 0 100000000 0 0 50000 N
gcc_prng_ahb_clk 1 1 0 100000000 0 0 50000 Y
gcc_blsp1_ahb_clk 4 5 0 100000000 0 0 50000 N
blsp1_uart5_apps_clk_src 1 1 0 3686400 0 0 50003 Y
gcc_blsp1_uart5_apps_clk 3 3 0 3686400 0 0 50000 Y
blsp1_qup6_spi_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup6_spi_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup6_i2c_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup6_i2c_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup5_i2c_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup5_i2c_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup4_spi_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup4_spi_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup4_i2c_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup4_i2c_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup3_spi_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup3_spi_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup3_i2c_apps_clk_src 1 1 0 50000000 0 0 50000 Y
gcc_blsp1_qup3_i2c_apps_clk 1 1 0 50000000 0 0 50000 Y
blsp1_qup2_spi_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup2_spi_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup2_i2c_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup2_i2c_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup1_spi_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup1_spi_apps_clk 0 0 0 50000000 0 0 50000 N
blsp1_qup1_i2c_apps_clk_src 0 0 0 50000000 0 0 50000 N
gcc_blsp1_qup1_i2c_apps_clk 0 0 0 50000000 0 0 50000 N
sleep_clk 2 2 0 32768 0 0 50000 Y
gcc_sleep_clk_src 3 3 0 32768 0 0 50000 Y
gcc_usb1_sleep_clk 1 1 0 32768 0 0 50000 Y
gcc_usb0_sleep_clk 1 1 0 32768 0 0 50000 Y
its dp5_syn node in DTS - not sure if that answers your question
@robimarko , if it expects 10GBase-R and RTL sees it this way from it's side, i guess we should
have in dp5_syn node something to tell the same, kinda like
compatible = "ethernet-phy-ieee802.3-c49";
but i can't find right compatible anywhere in the docs
Update: or should I change phy-mode = "sgmii"; to phy-mode = "10gbase-r"; for dp5_syn?
Well, phy-mode is irrelevant for NSS-DP as its ignoring it, what is set in the OEM DTS?
dp5 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <0x05>;
reg = <0x3a003000 0x3fff>;
qcom,mactype = <0x01>;
local-mac-address = [00 00 00 00 00 00];
phy-mode = "sgmii";
};
i see that magical port_mac_sel = "QGMAC_PORT"; in another DTS:
&mdio {
qca8081: ethernet-phy@28 {
compatible = "ethernet-phy-id004d.d101";
reg = <28>;
reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
};
...
&switch {
status = "okay";
....
qcom,port_phyinfo {
....
port@5 {
port_id = <6>;
phy_address = <28>;
port_mac_sel = "QGMAC_PORT";
};
};
}
Hey folks, I was just trying to SSH into my CR1000A and came across this lovely thread, and you guys are really smart. Anyways I'm not trying to re-image my device and use it with Verizon as my ISP, I was just trying to see if I can have some more control/adjust it to my liking. So this may be a stupid question, but it appears the default image accepts SSH connections at 4577
ssh 192.168.1.1 -p 4577
kex_exchange_identification: Connection closed by remote host
But how would I go about dumping what the authorized_keys are or adding an authorized key, looks like it only accepts key-based auth. Tried a few command injections in the webUI as suggested earlier, but the input validation is spot on
QGMAC_PORT is just used for 2.5G ports, not for 10G
look up this thread on how to craft special backup config to jailbreak
any docs/code where i could deep dive to see how to make it work as 10G?
trying to add compatible causes crash dump
rtl9301: ethernet-phy@f {
compatible = "ethernet-phy-ieee802.3-c45"; // crashes
reg = <0x0f>;
};
[ 5.418451] Call trace:
[ 5.425560] phy_attached_print+0x28/0x1b0
[ 5.427819] phy_attached_info+0x14/0x20
[ 5.431985] nss_dp_adjust_link+0x53c/0x6c0 [qca_nss_dp]
Its honestly hard to guess as we did not have a case like this at all so far.
But you cannot fake it as a PHY since then you will actually try using the C45 generic PHY driver and that will fail miserably on any call.
Docs are non-existant
what about the code? any schema/yaml? What should I look for in OEM dts?
Also, RTL9301 seems to be at least somewhat initialized right from the boot: dp5 (lan)
RX counter is increased with every ping from any of 3 ethernet ports. And it shows that it leans MACs, and all packets are set to forward to CPU port by default. So this device might be even good enough to be added to OpenWRT once this dp5 config issue is resolved.
p.s. even the MoCA shows itself on one of RTL9301 ports as connected 2.5G device
Well, code is there in SSDK and NSS-DP, there is no schema for it.
what are the links for both? i'm still new in all this
Check out the OpenWrt makefiles for both, you will also see the downstream patches we carry
Ok, will do. I'm looking at this example.
Seems like 'phy-connection-type = "10gbase-r";' is the way to define it. Are you saying it's also ignored on this platform?
Yes, driver is looking at the switch_mac_mode properties to set the MAC mode, it doesn't care about anything else.
Ok, thanks. That info will limit my research. Curious, will it ever change to use standard approach?
Unless somebody really makes and effort then nope
And I guess qcom,mactype like below
dp1 {
device_type = "network";
compatible = "qcom,nss-dp";
qcom,id = <1>;
reg = <0x3a001000 0x200>;
qcom,mactype = <0>;
local-mac-address = [000000000000];
};
Is also not working?
I dont get what you are asking here