I was taking about kernel option only. I don't think I need BusyBox applet, right?
ok, I think I made some progress: usrApp starts on openWrt! 
it did need the dev/mem device and it does talk to /dev/spiXXXXX device too (confirmed by strace)
root@OpenWrt:/mnt# ./usrApp
RTK User Space SDK Initialize
RTCORE Driver Module Initialize
IOAL init
IOAL init
Log init
Hardware-profile probe (RTL9303_8XGE)
Hardware-profile init
IOAL init
IOAL init
RTK Driver Module Initialize
MAC probe (unit 0)
Chip 9303 (found)
MAC init (unit 0)
PHY probe (unit 0)
Chip Construct (unit 0)
Chip Construct
Disable PHY Polling
PHY Reset
MAC Construct
Turn Off Serdes
Serdes Construct
PHY Construct
Turn On Serdes
Mac_Polling_PHY Config
Enable PHY Polling
Misc
PHY init (unit 0)
Mgmt_dev init (unit 0)
unit=0,sds=3 cali success.
failed to connect to ubus
Start to run Diag Shell....
RTK.0> sh: /sbin/exec-dir: not found
unexpected switch port:27, link status:1
sh: /sbin/exec-dir: not found
and running the sys dump hwp all gives similar result as on oem firmware (but starts throwing a lot of noise at the end)
RTK.0> sys dump hwp all
Profile Information (67D678):
Profile-Name: RTL9303_8XGE
Profile-ID: 9300015
Profile-ID-Type: 0
CPU Type: External
SW Desc IDX: 0
Slave Interrupt Pin: 255
Chip count: 1
Cascade Mode: No
unit 0, 9303(1) (cpu)
swcore support: 1
swcore-CPU Interface(1:normal, 2:SPI, 3: PCIe): 2
nic support: 1
port count: 6
macId: 8,20,24,25,27,28,
CpuMacId: 28 (attr)
Ether cnt: 5, macId(m/M): 8/27 msk:0x0b100100 0x00000000 (A)
Uplink cnt: 3, macId(m/M):24/27 msk:0x0b000000 0x00000000 (A)
2_5GE cnt: 3, macId(m/M): 0/25 msk:0x03100000 0x00000000 (E)
XGE cnt: 2, macId(m/M): 8/27 msk:0x08000100 0x00000000 (E)
Copper cnt: 4, macId(m/M): 8/25 msk:0x03100100 0x00000000 (M)
Serdes cnt: 1, macId(m/M):27/27 msk:0x08000000 0x00000000 (M)
port: 8, phyIdx0
port:20, phyIdx1
port:24, phyIdx2
port:25, phyIdx3
port:27, phyIdx255
port:28, phyIdx255
PHY Count:4
type:25(CUST5 ) port:1 baseMac:8
type:19(RTL8226B ) port:1 baseMac:20
type:19(RTL8226B ) port:1 baseMac:24
type:24(CUST4 ) port:1 baseMac:25
PHY[0]: chipID 25, baseMacId 8, phy_max 1
PHY[1]: chipID 19, baseMacId 20, phy_max 1
PHY[2]: chipID 19, baseMacId 24, phy_max 1
PHY[3]: chipID 24, baseMacId 25, phy_max 1
unitMapStruct[0].pUnitInfo:9034a038,parsed_info=9034a020,swDescp=67d6d8
unitMapStruct[1].pUnitInfo:820088,parsed_info=0,swDescp=0
unitMapStruct[2].pUnitInfo:820088,parsed_info=0,swDescp=0
unitMapStruct[3].pUnitInfo:820088,parsed_info=0,swDescp=0
unitMapStruct[4].pUnitInfo:820088,parsed_info=0,swDescp=0
unitMapStruct[5].pUnitInfo:820088,parsed_info=0,swDescp=0
unitMapStruct[6].pUnitInfo:820088,parsed_info=0,swDescp=0
unitMapStruct[7].pUnitInfo:820088,parsed_info=0,swDescp=0
unitMapStruct[8].pUnitInfo:820088,parsed_info=0,swDescp=0
unitMapStruct[9].pUnitInfo:820088,parsed_info=0,swDescp=0
unitMapStruct[10].pUnitInfo:820088,parsed_info=0,swDescp=0
unitMapStruct[11].pUnitInfo:820088,parsed_info=0,swDescp=0
unitMapStruct[12].pUnitInfo:820088,parsed_info=0,swDescp=0
unitMapStruct[13].pUnitInfo:820088,parsed_info=0,swDescp=0
unitMapStruct[14].pUnitInfo:820088,parsed_info=0,swDescp=0
unitMapStruct[15].pUnitInfo:820088,parsed_info=0,swDescp=0
(&parsedInfoEmpty.unitInfo[EMPTY]=820088)
info->hwp=RTL9303_8XGE(67d678)
info->hwp_localUnitCnt=1
info->hwp_embeddedCpuUnitId=0
info->hwp_cascade_mode=0
info->hwp_cascadeSlaveUnitID=0
info->hwp->swDescp[0]=67d6d8
info->hwp->swDescp[1]=0
info->hwp->swDescp[2]=0
info->unitInfo[0].hwp_chip_id=93030000
info->unitInfo[0].hwp_chip_revision=1
info->unitInfo[0].hwp_chip_family_id=93000000
info->unitInfo[0].hwp_maxMacId=28
info->unitInfo[0].hwp_minMacId=8
info->unitInfo[0].hwp_macID2PortDescp:
p[0]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[1]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[2]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[3]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[4]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[5]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[6]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[7]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[8]=67d6ec,mac_id=8,phyIdx=0,sdsIdx=0,smi=2,phy_addr=0,attr=1,eth=8,medi=1,
p[9]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[10]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[11]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[12]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[13]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[14]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[15]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[16]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[17]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[18]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[19]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[20]=67d6fc,mac_id=20,phyIdx=1,sdsIdx=1,smi=0,phy_addr=7,attr=1,eth=4,medi=1,
p[21]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[22]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[23]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[24]=67d70c,mac_id=24,phyIdx=2,sdsIdx=2,smi=1,phy_addr=3,attr=3,eth=4,medi=1,
p[25]=67d71c,mac_id=25,phyIdx=3,sdsIdx=3,smi=0,phy_addr=15,attr=3,eth=4,medi=1,
p[26]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[27]=67d72c,mac_id=27,phyIdx=255,sdsIdx=4,smi=255,phy_addr=255,attr=3,eth=8,medi=8,
p[28]=67d73c,mac_id=28,phyIdx=255,sdsIdx=255,smi=255,phy_addr=255,attr=8,eth=255,medi=255,
p[29]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[30]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[31]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[32]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[33]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[34]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[35]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[36]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[37]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[38]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[39]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[40]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[41]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[42]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[43]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[44]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[45]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[46]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[47]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[48]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[49]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[50]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[51]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[52]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[53]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[54]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[55]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[56]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[57]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[58]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[59]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[60]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[61]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[62]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
p[63]=822148,mac_id=0,phyIdx=0,sdsIdx=0,smi=0,phy_addr=0,attr=0,eth=0,medi=0,
info->unitInfo[0].hwp_macID2SerdesID:
p[0]=255,p[1]=255,p[2]=255,p[3]=255,p[4]=255,p[5]=255,p[6]=255,p[7]=255,p[8]=3,p[9]=255,p[10]=255,p[11]=255,p[12]=255,p[13]=255,p[14]=255,p[15]=255,p[16]=255,p[17]=255,p[18]=255,p[19]=255,p[20]=5,p[21]=255,p[22]=255,p[23]=255,p[24]=6,p[25]=7,p[26]=255,p[27]=9,p[28]=255,p[29]=255,p[30]=255,p[31]=255,p[32]=255,p[33]=255,p[34]=255,p[35]=255,p[36]=255,p[37]=255,p[38]=255,p[39]=255,p[40]=255,p[41]=255,p[42]=255,p[43]=255,p[44]=255,p[45]=255,p[46]=255,p[47]=255,p[48]=255,p[49]=255,p[50]=255,p[51]=255,p[52]=255,p[53]=255,p[54]=255,p[55]=255,p[56]=255,p[57]=255,p[58]=255,p[59]=255,p[60]=255,p[61]=255,p[62]=255,p[63]=255,
info->unitInfo[0].hwp_portCpuMacId=28
Ether : count=5, max=27, min=8
Uplink : count=3, max=27, min=24
Cascade: count=0, max=0, min=64
Fe : count=0, max=0, min=64
Ge : count=0, max=0, min=64
Xge : count=2, max=27, min=8
SXge : count=0, max=0, min=64
Copper : count=4, max=25, min=8
Fiber : count=0, max=0, min=64
Combo : count=0, max=0, min=64
Serdes : count=1, max=27, min=27
info->unitInfo[0].hwp_sdsID2phyType:
SDS 3 PHY:25
SDS 5 PHY:19
SDS 6 PHY:19
SDS 7 PHY:24
SDS 9 PHY:20
info->unitInfo[0].hwp_sdsID2MacID:
s[3]=8,s[5]=20,s[6]=24,s[7]=25,s[9]=27,
info->unitInfo[0].hwp_attriPortMask:
attr[0]=b100100
attr[0]=0
attr[1]=b000000
attr[1]=0
attr[2]=0
attr[2]=0
attr[3]=10000000
attr[3]=0
attr[4]=0
attr[4]=0
info->unitInfo[0].hwp_ethTypePortMask:
eth[0]=0
eth[0]=0
eth[1]=0
eth[1]=0
eth[2]=3100000
eth[2]=0
eth[3]=8000100
eth[3]=0
eth[4]=0
eth[4]=0
info->unitInfo[0].hwp_mediumPortMask:
med[0]=3100100
med[0]=0
med[1]=0
med[1]=0
med[2]=0
med[2]=0
med[3]=8000000
med[3]=0
info->unitInfo[0].hwp_allPortMask=1b100100
info->unitInfo[0].hwp_allPortMask=0
info->unitInfo[0].hwp_macID2phyAddr:
p[0]=255,p[1]=255,p[2]=255,p[3]=255,p[4]=255,p[5]=255,p[6]=255,p[7]=255,p[8]=0,p[9]=255,p[10]=255,p[11]=255,p[12]=255,p[13]=255,p[14]=255,p[15]=255,p[16]=255,p[17]=255,p[18]=255,p[19]=255,p[20]=7,p[21]=255,p[22]=255,p[23]=255,p[24]=3,p[25]=15,p[26]=255,p[27]=255,p[28]=255,p[29]=255,p[30]=255,p[31]=255,p[32]=255,p[33]=255,p[34]=255,p[35]=255,p[36]=255,p[37]=255,p[38]=255,p[39]=255,p[40]=255,p[41]=255,p[42]=255,p[43]=255,p[44]=255,p[45]=255,p[46]=255,p[47]=255,p[48]=255,p[49]=255,p[50]=255,p[51]=255,p[52]=255,p[53]=255,p[54]=255,p[55]=255,p[56]=255,p[57]=255,p[58]=255,p[59]=255,p[60]=255,p[61]=255,p[62]=255,p[63]=255,
info->unitInfo[0].hwp_macID2phyType:
p[0]=27,p[1]=27,p[2]=27,p[3]=27,p[4]=27,p[5]=27,p[6]=27,p[7]=27,p[8]=25,p[9]=27,p[10]=27,p[11]=27,p[12]=27,p[13]=27,p[14]=27,p[15]=27,p[16]=27,p[17]=27,p[18]=27,p[19]=27,p[20]=19,p[21]=27,p[22]=27,p[23]=27,p[24]=19,p[25]=24,p[26]=27,p[27]=20,p[28]=20,p[29]=27,p[30]=27,p[31]=27,p[32]=27,p[33]=27,p[34]=27,p[35]=27,p[36]=27,p[37]=27,p[38]=27,p[39]=27,p[40]=27,p[41]=27,p[42]=27,p[43]=27,p[44]=27,p[45]=27,p[46]=27,p[47]=27,p[48]=27,p[49]=27,p[50]=27,p[51]=27,p[52]=27,p[53]=27,p[54]=27,p[55]=27,p[56]=27,p[57]=27,p[58]=27,p[59]=27,p[60]=27,p[61]=27,p[62]=27,p[63]=27,
info->unitInfo[0].hwp_sdsID2SerdesDescp:
sds[0]=820068,sds[1]=820068,sds[2]=820068,sds[3]=67daed,sds[4]=820068,sds[5]=67daef,sds[6]=67daf1,sds[7]=67daf3,sds[8]=820068,sds[9]=67daf5,sds[10]=820068,sds[11]=820068,sds[12]=820068,sds[13]=820068,sds[14]=820068,sds[15]=820068,sds[16]=820068,sds[17]=820068,sds[18]=820068,sds[19]=820068,sds[20]=820068,sds[21]=820068,sds[22]=820068,sds[23]=820068,
info->unitInfo[0].hwp_phyBaseMacID:
p[0]=255,p[1]=255,p[2]=255,p[3]=255,p[4]=255,p[5]=255,p[6]=255,p[7]=255,p[8]=8,p[9]=255,p[10]=255,p[11]=255,p[12]=255,p[13]=255,p[14]=255,p[15]=255,p[16]=255,p[17]=255,p[18]=255,p[19]=255,p[20]=20,p[21]=255,p[22]=255,p[23]=255,p[24]=24,p[25]=25,p[26]=255,p[27]=27,p[28]=28,p[29]=255,p[30]=255,p[31]=255,p[32]=255,p[33]=255,p[34]=255,p[35]=255,p[36]=255,p[37]=255,p[38]=255,p[39]=255,p[40]=255,p[41]=255,p[42]=255,p[43]=255,p[44]=255,p[45]=255,p[46]=255,p[47]=255,p[48]=255,p[49]=255,p[50]=255,p[51]=255,p[52]=255,p[53]=255,p[54]=255,p[55]=255,p[56]=255,p[57]=255,p[58]=255,p[59]=255,p[60]=255,p[61]=255,p[62]=255,p[63]=255,
info->unitInfo[0].hwp_ledNum:
p[0]=0,p[1]=0,p[2]=0,p[3]=0,p[4]=0,p[5]=0,p[6]=0,p[7]=0,p[8]=2,p[9]=0,p[10]=0,p[11]=0,p[12]=0,p[13]=0,p[14]=0,p[15]=0,p[16]=0,p[17]=0,p[18]=0,p[19]=0,p[20]=2,p[21]=0,p[22]=0,p[23]=0,p[24]=2,p[25]=2,p[26]=0,p[27]=2,p[28]=255,p[29]=0,p[30]=0,p[31]=0,p[32]=0,p[33]=0,p[34]=0,p[35]=0,p[36]=0,p[37]=0,p[38]=0,p[39]=0,p[40]=0,p[41]=0,p[42]=0,p[43]=0,p[44]=0,p[45]=0,p[46]=0,p[47]=0,p[48]=0,p[49]=0,p[50]=0,p[51]=0,p[52]=0,p[53]=0,p[54]=0,p[55]=0,p[56]=0,p[57]=0,p[58]=0,p[59]=0,p[60]=0,p[61]=0,p[62]=0,p[63]=0,
info->unitInfo[0].hwp_multiSdsPortSdsmask:
info->unitInfo[0].hwp_multiSdsBaseSds:
info->unitInfo[0].hwp_macID2SCDescp:
info->unitInfo[0].hwp_scBaseMacID:
info->unitInfo[0].swDescp=67d6d8
info->unitInfo[0].parsed_info=9034a020I did have same output if I remember correctly, I just removed them because it was too long. At this point, we can just load the commands with usrAPP to bring up the switch interface?
I guess we now can. Could you pls collect all the command oem firmware sends?
Ideally we would need to trim it down to the absolute minimum till @olliver does his magic.
Meanwhile I'm trying to capture spi communication via strace so we can replay it if needed.
@olliver do you happen to know why usrApp needs /dev/mem? OEM dts has a lot of reserved ranges which i copied to my DTS
On a side note. @robimarko, why do we not use DMA in OpenWrt?
OEM has this
reserved-memory {
#address-cells = <0x02>;
#size-cells = <0x02>;
ranges;
.....
dma_pool0@54800000 {
compatible = "shared-dma-pool";
no-map;
reg = <0x00 0x54800000 0x00 0x1800000>;
linux,phandle = <0x2d>;
phandle = <0x2d>;
};
};
which, when added to DTS enables DMA pool
[ 0.000000] Reserved memory: created DMA memory pool at 0x0000000054800000, size 24 MiB
[ 0.000000] OF: reserved mem: initialized node dma_pool0@54800000, compatible id shared-dma-pool
and OEM uses it here
pci@20000000 {
compatible = "qcom,pcie-ipq807x";
.....
pcie0_rp {
reg = <0x00 0x00 0x00 0x00 0x00>;
status = "ok";
qcom,mhi@0 {
reg = <0x00 0x00 0x00 0x00 0x00>;
qrtr_instance_id = <0x20>;
#address-cells = <0x02>;
#size-cells = <0x02>;
memory-region = <0x2d>;
};
};
};
Should I do the same?
some more progress, i guess: packets are registering on lan. ping is not working
root@OpenWrt:/# ifconfig
lan Link encap:Ethernet HWaddr 5A:E8:CD:DC:84:DE
inet addr:192.168.1.1 Bcast:192.168.1.255 Mask:255.255.255.0
UP BROADCAST MULTICAST MTU:1500 Metric:1
RX packets:761 errors:0 dropped:0 overruns:0 frame:0
TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:48706 (47.5 KiB) TX bytes:0 (0.0 B)
Base address:0x3000
should be this(/etc/init.d/rtl-9303), I think you can just run it to push commands:
#!/bin/sh /etc/rc.common
START=20
DIAG_FIFO=/tmp/rtl9303_diag.fifo
. /usr/sbin/qos/qos_defs.sh
set_static_l2_table_entry()
{
lan_mac=`uci get hal.system.mac_address_eth`
if [ "$lan_mac" != "" ]; then
# untag
echo "l2-table add mac-ucast 1 $lan_mac port 27" > $DIAG_FIFO
echo "l2-table set mac-ucast 1 $lan_mac port 27 static" > $DIAG_FIFO
# vlan id 10
echo "l2-table add mac-ucast 10 $lan_mac port 27" > $DIAG_FIFO
echo "l2-table set mac-ucast 10 $lan_mac port 27 static" > $DIAG_FIFO
# vlan id 20
echo "l2-table add mac-ucast 20 $lan_mac port 27" > $DIAG_FIFO
echo "l2-table set mac-ucast 20 $lan_mac port 27 static" > $DIAG_FIFO
# vlan id 30
echo "l2-table add mac-ucast 30 $lan_mac port 27" > $DIAG_FIFO
echo "l2-table set mac-ucast 30 $lan_mac port 27 static" > $DIAG_FIFO
echo "l2-table set port-move sttc-port-move learn state enable" > $DIAG_FIFO
echo "l2-table set port-move sttc-port-move action drop" > $DIAG_FIFO
fi
}
enable_eee_mode()
{
echo "eee set port 8 state enable" > $DIAG_FIFO
echo "eee set port 20 state enable" > $DIAG_FIFO
echo "eee set port 24 state enable" > $DIAG_FIFO
echo "eee set port 25 state enable" > $DIAG_FIFO
echo "eee set port 27 state enable" > $DIAG_FIFO
}
set_ether_led(){
#10G Lan LED
echo "port set phy-mmd-reg port 8 mmd-addr 0x1E mmd-reg 0xc430 data 0xC0C0" > /tmp/rtl9303_diag.fifo
echo "port set phy-mmd-reg port 8 mmd-addr 0x1E mmd-reg 0xc431 data 0x20" > /tmp/rtl9303_diag.fifo
#2.5G Lan LED
echo "port set phy-mmd-reg port 20 mmd-addr 0x1F mmd-reg 0xd032 data 0x24" > /tmp/rtl9303_diag.fifo
echo "port set phy-mmd-reg port 20 mmd-addr 0x1F mmd-reg 0xd034 data 0x3" > /tmp/rtl9303_diag.fifo
echo "port set phy-mmd-reg port 24 mmd-addr 0x1F mmd-reg 0xd032 data 0x24" > /tmp/rtl9303_diag.fifo
echo "port set phy-mmd-reg port 24 mmd-addr 0x1F mmd-reg 0xd034 data 0x3" > /tmp/rtl9303_diag.fifo
}
boot() {
mkfifo $DIAG_FIFO
tail -f $DIAG_FIFO | /usr/bin/usrApp&
sleep 2
echo "port set port all state disable" > $DIAG_FIFO
# Clean up vlan table and l2 table for caching
# echo "vlan destroy all restore-default-vlan" > $DIAG_FIFO
echo "l2-table del all" > $DIAG_FIFO
sleep 2
# Create vlan-table vid is 1 for untag
# vid 0 will untag in ingress, then need to use acl command to tag vid 0
util_ethernet_cli createvlan 0
util_ethernet_cli setvlan 0 member all
util_ethernet_cli setvlan 0 untag-port 27
util_ethernet_cli setvlan 1 member all
util_ethernet_cli setvlan 1 untag-port all
util_ethernet_cli setvlanpvidinnerport 1
util_ethernet_cli setpvidmode untag-only
# Guest wifi
util_ethernet_cli createvlan 10
util_ethernet_cli setvlan 10 member all
# Zenreach AP
util_ethernet_cli createvlan 20
util_ethernet_cli setvlan 20 member all
# IoT wifi
util_ethernet_cli createvlan 30
util_ethernet_cli setvlan 30 member all
#switch internal proirity to queue
util_ethernet_cli set_internal_pri_to_queue 0 1 1 0 2 2 3 3 4 4 5 5 6 6 7 7
#Strict
util_ethernet_cli set_scheduler sp
#acl filter vlan 10
#acl set pbit 1, dscp 8 and internal priority 1
util_ethernet_cli set_acl_rule entry $GUEST_ENTRY_BASE vid 10 pbit_action 1 dscp_action 8 queue 1
set_static_l2_table_entry
enable_eee_mode
echo "port set port all state enable" > $DIAG_FIFO
set_ether_led
}
That is curious. I wonder how that is connected, as I haven't seen any PCIe pins on the swcore.
Sure we do 
I would be able to compile u-boot from scratch without blobs if we didn't.
btw, needing devmem should not be any relevance to the switch chip, as with devmem you'd be accessing the ARM cpu. The question is still 'what is it trying to do there'. You can hack /dev/mem maybe and output whatever registers its trying to write, and figure out why it's doing that. Usually because some nasty hackery.
Because ath11k will allocate memory itself, no need to pass it a memory region
Understood. Do we need other reserve-memory nodes ported from OEM dts?
Also, why does uboot not patch the Mac address in dts from ethaddr variable? I have alias set to ethernet0 and ethernet1
Not really, what would additional reserved-memory nodes be used for?
U-boot isn't always used to set MAC-s, I would check the U-boot env for MAC-s or you are going to have to use userspace helpers since NVMEM doesn't work on eMMC
the OEM dts has those mem-related entries:
/memreserve/ 0x000000004a3e8000 0x0000000000015000;
/ {
memory {
device_type = "memory";
reg = <0x00 0x40000000 0x00 0x80000000>;
};
reserved-memory {
#address-cells = <0x02>;
#size-cells = <0x02>;
ranges;
nss@40000000 {
no-map;
reg = <0x00 0x40000000 0x00 0x1000000>;
};
tzapp@4a400000 {
no-map;
reg = <0x00 0x4a400000 0x00 0x200000>;
};
uboot@4a600000 {
no-map;
reg = <0x00 0x4a600000 0x00 0x400000>;
};
sbl@4aa00000 {
no-map;
reg = <0x00 0x4aa00000 0x00 0x100000>;
};
smem@4ab00000 {
no-map;
reg = <0x00 0x4ab00000 0x00 0x100000>;
linux,phandle = <0x1b>;
phandle = <0x1b>;
};
tz@4ac00000 {
no-map;
reg = <0x00 0x4ac00000 0x00 0x400000>;
};
wcnss@4b000000 {
no-map;
reg = <0x00 0x4b000000 0x00 0x5f00000>;
linux,phandle = <0x12>;
phandle = <0x12>;
};
q6_etr_dump@50f00000 {
no-map;
reg = <0x00 0x50f00000 0x00 0x100000>;
linux,phandle = <0x13>;
phandle = <0x13>;
};
m3_dump@51000000 {
no-map;
reg = <0x00 0x51000000 0x00 0x100000>;
};
qcn9000_pcie0@51100000 {
no-map;
reg = <0x00 0x51100000 0x00 0x3700000>;
};
dma_pool0@54800000 {
compatible = "shared-dma-pool";
no-map;
reg = <0x00 0x54800000 0x00 0x1800000>;
linux,phandle = <0x2d>;
phandle = <0x2d>;
};
};
i also see in logs that uboot patches machid. How can I check if it can be used to patch MAC addresses?
it has both ethaddr and baseMac variables properly set
They seem to just be preallocating memory for QCN as well, no point in doing that as ath11k can just request the memory and it will be allocated.
If it is configured to update MAC-s then just having aliases is enough,
found this:
RTK.0> switch get sdk-version
SDK version : 3.6.2.56
OS version : Linux 3.18.24
Compiler version : GCC 4.8.5
C Library version : uClibc-0.9.33.2 with NPTL
does it mean we can load openwrt on it ? 
also this: its not 9301 after all?
RTK.0> debug get chip
Chip ID : 9303
Family ID : 9300
IFF there's RAM and Flash connected to the RTL. Which I doubt. I think the sdk-version just shows you what was used to build the binary, and they use the same sdk for full-blown switches and just the app, with just a different interface.
Also, rtl9303 or rtl9301 doesn't matter, they are virtually identical. The difference beeing the bandwith/SDS-ports it has.
Is the 2.4Ghz works ok on your testing openwrt version? I have problem on verizon firmware that 2.4Ghz keep turning off after I added couple cameras to my network and have seen other people reported that as well.
Any timeline of the beta openwrt release? Thank you!
I never tested wifi that deep yet. We are not even alpha ready. Pending steps as of today:
- Make rtl9301 work both ways (RX works, TX doesn't)
- Add userspace logic to setup MACs from env variables
- Finish generation of sysupgrade scripts.
- Flash 1st version to the MMC (here we would need @meisterlone's help, at least initially)
- Integrate the userspace RTL utility into the image
- Test all connectivity for stability
- 2nd AQR 10G port - ?
- MoCA - ?
This would make 'good enough' alpha community build
Then we would need to wait for/help testing real rtl3901 driver from @olliver. This seems to be 200 patches (many years) away 
1 Like
ok. thanks.
on another note: dp5 port receives packets from RTL9301 but nothing is getting sent. Could it be the problem on how dp5 port is configured from ARM side? I'm finding some bits of info about those ports have VLANs defined right in the DTS?
this it how it is in OEM.
switch_lan_bmp = <0x3e>;
switch_wan_bmp = <0x40>;
switch_mac_mode = <0x00>;
switch_mac_mode1 = <0x0e>;
switch_mac_mode2 = <0x0d>;
bm_tick_mode = <0x00>;
tm_tick_mode = <0x00>;
switch_lan_bmp = <0x3e>; is not working in openwrt - i had to set to proper 0x20 value
trying to find some docs on what those modes should be? RTL reports that it's CPU port is 10G fiber for some reason.
Can you check cat /sys/kernel/debug/clk/clk_summary ?
There are no preset VLAN-s, that was couple of generations ago.
If you mean MAC modes, well that is the actual MAC backbone link mode.
0 is PSGMII, 0xe is 10GBase-R and 0xd is USXGMII.
I am guessing its detecting it as fiber if its connected to UNIPHY1 which is running in 10GBaseR
This is from OEM firmware:
root@CR1000A:/# cat /sys/kernel/debug/clk/clk_summary
clock enable_cnt prepare_cnt rate accuracy phase
----------------------------------------------------------------------------------------
uniphy2_gcc_tx_clk 0 0 312500000 0 0
uniphy2_gcc_rx_clk 0 0 312500000 0 0
uniphy1_gcc_tx_clk 1 1 312500000 0 0
nss_port5_tx_clk_src 1 1 312500000 0 0
nss_port5_tx_div_clk_src 3 3 312500000 0 0
gcc_uniphy1_port5_tx_clk 1 1 312500000 0 0
gcc_uniphy0_port5_tx_clk 1 1 312500000 0 0
gcc_nss_port5_tx_clk 1 1 312500000 0 0
uniphy1_gcc_rx_clk 1 1 312500000 0 0
nss_port5_rx_clk_src 1 1 312500000 0 0
nss_port5_rx_div_clk_src 3 3 312500000 0 0
gcc_uniphy1_port5_rx_clk 1 1 312500000 0 0
gcc_uniphy0_port5_rx_clk 1 1 312500000 0 0
gcc_nss_port5_rx_clk 1 1 312500000 0 0
uniphy0_gcc_tx_clk 0 0 125000000 0 0
uniphy0_gcc_rx_clk 0 0 125000000 0 0
pcie20_phy0_pipe_clk 1 1 250000000 0 0
pcie0_pipe_clk_src 1 1 250000000 0 0
gcc_pcie0_pipe_clk 1 1 250000000 0 0
usb3phy_1_cc_pipe_clk 1 1 125000000 0 0
usb1_pipe_clk_src 1 1 125000000 0 0
gcc_usb1_pipe_clk 2 2 125000000 0 0
usb3phy_0_cc_pipe_clk 1 1 125000000 0 0
usb0_pipe_clk_src 1 1 125000000 0 0
gcc_usb0_pipe_clk 2 2 125000000 0 0
pcie20_phy1_pipe_clk 1 1 125000000 0 0
pcie1_pipe_clk_src 1 1 125000000 0 0
gcc_pcie1_pipe_clk 1 1 125000000 0 0
bias_pll_nss_noc_clk 1 1 416500000 0 0
nss_noc_bfdcd_clk_src 1 1 416500000 0 0
nss_noc_clk_src 6 6 416500000 0 0
gcc_ubi1_nc_axi_clk 1 1 416500000 0 0
gcc_ubi0_nc_axi_clk 1 1 416500000 0 0
gcc_ubi1_axi_clk 1 1 416500000 0 0
gcc_ubi0_axi_clk 1 1 416500000 0 0
gcc_nss_noc_clk 2 2 416500000 0 0
gcc_mem_noc_nss_axi_clk 2 2 416500000 0 0
bias_pll_cc_clk 1 1 300000000 0 0
nss_ppe_clk_src 16 16 300000000 0 0
gcc_port6_mac_clk 1 1 300000000 0 0
gcc_port5_mac_clk 1 1 300000000 0 0
gcc_port4_mac_clk 1 1 300000000 0 0
gcc_port3_mac_clk 1 1 300000000 0 0
gcc_port2_mac_clk 1 1 300000000 0 0
gcc_port1_mac_clk 1 1 300000000 0 0
gcc_nssnoc_ppe_clk 1 1 300000000 0 0
gcc_nssnoc_ppe_cfg_clk 1 1 300000000 0 0
gcc_nss_ppe_ipe_clk 1 1 300000000 0 0
gcc_nss_ppe_clk 1 1 300000000 0 0
gcc_nss_ppe_cfg_clk 1 1 300000000 0 0
gcc_nss_ppe_btq_clk 1 1 300000000 0 0
gcc_nss_edma_clk 1 1 300000000 0 0
gcc_nss_edma_cfg_clk 1 1 300000000 0 0
gcc_crypto_ppe_clk 1 1 300000000 0 0
nss_ppe_cdiv_clk_src 1 1 75000000 0 0
gcc_nss_ptp_ref_clk 2 2 75000000 0 0
xo 22 22 19200000 0 0
apss_pll_early 1 1 2208000000 0 0
apcs_alias0_clk_src 1 1 2208000000 0 0
apcs_alias0_core_clk 1 1 2208000000 0 0
apss_pll 0 0 2208000000 0 0
adss_pwm_clk_src 0 0 19200000 0 0
gcc_adss_pwm_clk 0 0 19200000 0 0
audio_pll_main 0 0 722534399 0 0
audio_pll 0 0 180633599 0 0
nss_crypto_pll_main 1 1 1200000000 0 0
nss_crypto_pll 1 1 600000000 0 0
nss_crypto_clk_src 2 2 600000000 0 0
gcc_nssnoc_crypto_clk 1 1 600000000 0 0
gcc_nss_crypto_clk 2 2 600000000 0 0
gpll2_main 2 2 1152000000 0 0
gpll2 1 1 1152000000 0 0
sdcc1_apps_clk_src 1 1 384000000 0 0
gcc_sdcc1_apps_clk 1 1 384000000 0 0
gpll4_main 1 1 1200000000 0 0
gpll4 3 3 1200000000 0 0
qdss_at_clk_src 1 1 240000000 0 0
gcc_qdss_at_clk 1 1 240000000 0 0
qdss_tsctr_clk_src 1 1 600000000 0 0
qdss_dap_sync_clk_src 1 1 150000000 0 0
gcc_qdss_dap_clk 9 9 150000000 0 0
apss_axi_clk_src 1 1 600000000 0 0
gcc_apss_axi_clk 1 1 600000000 0 0
gpll6_main 2 2 1080000000 0 0
gpll6_out_main_div2 0 0 540000000 0 0
gpll6 2 2 1080000000 0 0
usb1_mock_utmi_clk_src 1 1 20000000 0 0
gcc_usb1_mock_utmi_clk 1 1 20000000 0 0
usb0_mock_utmi_clk_src 1 1 20000000 0 0
gcc_usb0_mock_utmi_clk 1 1 20000000 0 0
ubi32_pll_main 1 1 1689600000 0 0
ubi32_pll 2 2 1689600000 0 0
nss_ubi1_clk_src 1 1 1689600000 0 0
nss_ubi1_div_clk_src 1 1 1689600000 0 0
gcc_ubi1_core_clk 5 5 1689600000 0 0
nss_ubi0_clk_src 1 1 1689600000 0 0
nss_ubi0_div_clk_src 1 1 1689600000 0 0
gcc_ubi0_core_clk 5 5 1689600000 0 0
gpll0_main 2 2 800000000 0 0
gpll0_out_main_div2 2 2 400000000 0 0
blsp1_qup5_spi_apps_clk_src 1 1 12500000 0 0
gcc_blsp1_qup5_spi_apps_clk 1 1 12500000 0 0
ubi_mpt_clk_src 2 2 25000000 0 0
gcc_ubi1_mpt_clk 1 1 25000000 0 0
gcc_ubi0_mpt_clk 1 1 25000000 0 0
gpll0 15 15 800000000 0 0
nss_ce_clk_src 9 9 200000000 0 0
gcc_ubi1_ahb_clk 1 1 200000000 0 0
gcc_ubi0_ahb_clk 1 1 200000000 0 0
gcc_nssnoc_ubi1_ahb_clk 1 1 200000000 0 0
gcc_nssnoc_ubi0_ahb_clk 1 1 200000000 0 0
gcc_nssnoc_ce_axi_clk 1 1 200000000 0 0
gcc_nssnoc_ce_apb_clk 1 1 200000000 0 0
gcc_nss_csr_clk 1 1 200000000 0 0
gcc_nss_ce_axi_clk 1 1 200000000 0 0
gcc_nss_ce_apb_clk 1 1 200000000 0 0
usb1_master_clk_src 3 3 133333333 0 0
gcc_sys_noc_usb1_axi_clk 1 1 133333333 0 0
gcc_snoc_bus_timeout3_ahb_clk 1 1 133333333 0 0
gcc_usb1_master_clk 1 1 133333333 0 0
usb0_master_clk_src 3 3 133333333 0 0
gcc_sys_noc_usb0_axi_clk 1 1 133333333 0 0
gcc_snoc_bus_timeout2_ahb_clk 1 1 133333333 0 0
gcc_usb0_master_clk 1 1 133333333 0 0
sdcc1_ice_core_clk_src 1 1 160000000 0 0
gcc_sdcc1_ice_core_clk 1 1 160000000 0 0
pcie1_axi_clk_src 3 3 200000000 0 0
gcc_sys_noc_pcie1_axi_clk 1 1 200000000 0 0
gcc_pcie1_axi_s_clk 1 1 200000000 0 0
gcc_pcie1_axi_m_clk 1 1 200000000 0 0
pcie0_rchng_clk_src 1 1 100000000 0 0
gcc_pcie0_rchng_clk 1 1 100000000 0 0
pcie0_axi_clk_src 4 4 200000000 0 0
gcc_pcie0_axi_s_bridge_clk 1 1 200000000 0 0
gcc_sys_noc_pcie0_axi_clk 1 1 200000000 0 0
gcc_pcie0_axi_s_clk 1 1 200000000 0 0
gcc_pcie0_axi_m_clk 1 1 200000000 0 0
system_noc_bfdcd_clk_src 2 2 266666666 0 0
system_noc_clk_src 1 1 266666666 0 0
gcc_nssnoc_snoc_clk 2 2 266666666 0 0
nss_imem_clk_src 1 1 400000000 0 0
gcc_nss_imem_clk 2 2 400000000 0 0
crypto_clk_src 1 1 160000000 0 0
gcc_crypto_clk 1 1 160000000 0 0
blsp1_uart5_apps_clk_src 1 1 3686400 0 0
gcc_blsp1_uart5_apps_clk 3 3 3686400 0 0
blsp1_qup6_spi_apps_clk_src 0 0 50000000 0 0
gcc_blsp1_qup6_spi_apps_clk 0 0 50000000 0 0
blsp1_qup6_i2c_apps_clk_src 0 0 50000000 0 0
gcc_blsp1_qup6_i2c_apps_clk 0 0 50000000 0 0
blsp1_qup5_i2c_apps_clk_src 0 0 50000000 0 0
gcc_blsp1_qup5_i2c_apps_clk 0 0 50000000 0 0
blsp1_qup4_spi_apps_clk_src 0 0 50000000 0 0
gcc_blsp1_qup4_spi_apps_clk 0 0 50000000 0 0
blsp1_qup4_i2c_apps_clk_src 0 0 50000000 0 0
gcc_blsp1_qup4_i2c_apps_clk 0 0 50000000 0 0
blsp1_qup3_spi_apps_clk_src 0 0 50000000 0 0
gcc_blsp1_qup3_spi_apps_clk 0 0 50000000 0 0
blsp1_qup3_i2c_apps_clk_src 1 1 50000000 0 0
gcc_blsp1_qup3_i2c_apps_clk 1 1 50000000 0 0
blsp1_qup2_spi_apps_clk_src 0 0 50000000 0 0
gcc_blsp1_qup2_spi_apps_clk 0 0 50000000 0 0
blsp1_qup2_i2c_apps_clk_src 0 0 50000000 0 0
gcc_blsp1_qup2_i2c_apps_clk 0 0 50000000 0 0
blsp1_qup1_spi_apps_clk_src 1 1 50000000 0 0
gcc_blsp1_qup1_spi_apps_clk 1 1 50000000 0 0
blsp1_qup1_i2c_apps_clk_src 0 0 50000000 0 0
gcc_blsp1_qup1_i2c_apps_clk 0 0 50000000 0 0
apss_ahb_clk_src 1 1 100000000 0 0
apss_ahb_postdiv_clk_src 1 1 100000000 0 0
gcc_apss_ahb_clk 1 1 100000000 0 0
pcnoc_bfdcd_clk_src 1 1 100000000 0 0
pcnoc_clk_src 15 16 100000000 0 0
gcc_dcc_clk 0 0 100000000 0 0
gcc_cmn_12gpll_ahb_clk 1 1 100000000 0 0
gcc_usb1_phy_cfg_ahb_clk 1 1 100000000 0 0
gcc_usb0_phy_cfg_ahb_clk 1 1 100000000 0 0
gcc_uniphy2_ahb_clk 1 1 100000000 0 0
gcc_uniphy1_ahb_clk 1 1 100000000 0 0
gcc_uniphy0_ahb_clk 1 1 100000000 0 0
gcc_sdcc2_ahb_clk 0 0 100000000 0 0
gcc_sdcc1_ahb_clk 1 1 100000000 0 0
gcc_qpic_clk 0 0 100000000 0 0
gcc_qpic_ahb_clk 0 1 100000000 0 0
gcc_prng_ahb_clk 1 1 100000000 0 0
gcc_pcie1_ahb_clk 1 1 100000000 0 0
gcc_pcie0_ahb_clk 1 1 100000000 0 0
gcc_nss_cfg_clk 1 1 100000000 0 0
gcc_mdio_ahb_clk 1 1 100000000 0 0
gcc_crypto_axi_clk 1 1 100000000 0 0
gcc_crypto_ahb_clk 1 2 100000000 0 0
gcc_blsp1_ahb_clk 6 7 100000000 0 0
gp3_clk_src 0 0 19200000 0 0
gcc_gp3_clk 0 0 19200000 0 0
gp2_clk_src 0 0 19200000 0 0
gcc_gp2_clk 0 0 19200000 0 0
gp1_clk_src 0 0 19200000 0 0
gcc_gp1_clk 0 0 19200000 0 0
usb1_aux_clk_src 1 1 19200000 0 0
gcc_usb1_aux_clk 2 2 19200000 0 0
usb0_aux_clk_src 1 1 19200000 0 0
gcc_usb0_aux_clk 2 2 19200000 0 0
sdcc2_apps_clk_src 0 0 19200000 0 0
gcc_sdcc2_apps_clk 0 0 19200000 0 0
pcie1_aux_clk_src 1 1 19200000 0 0
gcc_pcie1_aux_clk 1 1 19200000 0 0
pcie0_aux_clk_src 1 1 19200000 0 0
gcc_pcie0_aux_clk 1 1 19200000 0 0
blsp1_uart6_apps_clk_src 0 0 19200000 0 0
gcc_blsp1_uart6_apps_clk 0 0 19200000 0 0
blsp1_uart4_apps_clk_src 0 0 19200000 0 0
gcc_blsp1_uart4_apps_clk 0 0 19200000 0 0
blsp1_uart3_apps_clk_src 0 0 19200000 0 0
gcc_blsp1_uart3_apps_clk 0 0 19200000 0 0
blsp1_uart2_apps_clk_src 0 0 19200000 0 0
gcc_blsp1_uart2_apps_clk 0 0 19200000 0 0
blsp1_uart1_apps_clk_src 0 0 19200000 0 0
gcc_blsp1_uart1_apps_clk 0 0 19200000 0 0
nss_port6_tx_clk_src 1 1 19200000 0 0
nss_port6_tx_div_clk_src 2 2 19200000 0 0
gcc_uniphy2_port6_tx_clk 1 1 19200000 0 0
gcc_nss_port6_tx_clk 1 1 19200000 0 0
nss_port6_rx_clk_src 1 1 19200000 0 0
nss_port6_rx_div_clk_src 2 2 19200000 0 0
gcc_uniphy2_port6_rx_clk 1 1 19200000 0 0
gcc_nss_port6_rx_clk 1 1 19200000 0 0
nss_port4_tx_clk_src 1 1 19200000 0 0
nss_port4_tx_div_clk_src 2 2 19200000 0 0
gcc_uniphy0_port4_tx_clk 1 1 19200000 0 0
gcc_nss_port4_tx_clk 1 1 19200000 0 0
nss_port4_rx_clk_src 1 1 19200000 0 0
nss_port4_rx_div_clk_src 2 2 19200000 0 0
gcc_uniphy0_port4_rx_clk 1 1 19200000 0 0
gcc_nss_port4_rx_clk 1 1 19200000 0 0
nss_port3_tx_clk_src 1 1 19200000 0 0
nss_port3_tx_div_clk_src 2 2 19200000 0 0
gcc_uniphy0_port3_tx_clk 1 1 19200000 0 0
gcc_nss_port3_tx_clk 1 1 19200000 0 0
nss_port3_rx_clk_src 1 1 19200000 0 0
nss_port3_rx_div_clk_src 2 2 19200000 0 0
gcc_uniphy0_port3_rx_clk 1 1 19200000 0 0
gcc_nss_port3_rx_clk 1 1 19200000 0 0
nss_port2_tx_clk_src 1 1 19200000 0 0
nss_port2_tx_div_clk_src 2 2 19200000 0 0
gcc_uniphy0_port2_tx_clk 1 1 19200000 0 0
gcc_nss_port2_tx_clk 1 1 19200000 0 0
nss_port2_rx_clk_src 1 1 19200000 0 0
nss_port2_rx_div_clk_src 2 2 19200000 0 0
gcc_uniphy0_port2_rx_clk 1 1 19200000 0 0
gcc_nss_port2_rx_clk 1 1 19200000 0 0
nss_port1_tx_clk_src 1 1 19200000 0 0
nss_port1_tx_div_clk_src 2 2 19200000 0 0
gcc_uniphy0_port1_tx_clk 1 1 19200000 0 0
gcc_nss_port1_tx_clk 1 1 19200000 0 0
nss_port1_rx_clk_src 1 1 19200000 0 0
nss_port1_rx_div_clk_src 2 2 19200000 0 0
gcc_uniphy0_port1_rx_clk 1 1 19200000 0 0
gcc_nss_port1_rx_clk 1 1 19200000 0 0
gcc_xo_clk_src 7 7 19200000 0 0
gcc_cmn_12gpll_sys_clk 1 1 19200000 0 0
gcc_uniphy2_sys_clk 1 1 19200000 0 0
gcc_uniphy1_sys_clk 1 1 19200000 0 0
gcc_uniphy0_sys_clk 1 1 19200000 0 0
gcc_nssnoc_qosgen_ref_clk 1 1 19200000 0 0
gcc_xo_clk 1 1 19200000 0 0
gcc_xo_div4_clk_src 1 1 4800000 0 0
gcc_nssnoc_timeout_ref_clk 1 1 4800000 0 0
sleep_clk 2 2 32000 0 0
gcc_sleep_clk_src 3 3 32000 0 0
gcc_usb1_sleep_clk 1 1 32000 0 0
gcc_usb0_sleep_clk 1 1 32000 0 0