Adding OpenWrt support for Checkpoint Appliance

HI All.
I am new to the forum here.
I have obtained a new checkpoint firewall appliance that i Would like to run openwrt on.
image

After doing a bit of research,it seems i can on Kali on this device via deboot strap, which is great. See Here

I was wondering what the best way to get openwrt running on this device considering armhf hardware.
I also have shell access to the device.

I can provide board pictures as well if required.

Neither your post, nor the referenced guide about using chroots suggest what exact device you're talking about (the guide covers both amd64 and ARMv7) - and at least to the untrained eye, the picture isn't more revealing either. If you can add the the hardware specifications (CPU architecture, CPU, flash/ RAM, BIOS/ UEFI/ coreboot/ $locked_down_homegrown_firmware) beyond the mere model name, all the better.

…at least the guide doesn't help you with installing kali either, just setting up a chroot for it.

1 Like

OpenWrt has already been ported to the Check Point L-50. The L-61 device uses a Cavium CN7020 so support is possible. The L-71/L-72 devices which resemble your picture above appear to use an ARM processor, but I have been unable to confirm.

THanks for the replies guys.
The V-80 is the device i have.
It uses an arm processor.
I am trying to find out how I can capture more information from this device, the standard tools like dmidecode don't run on the device...

Here is some screenshots I have captured.


More details

Here is the boot log that might give some more hints.

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BootROM - 2.03

Starting CP-0 IOROM 1.07

Booting from eMMC 0 (0x2B)

Found valid image at boot postion 0x000

lNOTICE:  Starting binary extension
NOTICE:  SVC: DEV ID: 8040, FREQ Mode: 0x1
NOTICE:  SVC: AVS work point changed from 0x27 to 0x27
mv_ddr: mv_ddr-release-19.06.3-g??? (Nov 25 2019 - 04:25:14 PM)
mv_ddr: completed successfully
NOTICE:  Cold boot
lNOTICE:  Booting Trusted Firmware
NOTICE:  BL1: v1.5(debug): (Marvell-release-19.06.3)
NOTICE:  BL1: Built : 16:25:23, Nov 25 2019
NOTICE:  BL1: Booting BL2
lNOTICE:  BL2: v1.5(debug): (Marvell-release-19.06.3)
NOTICE:  BL2: Built : 16:25:27, Nov 25 2019
BL2: Initiating SCP_BL2 transfer to SCP
NOTICE:  SCP_BL2 contains 5 concatenated images
NOTICE:  Skipping MSS CP3 related image
NOTICE:  Skipping MSS CP2 related image
NOTICE:  Load image to CP1 MSS AP0
NOTICE:  Loading MSS image from addr. 0x40269f4 Size 0x1cd8 to MSS at 0xf4280000
NOTICE:  Done
NOTICE:  Load image to CP0 MSS AP0
NOTICE:  Loading MSS image from addr. 0x40286cc Size 0x1cd8 to MSS at 0xf2280000
NOTICE:  Done
NOTICE:  Load image to AP0 MSS
NOTICE:  Loading MSS image from addr. 0x402a3a4 Size 0x5420 to MSS at 0xf0580000
NOTICE:  Done
NOTICE:  SCP Image doesn't contain PM firmware
NOTICE:  BL1: Booting BL31
lNOTICE:  MSS PM is not supported in this build
NOTICE:  BL31: v1.5(debug): (Marvell-release-19.06.3)
NOTICE:  BL31: Built : 16:25:34, Nov 25 2019
l

U-Boot 2018.03-release-19.06.3 (Nov 25 2019 - 16:24:37 +0200)

Model: Marvell Armada 8040 Sunspear V1_dvt1 Software 0.0.4
SoC: Armada8040-A2; AP806-A1; 2xCP110-A2
Clock:  CPU     2000 [MHz]
	DDR     1050 [MHz]
	FABRIC  1050 [MHz]
	MSS     200  [MHz]
LLC Enabled (Exclusive Mode)
DRAM:  2 GiB

 === V1 board_init (Check Point version: 992000112) ===
Comphy chip #0:
Comphy-0: UNCONNECTED  
Comphy-1: USB3_HOST0   
Comphy-2: SFI0          10.3125 Gbps
Comphy-3: USB3_HOST1   
Comphy-4: UNCONNECTED  
Comphy-5: PEX2         
Comphy chip #1:
Comphy-0: UNCONNECTED  
Comphy-1: SGMII2        1.25 Gbps 
Comphy-2: UNCONNECTED  
Comphy-3: UNCONNECTED  
Comphy-4: PEX1         
Comphy-5: UNCONNECTED  
UTMI PHY 0 initialized to USB Host0
UTMI PHY 1 initialized to USB Host1
PCIE-0: Link up (Gen2-x1, Bus0)
PCIE-2: Link up (Gen2-x1, Bus2)
MMC:   sdhci@6e0000: 0, sdhci@780000: 1
Loading Environment from MMC... OK
Model: Marvell Armada 8040 Sunspear V1_dvt1 Software 0.0.4
Net:   incorrect phy mode
eth0: mvpp2-0incorrect phy mode
, eth-1: mvpp2-1, eth1: mvpp2-2, eth2: mvpp2-4, eth3: mvpp2-5 [PRIME]
config_88E1512_init++
incorrect phy mode
m88e151x_config_leds(mvpp2-4)
config_88E1512_init++
incorrect phy mode
m88e151x_config_leds(mvpp2-5)
set_88E6393_mdio:miiphy_get_current_dev=cp0-mdio
cp_set_board_vars started
switch to partitions #0, OK
mmc1(part 0) is current device

MMC read: dev # 1, block # 4096, count 512 ... 512 blocks read: OK
blob magic: a5a51234
blob crc: 2dbda77b
Verifying CRC for settings area... Done
cp_set_board_vars: dsl_annex is env_set to nothing
Saving Environment to MMC... Writing to MMC(1)... OK

************ Hit 'Ctrl + C' for boot menu ************

 2  1  1  0 
USB0:   Register 2000120 NbrPorts 2
Starting the controller
USB XHCI 1.00
USB1:   Register 2000120 NbrPorts 2
Starting the controller
USB XHCI 1.00
scanning bus 0 for devices... 1 USB Device(s) found
scanning bus 1 for devices... cannot reset port 2!?
1 USB Device(s) found
       scanning usb for storage devices... 0 Storage Device(s) found

USB storage device not found .. 

Trying to load file "u-boot*v1.bin" from SD Card flash drive using FAT FS
Card did not respond to voltage select!
** Bad device mmc 0 **

Trying to load file "fw1*.img" from SD Card flash drive using FAT FS
Card did not respond to voltage select!
** Bad device mmc 0 **

Trying to load file "*.cfg" from SD Card flash drive using FAT FS
Card did not respond to voltage select!
** Bad device mmc 0 **
switch to partitions #0, OK
mmc1(part 0) is current device

MMC read: dev # 1, block # 1595393, count 98304 ... 98304 blocks read: OK

MMC read: dev # 1, block # 1693696, count 2048 ... 2048 blocks read: OK
## Flattened Device Tree blob at 06f00000
   Booting using the fdt blob at 0x6f00000
   Using Device Tree in place at 0000000006f00000, end 0000000006f0c8ef

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 4.14.76-release-1.3.0 (builder@lnx70bcccmp2) (gcc version 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701] (Linaro GCC 7.3-2018.05)) #1 SMP Wed Nov 25 14:16:57 IST 2020
[    0.000000] Boot CPU: AArch64 Processor [410fd081]
[    0.000000] Machine model: Marvell Armada 8040 Sunspear V1_dvt Software 0.0.3
[    0.000000] earlycon: uart8250 at MMIO32 0x00000000f0512000 (options '')
[    0.000000] bootconsole [uart8250] enabled
[    0.662094] xenon-sdhci f06e0000.sdhci: AP SDHC is running in slow mode
[    0.754140] armada-cp110-pinctrl f2440000.system-controller:pinctrl: missing marvell,function in node cp0-gpio-mpp-oem-pins

INIT: version 2.88 booting


Booting e[1mCheck Point RD-6281-Ae[0m User Space...
.================
INIT: Entering runlevel: 3

......................................................................................
System Started...

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That's the same processor as the Macchiatobin which is supported, so there is a reasonable chance to get support. I'd start with trying to get the GPL source from Check Point.

Very unlikely Checkpoint will give the source, is there another way ?
Jtag ?

Checkpoint would be legally required to provide the source.

Technically you may be able to get it working without source access, but that would involve considerably more efforts - and given that this target isn't the most common one, it's not going to be a walk in the park to begin with (the interesting question would be which wireless chipset they picked, hopefully not Marvell/ NXP...).

Apart from this, the device is exotic, but high-end with plenty of performance.

When requesting source files.
What files am I expecting to get back ?

If its Armada 8040 then its super supportable and powerful, especially due to number of SERDES programmable lanes.

I am assuming there are other hardware that use the Armada 8040 ?
Hence I am not going to be the first person to come across this platform.

Yes, there is HW both in OpenWrt and upstream that uses the same SoC

You should be able to request source from Check Point by emailing gpl-source@checkpoint.com You should supply the device Model and Serial Number with the request.

OK I have sent them an email will wait fore the reply.
I also had another checkpoint device land on my desk .


BootROM - 2.03

Starting CP-0 IOROM 1.07

Booting from eMMC 0 (0x2B)

Found valid image at boot postion 0x000

lNOTICE:  Starting binary extension
NOTICE:  SVC: DEV ID: 7040, FREQ Mode: 0x1a
NOTICE:  SVC: AVS work point changed from 0x21 to 0x1f
mv_ddr: mv_ddr-release-19.06.3-g??? (Nov 25 2019 - 04:24:03 PM)
mv_ddr: completed successfully
NOTICE:  Cold boot
lNOTICE:  Booting Trusted Firmware
NOTICE:  BL1: v1.5(debug): (Marvell-release-19.06.3)
NOTICE:  BL1: Built : 16:24:12, Nov 25 2019
NOTICE:  BL1: Booting BL2
lNOTICE:  BL2: v1.5(debug): (Marvell-release-19.06.3)
NOTICE:  BL2: Built : 16:24:17, Nov 25 2019
BL2: Initiating SCP_BL2 transfer to SCP
NOTICE:  SCP_BL2 contains 5 concatenated images
NOTICE:  Skipping MSS CP3 related image
NOTICE:  Skipping MSS CP2 related image
NOTICE:  Skipping MSS CP1 related image
NOTICE:  Load image to CP0 MSS AP0
NOTICE:  Loading MSS image from addr. 0x40286cc Size 0x1cd8 to MSS at 0xf2280000
NOTICE:  Done
NOTICE:  Load image to AP0 MSS
NOTICE:  Loading MSS image from addr. 0x402a3a4 Size 0x5420 to MSS at 0xf0580000
NOTICE:  Done
NOTICE:  BL1: Booting BL31
lNOTICE:  BL31: v1.5(debug): (Marvell-release-19.06.3)
NOTICE:  BL31: Built : 16:24:25, Nov 25 2019
l

U-Boot 2018.03-release-19.06.3 (Nov 25 2019 - 16:23:24 +0200)

Model: Marvell Armada 7040 Sunspear V0 Software 0.0.6
SoC: Armada7040-A2; AP806-A1; CP110-A2
Clock:  CPU     1400 [MHz]
	DDR     800  [MHz]
	FABRIC  800  [MHz]
	MSS     200  [MHz]
LLC Enabled (Exclusive Mode)
DRAM:  2 GiB

 === V0 board_init (Check Point version: 992000112) ===
Comphy chip #0:
Comphy-0: SGMII1        1.25 Gbps 
Comphy-1: USB3_HOST0   
Comphy-2: SGMII0        1.25 Gbps 
Comphy-3: UNCONNECTED  
Comphy-4: UNCONNECTED  
Comphy-5: PEX2         
UTMI PHY 0 initialized to USB Host0
PCIE-0: Link down
MMC:   sdhci@6e0000: 0, sdhci@780000: 1
Loading Environment from MMC... OK
Model: Marvell Armada 7040 Sunspear V0 Software 0.0.6
Net:   eth0: mvpp2-0, eth1: mvpp2-1 [PRIME]
config_88E1512_init++
m88e151x_config_leds(mvpp2-1)
cp_set_board_vars started
switch to partitions #0, OK
mmc1(part 0) is current device

MMC read: dev # 1, block # 4096, count 512 ... 512 blocks read: OK
blob magic: a5a51234
blob crc: ed6dc562
Verifying CRC for settings area... Done
cp_set_board_vars: dsl_annex is env_set to nothing
Saving Environment to MMC... Writing to MMC(1)... OK

************ Hit 'Ctrl + C' for boot menu ************

 2  1  1  0 
USB0:   Register 2000120 NbrPorts 2
Starting the controller
USB XHCI 1.00
scanning bus 0 for devices... 1 USB Device(s) found
       scanning usb for storage devices... 0 Storage Device(s) found

USB storage device not found .. 
switch to partitions #0, OK
mmc1(part 0) is current device

MMC read: dev # 1, block # 1595393, count 98304 ... 98304 blocks read: OK

MMC read: dev # 1, block # 1693696, count 2048 ... 2048 blocks read: OK
## Flattened Device Tree blob at 06f00000
   Booting using the fdt blob at 0x6f00000
   Using Device Tree in place at 0000000006f00000, end 0000000006f091fd

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 4.14.76-release-1.3.0 (builder@lnx70bcccmp1) (gcc version 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701] (Linaro GCC 7.3-2018.05)) #1 SMP Tue Aug 11 18:14:58 IDT 2020
[    0.000000] Boot CPU: AArch64 Processor [410fd081]
[    0.000000] Machine model: Marvell Armada 7040 Sunspear V0 Software 0.0.4
[    0.000000] earlycon: uart8250 at MMIO32 0x00000000f0512000 (options '')
[    0.000000] bootconsole [uart8250] enabled
[    0.342440] xenon-sdhci f06e0000.sdhci: AP SDHC is running in slow mode
[    1.433459] armada8k-pcie f2640000.pcie: phy link never came up
[    1.439418] armada8k-pcie f2640000.pcie: Link not up after reconfiguration

INIT: version 2.88 booting


Booting e[1mCheck Point RD-6281-Ae[0m User Space...
.================
INIT: Entering runlevel: 3


Once I get a reply back. Can you please briefly outline the process involved to get OpenWrt running.

There is no brief way, you'll have to develop the necessary changes on the source level.

exists, but that's just a rough start at best.