Stock Bootlog (most of it)
===================================================================
MT7621 stage1 code 10:33:55 (ASIC)
CPU=500000000 HZ BUS=166666666 HZ
==================================================================
Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x11100000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-1200Mhz ===
PLL3 FB_DL: 0x6, 1/0 = 522/502 19000000
PLL4 FB_DL: 0x14, 1/0 = 701/323 51000000
PLL2 FB_DL: 0x16, 1/0 = 745/279 59000000
do DDR setting..[01F40000]
Apply DDR3 Setting...(use customer AC)
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120
--------------------------------------------------------------------------------
0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0007:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0008:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0009:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000E:| 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
000F:| 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0
0010:| 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
0011:| 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0
0012:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0013:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
rank 0 coarse = 16
rank 0 fine = 40
B:| 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0
opt_dle value:9
DRAMC_R0DELDLY[018]=00002020
==================================================================
RX DQS perbit delay software calibration
==================================================================
1.0-15 bit dq delay value
==================================================================
bit| 0 1 2 3 4 5 6 7 8 9
--------------------------------------
0 | 8 7 9 9 7 7 7 6 7 7
10 | 10 9 10 11 8 10
--------------------------------------
==================================================================
2.dqs window
x=pass dqs delay value (min~max)center
y=0-7bit DQ of every group
input delay:DQS0 =32 DQS1 = 32
==================================================================
bit DQS0 bit DQS1
0 (1~60)30 8 (2~60)31
1 (1~61)31 9 (2~62)32
2 (2~62)32 10 (2~62)32
3 (1~59)30 11 (1~59)30
4 (1~60)30 12 (2~62)32
5 (2~62)32 13 (2~62)32
6 (1~61)31 14 (1~61)31
7 (1~62)31 15 (1~62)31
==================================================================
3.dq delay value last
==================================================================
bit| 0 1 2 3 4 5 6 7 8 9
--------------------------------------
0 | 10 8 9 11 9 7 8 7 8 7
10 | 10 11 10 11 9 11
==================================================================
==================================================================
TX perbyte calibration
==================================================================
DQS loop = 15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqsdly_pass[0]=15, finish count=1
dqs_perbyte_dly.last_dqsdly_pass[1]=15, finish count=2
DQ loop=15, cmp_err_1 = ffff0080
dqs_perbyte_dly.last_dqdly_pass[1]=15, finish count=1
DQ loop=14, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqdly_pass[0]=14, finish count=2
byte:0, (DQS,DQ)=(8,8)
byte:1, (DQS,DQ)=(8,8)
20,data:88
[EMI] DRAMC calibration passed
===================================================================
MT7621 stage1 code done
CPU=500000000 HZ BUS=166666666 HZ
===================================================================
U-Boot 1.1.3 (Jun 19 2017 - 13:43:21)
Board: Ralink APSoC DRAM: 128 MB
relocate_code Pointer at: 87fa4000
Config XHCI 40M PLL
flash manufacture id: c2, device id 20 18
find flash: MX25L12805D
*** Warning - bad CRC, using default environment
============================================
Ralink UBoot Version: 5.0.0.0
--------------------------------------------
ASIC MT7621A DualCore (MAC to MT7530 Mode)
DRAM_CONF_FROM: Auto-Detection
DRAM_TYPE: DDR3
DRAM bus: 16 bit
Xtal Mode=3 OCP Ratio=1/3
Flash component: SPI Flash
Date:Jun 19 2017 Time:13:43:21
============================================
icache: sets:256, ways:4, linesz:32 ,total:32768
dcache: sets:256, ways:4, linesz:32 ,total:32768
##### The CPU freq = 880 MHZ ####
estimate memory size =128 Mbytes
#Reset_MT7530
Please choose the operation:
1: Load system code to SDRAM via TFTP.
2: Load system code then write to Flash via TFTP.
3: Boot system code via Flash (default).
4: Entr boot command line interface.
7: Load Boot Loader code then write to Flash via Serial.
9: Load Boot Loader code then write to Flash via TFTP.
default: 3 0
3: System Boot system code via Flash.
## Booting image at bc050000 ...
Image Name: Linux Kernel Image
Image Type: MIPS Linux Kernel Image (lzma compressed)
Data Size: 6698280 Bytes = 6.4 MB
Load Address: 81001000
Entry Point: 8164b8b0
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK
No initrd
## Transferring control to Linux (at address 8164b8b0) ...
## Giving linux memsize in MB, 128
Starting kernel ...
LINUX started...
THIS IS ASIC
SDK 5.0.S.0
Linux version 3.10.14 (root@ubuntu12-64) (gcc version 4.6.3 (Buildroot 2012.11.1) ) #399 SMP Fri May 25 11:38:00 CST 2018
The CPU feqenuce set to 880 MHz
GCMP present
CPU0 revision is: 0001992f (MIPS 1004Kc)
Software DMA cache coherency
Determined physical RAM map:
memory: 08000000 @ 00000000 (usable)
Initrd not found or empty - disabling initrd
Zone ranges:
DMA [mem 0x00000000-0x00ffffff]
Normal [mem 0x01000000-0x07ffffff]
Movable zone start for each node
Early memory node ranges
node 0: [mem 0x00000000-0x07ffffff]
Detected 3 available secondary CPU(s)
Primary instruction cache 32kB, 4-way, VIPT, linesize 32 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
PERCPU: Embedded 7 pages/cpu @81da2000 s6784 r8192 d13696 u32768
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512
Kernel command line: console=ttyS1,57600n8 root=/dev/ram0
PID hash table entries: 512 (order: -1, 2048 bytes)
Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
Writing ErrCtl register=00040ee8
Readback ErrCtl register=00040ee8
Memory: 116888k/131072k available (6484k kernel code, 14184k reserved, 1953k data, 3588k init, 0k highmem)
Hierarchical RCU implementation.
NR_IRQS:128
console [ttyS1] enabled
Calibrating delay loop... 574.46 BogoMIPS (lpj=1148928)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
launch: starting cpu1
launch: cpu1 gone!
CPU1 revision is: 0001992f (MIPS 1004Kc)
Primary instruction cache 32kB, 4-way, VIPT, linesize 32 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
Synchronize counters for CPU 1: done.
launch: starting cpu2
launch: cpu2 gone!
CPU2 revision is: 0001992f (MIPS 1004Kc)
Primary instruction cache 32kB, 4-way, VIPT, linesize 32 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
Synchronize counters for CPU 2: done.
launch: starting cpu3
launch: cpu3 gone!
CPU3 revision is: 0001992f (MIPS 1004Kc)
Primary instruction cache 32kB, 4-way, VIPT, linesize 32 bytes.
Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
Synchronize counters for CPU 3: done.
Brought up 4 CPUs
devtmpfs: initialized
NET: Registered protocol family 16
release PCIe RST: RALINK_RSTCTRL = 7000000
PCIE PHY initialize
***** Xtal 40MHz *****
start MT7621 PCIe register access
RALINK_RSTCTRL = 7000000
RALINK_CLKCFG1 = 77ffeff8
*************** MT7621 PCIe RC mode *************
PCIE2 no card, disable it(RST&CLK)
pcie_link status = 0x3
RALINK_RSTCTRL= 3000000
*** Configure Device number setting of Virtual PCI-PCI bridge ***
RALINK_PCI_PCICFG_ADDR = 21007f2 -> 21007f2
PCIE0 enabled
PCIE1 enabled
interrupt enable status: 300000
Port 1 N_FTS = 1b105000
Port 0 N_FTS = 1b105000
config reg done
init_rt2880pci done
bio: create slab <bio-0> at 0
vgaarb: loaded
SCSI subsystem initialized
PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff]
pci_bus 0000:00: root bus resource [io 0x1e160000-0x1e16ffff]
pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
pci 0000:00:00.0: BAR 0: can't assign mem (size 0x80000000)
pci 0000:00:01.0: BAR 0: can't assign mem (size 0x80000000)
pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x600fffff]
pci 0000:00:01.0: BAR 8: assigned [mem 0x60100000-0x601fffff]
pci 0000:00:00.0: BAR 1: assigned [mem 0x60200000-0x6020ffff]
pci 0000:00:01.0: BAR 1: assigned [mem 0x60210000-0x6021ffff]
pci 0000:01:00.0: BAR 0: assigned [mem 0x60000000-0x600fffff 64bit]
pci 0000:00:00.0: PCI bridge to [bus 01]
pci 0000:00:00.0: bridge window [mem 0x60000000-0x600fffff]
pci 0000:02:00.0: BAR 0: assigned [mem 0x60100000-0x601fffff 64bit]
pci 0000:00:01.0: PCI bridge to [bus 02]
pci 0000:00:01.0: bridge window [mem 0x60100000-0x601fffff]
PCI: Enabling device 0000:00:00.0 (0004 -> 0006)
PCI: Enabling device 0000:00:01.0 (0004 -> 0006)
BAR0 at slot 0 = 0
bus=0x0, slot = 0x0
res[0]->start = 0
res[0]->end = 0
res[1]->start = 60200000
res[1]->end = 6020ffff
res[2]->start = 0
res[2]->end = 0
res[3]->start = 0
res[3]->end = 0
res[4]->start = 0
res[4]->end = 0
res[5]->start = 0
res[5]->end = 0
BAR0 at slot 1 = 0
bus=0x0, slot = 0x1
res[0]->start = 0
res[0]->end = 0
res[1]->start = 60210000
res[1]->end = 6021ffff
res[2]->start = 0
res[2]->end = 0
res[3]->start = 0
res[3]->end = 0
res[4]->start = 0
res[4]->end = 0
res[5]->start = 0
res[5]->end = 0
bus=0x1, slot = 0x0, irq=0x4
res[0]->start = 60000000
res[0]->end = 600fffff
res[1]->start = 0
res[1]->end = 0
res[2]->start = 0
res[2]->end = 0
res[3]->start = 0
res[3]->end = 0
res[4]->start = 0
res[4]->end = 0
res[5]->start = 0
res[5]->end = 0
bus=0x2, slot = 0x1, irq=0x18
res[0]->start = 60100000
res[0]->end = 601fffff
res[1]->start = 0
res[1]->end = 0
res[2]->start = 0
res[2]->end = 0
res[3]->start = 0
res[3]->end = 0
res[4]->start = 0
res[4]->end = 0
res[5]->start = 0
res[5]->end = 0
Switching to clocksource Ralink Systick timer
NET: Registered protocol family 2
Clockevents: could not switch to one-shot mode:
Clockevents: could not switch to one-shot mode:
MIPS is not functional.
MIPS is not functional.
Clockevents: could not switch to one-shot mode: MIPS is not functional.
Could not switch to high resolution mode on CPU 0
Could not switch to high resolution mode on CPU 2
Could not switch to high resolution mode on CPU 3
Clockevents: could not switch to one-shot mode: MIPS is not functional.
Could not switch to high resolution mode on CPU 1
TCP established hash table entries: 1024 (order: 1, 8192 bytes)
TCP bind hash table entries: 1024 (order: 1, 8192 bytes)
TCP: Hash tables configured (established 1024 bind 1024)
TCP: reno registered
UDP hash table entries: 256 (order: 1, 8192 bytes)
UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
NET: Registered protocol family 1
4 CPUs re-calibrate udelay(lpj = 1167360)
fuse init (API version 7.22)
msgmni has been set to 228
io scheduler noop registered (default)
reg_int_mask=0, INT_MASK= 0
HSDMA_init
hsdma_phy_tx_ring0 = 0x00c00000, hsdma_tx_ring0 = 0xa0c00000
hsdma_phy_rx_ring0 = 0x00c04000, hsdma_rx_ring0 = 0xa0c04000
TX_CTX_IDX0 = 0
TX_DTX_IDX0 = 0
RX_CRX_IDX0 = 3ff
RX_DRX_IDX0 = 0
set_fe_HSDMA_glo_cfg
HSDMA_GLO_CFG = 465
Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
serial8250: ttyS0 at MMIO 0x1e000d00 (irq = 27) is a 16550A
serial8250: ttyS1 at MMIO 0x1e000c00 (irq = 26) is a 16550A
Ralink gpio driver initialized
brd: module loaded
flash manufacture id: c2, device id 20 18
MX25L12805D(c2 2018c220) (16384 Kbytes)
mtd .name = raspi, .size = 0x01000000 (16M) .erasesize = 0x00010000 (64K) .numeraseregions = 0
Creating 5 MTD partitions on "raspi":
0x000000000000-0x000001000000 : "ALL"
0x000000000000-0x000000030000 : "Bootloader"
0x000000030000-0x000000040000 : "Config"
0x000000040000-0x000000050000 : "Factory"
0x000000050000-0x000001000000 : "Kernel"
PPP generic driver version 2.4.2
PPP BSD Compression module registered
PPP MPPE Compression module registered
NET: Registered protocol family 24
PPTP driver version 0.8.5
register mt_drv
=== pAd = c2181000, size = 4154432 ===
<-- RTMPAllocAdapterBlock, Status=0
pAd->PciHif.CSRBaseAddress =0xc2080000, csr_addr=0xc2080000!
RTMPInitPCIeDevice():device_id=0x7615
DriverOwn()::Try to Clear FW Own...
DriverOwn()::Success to clear FW Own
mt_pci_chip_cfg(): HWVer=0x8a10, FWVer=0x8a10, pAd->ChipID=0x7615
mt_pci_chip_cfg(): HIF_SYS_REV=0x76150001
RtmpChipOpsHook(492): Not support for HIF_MT yet! MACVersion=0x0
mt7615_init()-->
Use 1st iPAiLNA default bin.
Use 0st /etc_ro/wlan/MT7615E_EEPROM1.bin default bin.
<--mt7615_init()
ChipOpsMCUHook
cut_through_token_list_init(): TokenList inited done!id_head/tail=0/4096
cut_through_token_list_init(): 84a3c588,84a3c588
cut_through_token_list_init(): TokenList inited done!id_head/tail=0/4096
cut_through_token_list_init(): 84a3c598,84a3c598
<-- RTMPAllocTxRxRingMemory, Status=0
=== pAd = c2681000, size = 4154432 ===
<-- RTMPAllocAdapterBlock, Status=0
pAd->PciHif.CSRBaseAddress =0xc2580000, csr_addr=0xc2580000!
RTMPInitPCIeDevice():device_id=0x7615
DriverOwn()::Try to Clear FW Own...
DriverOwn()::Success to clear FW Own
mt_pci_chip_cfg(): HWVer=0x8a10, FWVer=0x8a10, pAd->ChipID=0x7615
mt_pci_chip_cfg(): HIF_SYS_REV=0x76150001
RtmpChipOpsHook(492): Not support for HIF_MT yet! MACVersion=0x0
mt7615_init()-->
Use 2nd iPAiLNA default bin.
Use 1st /etc_ro/wlan/MT7615E_EEPROM2.bin default bin.
<--mt7615_init()
ChipOpsMCUHook
cut_through_token_list_init(): TokenList inited done!id_head/tail=0/4096
cut_through_token_list_init(): 86015708,86015708
cut_through_token_list_init(): TokenList inited done!id_head/tail=0/4096
cut_through_token_list_init(): 86015718,86015718
<-- RTMPAllocTxRxRingMemory, Status=0
rdm_major = 253
GMAC1_MAC_ADRH -- : 0x00000002
GMAC1_MAC_ADRL -- : 0x72f14719
Ralink APSoC Ethernet Driver Initilization. v3.1 1024 rx/tx descriptors allocated, mtu = 1500!
GMAC1_MAC_ADRH -- : 0x00000002
GMAC1_MAC_ADRL -- : 0x72f14719
PROC INIT OK!
MTK MSDC device init.
msdc0 -> ================ <- msdc_set_mclk() : L<686> PID<swapper/0><0x1>
msdc0 -> !!! Set<400KHz> Source<50000KHz> -> sclk<390KHz> <- msdc_set_mclk() : L<687> PID<swapper/0><0x1>
msdc0 -> ================ <- msdc_set_mclk() : L<688> PID<swapper/0><0x1>
msdc0 -> ops_get_cd return<1> <- msdc_ops_get_cd() : L<2317> PID<kworker/u8:0><0x6>
mtk-sd: MediaTek MT6575 MSDC Driver
GACT probability on
msdc0 -> XXX MSDC_INT_SDIOIRQ <- msdc_irq() : L<2393>
msdc0 -> XXX CMD<52> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<52> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<8> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<5> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<5> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<5> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<5> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<55> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<55> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<55> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<55> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<1> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> set mclk to 0!!! <- msdc_set_mclk() : L<634> PID<kworker/u8:0><0x6>
msdc0 -> set mclk to 0!!! <- msdc_set_mclk() : L<634> PID<kworker/u8:0><0x6>
msdc0 -> ================ <- msdc_set_mclk() : L<686> PID<kworker/u8:0><0x6>
msdc0 -> !!! Set<300KHz> Source<50000KHz> -> sclk<297KHz> <- msdc_set_mclk() : L<687> PID<kworker/u8:0><0x6>
msdc0 -> ================ <- msdc_set_mclk() : L<688> PID<kworker/u8:0><0x6>
msdc0 -> XXX CMD<52> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<52> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<8> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<5> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<5> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<5> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<5> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<55> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<55> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<55> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<55> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<1> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> set mclk to 0!!! <- msdc_set_mclk() : L<634> PID<kworker/u8:0><0x6>
msdc0 -> set mclk to 0!!! <- msdc_set_mclk() : L<634> PID<kworker/u8:0><0x6>
msdc0 -> ================ <- msdc_set_mclk() : L<686> PID<kworker/u8:0><0x6>
msdc0 -> !!! Set<260KHz> Source<50000KHz> -> sclk<255KHz> <- msdc_set_mclk() : L<687> PID<kworker/u8:0><0x6>
msdc0 -> ================ <- msdc_set_mclk() : L<688> PID<kworker/u8:0><0x6>
msdc0 -> XXX CMD<52> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<52> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<8> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<5> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<5> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<5> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<5> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<55> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<55> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<55> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<55> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> XXX CMD<1> MSDC_INT_CMDTMO <- msdc_irq() : L<2461>
msdc0 -> set mclk to 0!!! <- msdc_set_mclk() : L<634> PID<kworker/u8:0><0x6>
Mirror/redirect action on
Failed to load ipt action
Simple TC action Loaded
netem: version 1.3
u32 classifier
Performance counters on
input device check on
Actions configured
Netfilter messages via NETLINK v0.30.
nfnl_acct: registering with nfnetlink.
nf_conntrack version 0.5.0 (1826 buckets, 7304 max)
ctnetlink v0.93: registering with nfnetlink.
xt_time: kernel timezone is -0000
IPVS: Registered protocols ()
IPVS: Connection hash table configured (size=4096, memory=32Kbytes)
IPVS: Creating netns size=776 id=0
IPVS: ipvs loaded.
gre: GRE over IPv4 demultiplexor driver
ip_tables: (C) 2000-2006 Netfilter Core Team
Type=Restricted Cone
ipt_CLUSTERIP: ClusterIP Version 0.8 loaded successfully
arp_tables: (C) 2002 David S. Miller
TCP: cubic registered
NET: Registered protocol family 10
sit: IPv6 over IPv4 tunneling driver
NET: Registered protocol family 17
Bridge firewalling registered
l2tp_core: L2TP core driver, V2.0
l2tp_ppp: PPPoL2TP kernel driver, V2.0
8021q: 802.1Q VLAN Support v1.8
Warning: unable to open an initial console.
Freeing unused kernel memory: 3588K (8183f000 - 81bc0000)
Algorithmics/MIPS FPU Emulator v1.5
Welcome to
__ ___ _____ _____ _ _______ ______ _____ _ ___
| \ / || ___|| __ \ | || __ ||__ __|| ___|| | / /
| ^ || |__ | | \ \| || | | | | | | |__ | |/ /
| | | || ___|| | | || || |__| | | | | ___|| \
| | | || |___ | |__/ /| || __ | | | | |___ | |\ \
|__| |___||_____||_____/ |_||_| |_| |_| |_____||_| \__\
= Everyday Genius =
Password for 'admin' changed
ifconfig: ioctl 0x8913 failed: No such device
rmmod: hw_nat: No such file or directory
##### disable 1st wireless interface #####
##### disable 2nd wireless interface #####
##### disable 3rd wireless interface #####
rmmod: mt_wifi: No such file or directory
insmod: mt_wifi.ko: module not found
DriverOwn()::Return since already in Driver Own...
APWdsInitialize():WdsEntry[0]
APWdsInitialize():WdsEntry[1]
APWdsInitialize():WdsEntry[2]
APWdsInitialize():WdsEntry[3]
[wifi_fwd_set_cb_num] band_cb_offset=33, recv_from_cb_offset=34
[Force Roam] => Force Roam Support = 0
multi-profile merge success, en:1,pf1_num:1,pf2_num:1,total:2
MacAddress1 = 00:00:00:00:00:00
E2pAccessMode=2
SSID[0]=AP_5G22222, EdcaIdx=0
SSID[1]=AP_2G1111, EdcaIdx=0
RTMPSetProfileParameters(): DBDC Mode=1
TriBandChGrp=1/0/0/0
cfg_mode=14
cfg_mode=14
wmode_band_equal(): Band Equal!
cfg_mode=9
cfg_mode=9
[TxPower] BAND0: 100, BAND1: 100
[SKUenable] BAND0: 0, BAND1: 0
[PERCENTAGEenable] BAND0: 1, BAND1: 1
[BFBACKOFFenable] BAND0: 0, BAND1: 0
CalCacheApply = 0
APEdca0
Valid=1
APAifsn[0]=3
APAifsn[1]=7
APAifsn[2]=1
APAifsn[3]=1
APEdca1
Valid=1
APAifsn[0]=3
APAifsn[1]=7
APAifsn[2]=1
APAifsn[3]=1
APEdca2
APEdca3
BSSAifsn[0]=3
BSSAifsn[1]=7
BSSAifsn[2]=2
BSSAifsn[3]=2
BSSAifsn[0]=3
BSSAifsn[1]=7
BSSAifsn[2]=2
BSSAifsn[3]=2
APSDCapable[0]=0
APSDCapable[1]=0
default ApCliAPSDCapable[0]=0
default ApCliAPSDCapable[1]=0
DfsZeroWait Support=0/0
DfsZeroWaitCacTime=255/255
[PMF]Set_PMFMFPC_Proc:: apidx=0, Desired MFPC=0
[PMF]Set_PMFMFPC_Proc:: apidx=1, Desired MFPC=0
[PMF]Set_PMFMFPR_Proc:: apidx=0, Desired MFPR=0
[PMF]Set_PMFMFPR_Proc:: apidx=1, Desired MFPR=0
[PMF]Set_PMFSHA256_Proc:: apidx=0, Desired PMFSHA256=0
[PMF]Set_PMFSHA256_Proc:: apidx=1, Desired PMFSHA256=0
cfg_mode=14
cfg_mode=9
rtmp_read_wds_from_file(): WDS Profile
APWdsInitialize():WdsEntry[0]
APWdsInitialize():WdsEntry[1]
APWdsInitialize():WdsEntry[2]
APWdsInitialize():WdsEntry[3]
WDS-Enable mode=0
AndesSendCmdMsg: Could not send in band command due to diablefRTMP_ADAPTER_MCU_SEND_IN_BAND_CMD
HT: WDEV[0] Ext Channel = ABOVE
HT: WDEV[1] Ext Channel = ABOVE
HT: greenap_cap = 0
ez_read_parms_from_file network_weight[NETWORK_WEIGHT_LEN - 1] 0
I/F(ra0) ForceRoamSupport=1
IcapMode = 0
WtcSetMaxStaNum: MaxStaNum:102, BssidNum:2, WdsNum:4, ApcliNum:2, MaxNumChipRept:16, MinMcastWcid:124
Top Init Done!
Use alloc_skb
RX[0] DESC a0c12000 size = 8192
RX[1] DESC a0c14000 size = 8192
Hif Init Done!
ctl->txq = c2572f98
ctl->rxq = c2572fa4
ctl->ackq = c2572fb0
ctl->kickq = c2572fbc
ctl->tx_doneq = c2572fc8
ctl->rx_doneq = c2572fd4
mt7615_fw_prepare():FW(8a10), HW(8a10), CHIPID(7615))
mt7615_fw_prepare(2718): MT7615_E3, USE E3 patch and ram code binary image
AndesMTLoadRomMethodFwDlRing(1035), cap->rom_patch_len(11102)
AndesRestartCheck: Current TOP_MISC2(0x1)
AndesRestartCheck: (TOP_MISC2 = 1), ready to continue...RET(0)
20170304015247a
platform =
ALPS
hw/sw version =
8a108a10
patch version =
00000010
Patch SEM Status=2
MtCmdPatchSemGet:(ret = 0)
Patch is not ready && get semaphore success, SemStatus(2)
EventGenericEventHandler: CMD Success
MtCmdAddressLenReq:(ret = 0)
MtCmdPatchFinishReq
EventGenericEventHandler: CMD Success
Send checksum req..
Patch SEM Status=3
MtCmdPatchSemGet:(ret = 0)
Release patch semaphore, SemStatus(3)
AndesMTEraseRomPatch
WfMcuHwInit: Before NICLoadFirmware, check IcapMode=0
AndesMTLoadFwMethodFwDlRing(809), cap->fw_len(462888)
Build Date:_201705090345
Build Date:_201705090345
AndesRestartCheck: Current TOP_MISC2(0x1)
AndesRestartCheck: (TOP_MISC2 = 1), ready to continue...RET(0)
EventGenericEventHandler: CMD Success
MtCmdAddressLenReq:(ret = 0)
EventGenericEventHandler: CMD Success
MtCmdAddressLenReq:(ret = 0)
MtCmdFwStartReq: override = 1, address = 540672
EventGenericEventHandler: CMD Success
Build Date:_201704122039
EventGenericEventHandler: CMD Success
MtCmdAddressLenReq:(ret = 0)
MtCmdFwStartReq: override = 4, address = 0
EventGenericEventHandler: CMD Success
WfMcuHwInit: NICLoadFirmware OK, Check IcapMode=0
MCU Init Done!
MtCmdSetRlmPorCal: (ret = 0)
efuse_probe: efuse = 10000212
RtmpChipOpsEepromHook::e2p_type=2, inf_Type=5
RtmpEepromGetDefault::e2p_dafault=1
RtmpChipOpsEepromHook: E2P type(2), E2pAccessMode = 2, E2P default = 1
NVM is FLASH mode. dev_idx [0] FLASH OFFSET [0x0]
NICReadEEPROMParameters: EEPROM 0x52 b300
NICReadEEPROMParameters: EEPROM 0x52 b300
Country Region from e2p = 101
mt7615_antenna_default_reset(): TxPath = 4, RxPath = 4
mt7615_antenna_default_reset(): DBDC 2G TxPath = 2, 2G RxPath = 2
mt7615_antenna_default_reset(): DBDC 5G TxPath = 2, 2G RxPath = 2
rtmp_read_txpwr_from_eeprom(233): Don't Support this now!
RTMPReadTxPwrPerRate(1381): Don't Support this now!
RcRadioInit(): DbdcMode=1, ConcurrentBand=2
RcRadioInit(): pRadioCtrl=84a3d450,Band=0,rfcap=1,channel=1,PhyMode=2 extCha=0xf
RcRadioInit(): pRadioCtrl=84a3d53c,Band=1,rfcap=2,channel=36,PhyMode=1 extCha=0xf
MtCmdSetDbdcCtrl:(ret = 0)
Band Rf: 1, Phy Mode: 2
Band Rf: 2, Phy Mode: 1
AntCfgInit(2770): Not support for HIF_MT yet!
MtSingleSkuLoadParam: RF_LOCKDOWN Feature OFF !!!
MtBfBackOffLoadTable: RF_LOCKDOWN Feature OFF !!!
EEPROM Init Done!
mt_mac_init()-->
mt_mac_pse_init(2752): Don't Support this now!
mt7615_init_mac_cr()-->
mt7615_init_mac_cr(): TMAC_TRCR0=0x82783c8c
mt7615_init_mac_cr(): TMAC_TRCR1=0x82783c8c
MtAsicSetMacMaxLen(1300): Not finish Yet!
<--mt_mac_init()
CmdRxHdrTransBLUpdateRsp::EventExtCmdResult.u4Status = 0x0
CmdRxHdrTransBLUpdateRsp::EventExtCmdResult.u4Status = 0x0
CmdRxHdrTransBLUpdateRsp::EventExtCmdResult.u4Status = 0x0
MAC Init Done!
MT7615BBPInit():BBP Initialization.....
Band 0: valid=1, isDBDC=0, Band=2, CBW=1, CentCh/PrimCh=1/1, prim_ch_idx=0, txStream=2
Band 1: valid=0, isDBDC=0, Band=0, CBW=0, CentCh/PrimCh=0/0, prim_ch_idx=0, txStream=0
MT7615BBPInit() todo
PHY Init Done!
tx_pwr_comp_init():NotSupportYet!
MtCmdSetMacTxRx:(ret = 0)
MtCmdSetMacTxRx:(ret = 0)
CountryCode(2.4G/5G)=5/7, RFIC=25, PHY mode(2.4G/5G)=2/49, support 18 channels
ApAutoChannelAtBootUp----------------->
ApAutoChannelAtBootUp: AutoChannelBootup = 0, AutoChannelFlag = 0
ApAutoChannelAtBootUp<-----------------
WifiSysOpen(), wdev idx = 0
wdev_attr_update(): wdevId0 = 00:02:72:f1:47:17
MtCmdSetDbdcCtrl:(ret = 0)
Current Channel is 40. DfsZeroWaitSupport=0
MtAsicSetChBusyStat(840): Not support for HIF_MT yet!
MtAsicSetChBusyStat(840): Not support for HIF_MT yet!
[PMF]APPMFInit:: apidx=0, MFPC=0, MFPR=0, SHA256=0
[PMF]WPAMakeRsnIeCap: RSNIE Capability MFPC=0, MFPR=0
[Force Roam] => Force Roam Support = 1
ez_allocate_or_update_non_ez_band:: add new band entry at index: 0
HcUpdatePhyMode(): Update PhyMode for all wdev for this band PhyMode:49,Channel=40
CountryCode(2.4G/5G)=5/7, RFIC=25, PHY mode(2.4G/5G)=2/49, support 18 channels
wtc_acquire_groupkey_wcid: Found a non-occupied wtbl_idx:127 for WDEV_TYPE:1
LinkToOmacIdx = 0, LinkToWdevType = 1
bssUpdateBmcMngRate (BSS_INFO_BROADCAST_INFO), CmdBssInfoBmcRate.u2BcTransmit= 8192, CmdBssInfoBmcRate.u2McTransmit = 8196
MtCmdSetDbdcCtrl:(ret = 0)
[RadarStateCheck]Set into RD_NORMAL_MODE
MtCmdTxPowerSKUCtrl: fgTxPowerSKUEn: 0, BandIdx: 1
MtCmdTxPowerPercentCtrl: fgTxPowerPercentEn: 1, BandIdx: 1
MtCmdTxBfBackoffCtrl: fgTxBFBackoffEn: 0, BandIdx: 1
mt7615_bbp_adjust():rf_bw=2, ext_ch=3, PrimCh=40, HT-CentCh=38, VHT-CentCh=42
mt7615_apply_cal_data() : eeprom 0x52 bit 1 is 0, do runtime cal , skip RX reload
mt7615_apply_cal_data() : eeprom 0x52 bit 0 is 0, do runtime cal , skip TX reload
MtCmdChannelSwitch: control_chl = 40,control_ch2=0, central_chl = 42 DBDCIdx= 1, Band= 0
BW = 2,TXStream = 2, RXStream = 2, scan(0)
ap_phy_rrm_init_byRf(): AP Set CentralFreq at 42(Prim=40, HT-CentCh=38, VHT-CentCh=42, BBP_BW=2)
[WrapDfsRadarDetectStart]: Band0Ch is 40[WrapDfsRadarDetectStart]: Band1Ch is 0LeadTimeForBcn, OmacIdx = 0, WDEV_WITH_BCN_ABILITY
MtAsicSetRalinkBurstMode(2605): Not support for HIF_MT yet!
MtAsicSetPiggyBack(777): Not support for HIF_MT yet!
MtAsicSetTxPreamble(2584): Not support for HIF_MT yet!
RTMPSetLEDStatus: before AndesLedEnhanceOP , status=1, LED_CMD=2!
AndesLedEnhanceOP: Success!
WifiFwdSet::disabled=0
ap_ftkd> Initialize FT KDP Module...
Main bssid = 00:02:72:f1:47:17
AsicRadioOnOffCtrl(): DbdcIdx=1 RadioOn
MtCmdSetMacTxRx:(ret = 0)
MtCmdSetMacTxRx:(ret = 0)
MCS Set = ff ff 00 00 01
<==== mt_wifi_init, Status=0
MtCmdEDCCACtrl: BandIdx: 0, EDCCACtrl: 1
MtCmdEDCCACtrl: BandIdx: 1, EDCCACtrl: 1
WDS_Init():
The new WDS interface MAC = FF:FF:FF:FF:FF:FF
MacTabMatchWCID = 0
The new WDS interface MAC = FF:FF:FF:FF:FF:FF
MacTabMatchWCID = 0
The new WDS interface MAC = FF:FF:FF:FF:FF:FF
MacTabMatchWCID = 0
The new WDS interface MAC = FF:FF:FF:FF:FF:FF
MacTabMatchWCID = 0
Total allocated 4 WDS interfaces!
WtcSetMaxStaNum: MaxStaNum:102, BssidNum:2, WdsNum:4, ApcliNum:2, MaxNumChipRept:16, MinMcastWcid:124
red_is_enabled: set CR4/N9 RED Enable to 1.
cp_support_is_enabled: set CR4 CP_SUPPORT to Mode 2.
Correct apidx from 1 to 0 for WscUUIDInit
Generate UUID for apidx(0)
WifiSysOpen(), wdev idx = 1
wdev_attr_update(): wdevId1 = 02:02:72:f1:47:17
MtCmdSetDbdcCtrl:(ret = 0)
[PMF]APPMFInit:: apidx=1, MFPC=0, MFPR=0, SHA256=0
[PMF]WPAMakeRsnIeCap: RSNIE Capability MFPC=0, MFPR=0
[Force Roam] =
