beata,
I've been doing some work on this as well. I've copied over the dts folder from mainline 3.16 and modified the kirkwood-pogo_e02.dts for our uses. I've disabled the nand (I'm booting from usb, so nand is only used for uboot) and sdio and enabled spi0 and uart1. I haven't elaborated on the setup yet but I've got the pins documented on the wiki so anyone motivated should be able to replicate my work. I've also located MPP8 and MPP9 and enabled i2c-0 on these two pins. They're located on the back side of the device and have unpopulated pads and populated pullup resistors so it's a very easy access point, I'll take some pictures when I get time.
Anyway, here are my current device trees. I also had to delete the other kirkwood*.dts files because they were referencing the old kirkwood.dtsi.
kirkwood.dtsi
/include/ "skeleton.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
compatible = "marvell,kirkwood";
interrupt-parent = <&intc>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "marvell,feroceon";
reg = <0>;
clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
clock-names = "cpu_clk", "ddrclk", "powersave";
};
};
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
i2c0 = &i2c0;
};
mbus {
compatible = "marvell,kirkwood-mbus", "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
/* If a board file needs to change this ranges it must replace it completely */
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */
MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */
MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */
>;
controller = <&mbusc>;
pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
cesa: crypto@0301 {
compatible = "marvell,orion-crypto";
reg = <MBUS_ID(0xf0, 0x01) 0x30000 0x10000>,
<MBUS_ID(0x03, 0x01) 0 0x800>;
reg-names = "regs", "sram";
interrupts = <22>;
clocks = <&gate_clk 17>;
status = "okay";
};
nand: nand@012f {
#address-cells = <1>;
#size-cells = <1>;
cle = <0>;
ale = <1>;
bank-width = <1>;
compatible = "marvell,orion-nand";
reg = <MBUS_ID(0x01, 0x2f) 0 0x400>;
chip-delay = <25>;
/* set partition map and/or chip-delay in board dts */
clocks = <&gate_clk 7>;
pinctrl-0 = <&pmx_nand>;
pinctrl-names = "default";
status = "disabled";
};
};
ocp@f1000000 {
compatible = "simple-bus";
ranges = <0x00000000 0xf1000000 0x0100000>;
#address-cells = <1>;
#size-cells = <1>;
pinctrl: pin-controller@10000 {
/* set compatible property in SoC file */
reg = <0x10000 0x20>;
pmx_ge1: pmx-ge1 {
marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23",
"mpp24", "mpp25", "mpp26", "mpp27",
"mpp30", "mpp31", "mpp32", "mpp33";
marvell,function = "ge1";
};
pmx_nand: pmx-nand {
marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
"mpp4", "mpp5", "mpp18", "mpp19";
marvell,function = "nand";
};
/*
* Default SPI0 pinctrl setting with CSn on mpp0,
* overwrite marvell,pins on board level if required.
*/
pmx_spi: pmx-spi {
marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
marvell,function = "spi";
};
pmx_twsi0: pmx-twsi0 {
marvell,pins = "mpp8", "mpp9";
marvell,function = "twsi0";
};
/*
* Default UART pinctrl setting without RTS/CTS,
* overwrite marvell,pins on board level if required.
*/
pmx_uart0: pmx-uart0 {
marvell,pins = "mpp10", "mpp11";
marvell,function = "uart0";
};
pmx_uart1: pmx-uart1 {
marvell,pins = "mpp13", "mpp14";
marvell,function = "uart1";
};
};
core_clk: core-clocks@10030 {
compatible = "marvell,kirkwood-core-clock";
reg = <0x10030 0x4>;
#clock-cells = <1>;
};
spi0: spi@10600 {
compatible = "marvell,orion-spi";
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <23>;
reg = <0x10600 0x28>;
clocks = <&gate_clk 7>;
pinctrl-0 = <&pmx_spi>;
pinctrl-names = "default";
status = "disabled";
};
gpio0: gpio@10100 {
compatible = "marvell,orion-gpio";
#gpio-cells = <2>;
gpio-controller;
reg = <0x10100 0x40>;
ngpios = <32>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <35>, <36>, <37>, <38>;
clocks = <&gate_clk 7>;
};
gpio1: gpio@10140 {
compatible = "marvell,orion-gpio";
#gpio-cells = <2>;
gpio-controller;
reg = <0x10140 0x40>;
ngpios = <18>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <39>, <40>, <41>;
clocks = <&gate_clk 7>;
};
i2c0: i2c@11000 {
compatible = "marvell,mv64xxx-i2c";
reg = <0x11000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <29>;
clock-frequency = <100000>;
clocks = <&gate_clk 7>;
pinctrl-0 = <&pmx_twsi0>;
pinctrl-names = "default";
status = "disabled";
};
uart0: serial@12000 {
compatible = "ns16550a";
reg = <0x12000 0x100>;
reg-shift = <2>;
interrupts = <33>;
clocks = <&gate_clk 7>;
pinctrl-0 = <&pmx_uart0>;
pinctrl-names = "default";
status = "disabled";
};
uart1: serial@12100 {
compatible = "ns16550a";
reg = <0x12100 0x100>;
reg-shift = <2>;
interrupts = <34>;
clocks = <&gate_clk 7>;
pinctrl-0 = <&pmx_uart1>;
pinctrl-names = "default";
status = "disabled";
};
mbusc: mbus-controller@20000 {
compatible = "marvell,mbus-controller";
reg = <0x20000 0x80>, <0x1500 0x20>;
};
sysc: system-controller@20000 {
compatible = "marvell,orion-system-controller";
reg = <0x20000 0x120>;
};
bridge_intc: bridge-interrupt-ctrl@20110 {
compatible = "marvell,orion-bridge-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x20110 0x8>;
interrupts = <1>;
marvell,#interrupts = <6>;
};
gate_clk: clock-gating-control@2011c {
compatible = "marvell,kirkwood-gating-clock";
reg = <0x2011c 0x4>;
clocks = <&core_clk 0>;
#clock-cells = <1>;
};
l2: l2-cache@20128 {
compatible = "marvell,kirkwood-cache";
reg = <0x20128 0x4>;
};
intc: main-interrupt-ctrl@20200 {
compatible = "marvell,orion-intc";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x20200 0x10>, <0x20210 0x10>;
};
timer: timer@20300 {
compatible = "marvell,orion-timer";
reg = <0x20300 0x20>;
interrupt-parent = <&bridge_intc>;
interrupts = <1>, <2>;
clocks = <&core_clk 0>;
};
wdt: watchdog-timer@20300 {
compatible = "marvell,orion-wdt";
reg = <0x20300 0x28>, <0x20108 0x4>;
interrupt-parent = <&bridge_intc>;
interrupts = <3>;
clocks = <&gate_clk 7>;
status = "okay";
};
usb0: ehci@50000 {
compatible = "marvell,orion-ehci";
reg = <0x50000 0x1000>;
interrupts = <19>;
clocks = <&gate_clk 3>;
status = "okay";
};
dma0: xor@60800 {
compatible = "marvell,orion-xor";
reg = <0x60800 0x100
0x60A00 0x100>;
status = "okay";
clocks = <&gate_clk 8>;
xor00 {
interrupts = <5>;
dmacap,memcpy;
dmacap,xor;
};
xor01 {
interrupts = <6>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
dma1: xor@60900 {
compatible = "marvell,orion-xor";
reg = <0x60900 0x100
0x60B00 0x100>;
status = "okay";
clocks = <&gate_clk 16>;
xor00 {
interrupts = <7>;
dmacap,memcpy;
dmacap,xor;
};
xor01 {
interrupts = <8>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
eth0: ethernet-controller@72000 {
compatible = "marvell,kirkwood-eth";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x72000 0x4000>;
clocks = <&gate_clk 0>;
marvell,tx-checksum-limit = <1600>;
status = "disabled";
ethernet0-port@0 {
compatible = "marvell,kirkwood-eth-port";
reg = <0>;
interrupts = <11>;
/* overwrite MAC address in bootloader */
local-mac-address = [00 00 00 00 00 00];
/* set phy-handle property in board file */
};
};
mdio: mdio-bus@72004 {
compatible = "marvell,orion-mdio";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x72004 0x84>;
interrupts = <46>;
clocks = <&gate_clk 0>;
status = "disabled";
/* add phy nodes in board file */
};
eth1: ethernet-controller@76000 {
compatible = "marvell,kirkwood-eth";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x76000 0x4000>;
clocks = <&gate_clk 19>;
marvell,tx-checksum-limit = <1600>;
pinctrl-0 = <&pmx_ge1>;
pinctrl-names = "default";
status = "disabled";
ethernet1-port@0 {
compatible = "marvell,kirkwood-eth-port";
reg = <0>;
interrupts = <15>;
/* overwrite MAC address in bootloader */
local-mac-address = [00 00 00 00 00 00];
/* set phy-handle property in board file */
};
};
sata_phy0: sata-phy@82000 {
compatible = "marvell,mvebu-sata-phy";
reg = <0x82000 0x0334>;
clocks = <&gate_clk 14>;
clock-names = "sata";
#phy-cells = <0>;
status = "ok";
};
sata_phy1: sata-phy@84000 {
compatible = "marvell,mvebu-sata-phy";
reg = <0x84000 0x0334>;
clocks = <&gate_clk 15>;
clock-names = "sata";
#phy-cells = <0>;
status = "ok";
};
audio0: audio-controller@a0000 {
compatible = "marvell,kirkwood-audio";
#sound-dai-cells = <0>;
reg = <0xa0000 0x2210>;
interrupts = <24>;
clocks = <&gate_clk 9>;
clock-names = "internal";
status = "disabled";
};
};
};
kirkwood-6192.dtsi
/ {
mbus {
pciec: pcie-controller {
compatible = "marvell,kirkwood-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
ranges =
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
pcie0: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &intc 9>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gate_clk 2>;
status = "disabled";
};
};
};
ocp@f1000000 {
pinctrl: pin-controller@10000 {
compatible = "marvell,88f6192-pinctrl";
pmx_sata0: pmx-sata0 {
marvell,pins = "mpp5", "mpp21", "mpp23";
marvell,function = "sata0";
};
pmx_sata1: pmx-sata1 {
marvell,pins = "mpp4", "mpp20", "mpp22";
marvell,function = "sata1";
};
};
rtc: rtc@10300 {
compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
reg = <0x10300 0x20>;
interrupts = <53>;
clocks = <&gate_clk 7>;
};
sata: sata@80000 {
compatible = "marvell,orion-sata";
reg = <0x80000 0x5000>;
interrupts = <21>;
clocks = <&gate_clk 14>, <&gate_clk 15>;
clock-names = "0", "1";
status = "disabled";
};
};
};
kirkwood-pogo_e02.dts
/dts-v1/;
#include "kirkwood.dtsi"
#include "kirkwood-6192.dtsi"
/* kirkwood 6192 */
/ {
model = "Cloud Engines Pogoplug Mobile";
compatible = "cloudengines,pogov4a1", "marvell,kirkwood-88f6192", "marvell,kirkwood";
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>;
};
chosen {
bootargs = "console=ttyS0,115200n8 earlyprintk";
};
ocp@f1000000 {
pinctrl: pin-controller@10000 {
/* pmx_usb_power_enable: pmx-usb-power-enable {
marvell,pins = "mpp9";
marvell,function = "gpio";
}; */
pmx_led_green: pmx-led_green {
marvell,pins = "mpp22";
marvell,function = "gpio";
};
pmx_led_red: pmx-led_red {
marvell,pins = "mpp24";
marvell,function = "gpio";
};
pmx_sdio_cd: pmx_sdio_cd {
marvell,pins = "mpp27";
marvell,function = "gpio";
};
pmx_sdio_wp: pmx_sdio_wp {
marvell,pins = "mpp28";
marvell,function = "gpio";
};
pmx_eject_button: pmx_eject_button {
marvell,pins = "mpp29";
marvell,function = "gpio";
};
pmx_nand: pmx-nand {
marvell,pins = "";
marvell,function = "nand";
};
pmx_spi: pmx-spi {
marvell,pins = "mpp7", "mpp1", "mpp2", "mpp3";
marvell,function = "spi";
};
};
uart0: serial@12000 {
status = "ok";
};
uart1: serial@12100 {
status = "ok";
};
i2c0: i2c@11000 {
status = "ok";
};
spi0: spi@10600 {
status = "ok";
spidev@0 {
compatible = "spidev";
spi-max-frequency = <10000000>;
reg = <0>;
mode = <0>;
};
};
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&pmx_eject_button>;
pinctrl-names = "default";
button@1 {
label = "Eject button";
linux,code = <KEY_EJECTCD>;
gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
};
};
gpio-leds {
compatible = "gpio-leds";
pinctrl-0 = < &pmx_led_red &pmx_led_green >;
/* pinctrl-0 = < &pmx_usb_power_enable &pmx_led_red
&pmx_led_green >; */
pinctrl-names = "default";
health {
label = "status:green:health";
gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
fault {
label = "status:red:fault";
gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
};
};
/* regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&pmx_usb_power_enable>;
pinctrl-names = "default";
usb_power: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "USB Power";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>;
};
}; */
};
&nand {
chip-delay = <40>;
/* status = "okay"; */
/* partition@0 {
label = "u-boot";
reg = <0x0000000 0x100000>;
read-only;
};
partition@100000 {
label = "uImage";
reg = <0x0100000 0x400000>;
};
partition@500000 {
label = "pogoplug";
reg = <0x0500000 0x2000000>;
};
partition@2500000 {
label = "root";
reg = <0x02500000 0x5b00000>;
}; */
};
&mdio {
status = "okay";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
};
ð0 {
status = "okay";
ethernet0-port@0 {
phy-handle = <ðphy0>;
};
};
The "right" way to merge this is probably to update the rest of the kirkwood*.dts files to use the new mainline dts style but that requires a motivated person with quite a bit of free time on their hands 
Hope this is helpful
-Bob
