Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

pupie wrote:

Hi everyone,

I have done 16M Flash and 64M RAM hardware modification for TP-LINK TL-MR3420 and compiled a version openwrt for it. Everything works good as of now..

Original Hardware:
ar7241+ar9287 / 4M flash  /32M RAM /USB2.0. What we need to do is replcing its flash/memory chip and flash openwrt to unleash its potential.


Part one: find a proper chip:
1. You need to check the flash chip data sheet, it shall be 64k size per sector since this is defined in uboot.
Working Serial Flash chip:
8M: MX25L6405
16M: MX25L12805, S25FL128PIF

Memroy:
66 Pin,16bit DDR400 64M chip, you may desolder one from your old memory bar such as Hynix HY5DU121622DTP-D43 got find a suitable chip.


Part two: Compile uboot to support 8M/16M serial flash chip:
1. Download source code from tp-link gpl site: http://www.tp-link.com/support/todownload.asp?url=%2FGPL%2Fmr3420%5F3220v1%2Etar%2Egz
2. Extract the package, goto mr3420_3220v1/ap99/boot/u-boot/include/configs/ap99.h to modify the source code as following, be ware that  #define FLASH_SIZE 16 is the definition for your flash size, change it to 8 if you use a 8M chip.


/*
 * This file contains the configuration parameters for the pb93 board.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include <configs/ar7240.h>

//Support 8M/16M flash
#define FLASH_SIZE 16
#undef CFG_PROMPT
#define    CFG_PROMPT        "mr3420> "    /* Monitor Command Prompt    */

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define CFG_MAX_FLASH_BANKS     1        /* max number of memory banks */
#if (FLASH_SIZE == 16)
    #define CFG_MAX_FLASH_SECT      256    /* max number of sectors on one chip, NEED TO CHECK FLASH DATASHEET */
#else 
    #if (FLASH_SIZE == 8)
        #define CFG_MAX_FLASH_SECT      128    /* max number of sectors on one chip */
    #else
        #define CFG_MAX_FLASH_SECT      64    /* max number of sectors on one chip */
    #endif
#endif
#ifdef CONFIG_K31
    #define CFG_FLASH_SECTOR_SIZE   (256*1024)
    #define CFG_FLASH_SIZE          0x1000000 /* Total flash size */
#else
    #define CFG_FLASH_SECTOR_SIZE   (64*1024) /* NEED TO CHECK FLASH DATA SHEET 64k only*/
    #if (FLASH_SIZE == 16)
        #define CFG_FLASH_SIZE          0x01000000 /* Total flash size */
    #else
        #if (FLASH_SIZE == 8)
            #define CFG_FLASH_SIZE          0x00800000 /* Total flash size */
        #else
            #define CFG_FLASH_SIZE          0x00400000 /* Total flash size */
        #endif
    #endif
#endif

#define ENABLE_DYNAMIC_CONF 1
#define CONFIG_SUPPORT_AR7241 1

#if (CFG_MAX_FLASH_SECT * CFG_FLASH_SECTOR_SIZE) != CFG_FLASH_SIZE
#    error "Invalid flash configuration"
#endif

#define CFG_FLASH_WORD_SIZE     unsigned short 

/* 
 * We boot from this flash
 */
#define CFG_FLASH_BASE            0x9f000000

/*
 * Defines to change flash size on reboot
 */
#ifdef ENABLE_DYNAMIC_CONF

    #define UBOOT_FLASH_SIZE          (256 * 1024)

    #define UBOOT_ENV_SEC_START        (CFG_FLASH_BASE + UBOOT_FLASH_SIZE)

    #define CFG_FLASH_MAGIC           0xaabacada  
    #define CFG_FLASH_MAGIC_F         (UBOOT_ENV_SEC_START + CFG_FLASH_SECTOR_SIZE - 0x20)
    #define CFG_FLASH_SECTOR_SIZE_F   *(volatile int *)(CFG_FLASH_MAGIC_F + 0x4)
    #define CFG_FLASH_SIZE_F          *(volatile int *)(CFG_FLASH_MAGIC_F + 0x8) /* Total flash size */
    #define CFG_MAX_FLASH_SECT_F      (CFG_FLASH_SIZE / CFG_FLASH_SECTOR_SIZE) /* max number of sectors on one chip */
#endif


/* 
 * The following #defines are needed to get flash environment right 
 */
#define    CFG_MONITOR_BASE    TEXT_BASE
#define    CFG_MONITOR_LEN        (192 << 10)

#undef CONFIG_BOOTARGS
/* XXX - putting rootfs in last partition results in jffs errors */
#if (FLASH_SIZE == 16)
    #define CONFIG_BOOTARGS     "console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),13312k(rootfs),896k(uImage),64k(NVRAM),1792k(ART)"
#else
    #if (FLASH_SIZE == 8)
        #define CONFIG_BOOTARGS     "console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),5120k(rootfs),896k(uImage),64k(NVRAM),1792k(ART)"
    #else
        #define    CONFIG_BOOTARGS     "console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),2752k(rootfs),896k(uImage),64k(NVRAM),64k(ART) REVISIONID"
    #endif
#endif


/* default mtd partition table */
#undef MTDPARTS_DEFAULT

//#define MTDPARTS_DEFAULT    "mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),2752k(rootfs),896k(uImage),64k(NVRAM),64k(ART)"
#if (FLASH_SIZE == 16)
    #define MTDPARTS_DEFAULT    "mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),13312k(rootfs),896k(uImage),64k(NVRAM),1792k(ART)"
#else
    #if (FLASH_SIZE == 8)
        #define MTDPARTS_DEFAULT    "mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),5120k(rootfs),896k(uImage),64k(NVRAM),1792k(ART)"
    #else
        #define MTDPARTS_DEFAULT    "mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),2752k(rootfs),896k(uImage),64k(NVRAM),64k(ART)"
    #endif
#endif

#undef CFG_PLL_FREQ

#ifdef CONFIG_SUPPORT_AR7241 
    #define CFG_AR7241_PLL_FREQ    CFG_PLL_400_400_200
    //#define CFG_AR7241_PLL_FREQ    CFG_PLL_400_200_200
#endif

#define CFG_PLL_FREQ    CFG_PLL_400_400_200

#undef CFG_HZ
/*
 * MIPS32 24K Processor Core Family Software User's Manual
 *
 * 6.2.9 Count Register (CP0 Register 9, Select 0)
 * The Count register acts as a timer, incrementing at a constant
 * rate, whether or not an instruction is executed, retired, or
 * any forward progress is made through the pipeline.  The counter
 * increments every other clock, if the DC bit in the Cause register
 * is 0.
 */
/* Since the count is incremented every other tick, divide by 2 */
/* XXX derive this from CFG_PLL_FREQ */
#if (CFG_PLL_FREQ == CFG_PLL_200_200_100)
#   define CFG_HZ          (200000000/2)
#elif (CFG_PLL_FREQ == CFG_PLL_300_300_150)
#   define CFG_HZ          (300000000/2)
#elif (CFG_PLL_FREQ == CFG_PLL_350_350_175)
#   define CFG_HZ          (350000000/2)
#elif (CFG_PLL_FREQ == CFG_PLL_333_333_166)
#   define CFG_HZ          (333000000/2)
#elif (CFG_PLL_FREQ == CFG_PLL_266_266_133)
#   define CFG_HZ          (266000000/2)
#elif (CFG_PLL_FREQ == CFG_PLL_266_266_66)
#   define CFG_HZ          (266000000/2)
#elif (CFG_PLL_FREQ == CFG_PLL_400_400_200) || (CFG_PLL_FREQ == CFG_PLL_400_400_100)
#   define CFG_HZ          (400000000/2)
#elif (CFG_PLL_FREQ == CFG_PLL_320_320_80) || (CFG_PLL_FREQ == CFG_PLL_320_320_160)
#   define CFG_HZ          (320000000/2)
#elif (CFG_PLL_FREQ == CFG_PLL_410_400_200)
#   define CFG_HZ          (410000000/2)
#elif (CFG_PLL_FREQ == CFG_PLL_420_400_200)
#   define CFG_HZ          (420000000/2)
#elif (CFG_PLL_FREQ == CFG_PLL_240_240_120)
#   define CFG_HZ          (240000000/2)
#elif (CFG_PLL_FREQ == CFG_PLL_160_160_80)
#   define CFG_HZ          (160000000/2)
#elif (CFG_PLL_FREQ == CFG_PLL_400_200_200)
#   define CFG_HZ          (400000000/2)
#endif

/*
 * timeout values are in ticks
 */
#define CFG_FLASH_ERASE_TOUT    (2 * CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT    (2 * CFG_HZ) /* Timeout for Flash Write */

/*
 * Cache lock for stack
 */
#define CFG_INIT_SP_OFFSET    0x1000

/* lsz 081222
#define    CFG_ENV_IS_IN_FLASH    1
#undef CFG_ENV_IS_NOWHERE
*/
#undef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_IS_NOWHERE    1

/* Address and size of Primary Environment Sector    */
#define CFG_ENV_ADDR        0x9f040000
#define CFG_ENV_SIZE        CFG_FLASH_SECTOR_SIZE

#if defined(CONFIG_K31)
    define CONFIG_BOOTCOMMAND "bootm 0x9f050000"
#else
    #if (FLASH_SIZE == 16)
        #define CONFIG_BOOTCOMMAND "bootm 0x9f020000"
    #else
        #if (FLASH_SIZE == 8)
            //#define CONFIG_BOOTCOMMAND "bootm 0x9f550000"
            #define CONFIG_BOOTCOMMAND "bootm 0x9f020000"
        #else
            //#define CONFIG_BOOTCOMMAND "bootm 0x9f300000"
            #define CONFIG_BOOTCOMMAND "bootm 0x9f020000"
        #endif
    #endif
#endif
//#define CONFIG_FLASH_16BIT

/* DDR init values */

#define CONFIG_NR_DRAM_BANKS    2

/* DDR values to support AR7241 */

#ifdef CONFIG_SUPPORT_AR7241 
#define CFG_7241_DDR1_CONFIG_VAL      0xc7bc8cd0
//#define CFG_7241_DDR1_CONFIG_VAL      0x6fbc8cd0
#define CFG_7241_DDR1_MODE_VAL_INIT   0x133
#define CFG_7241_DDR1_EXT_MODE_VAL    0x0
#define CFG_7241_DDR1_MODE_VAL        0x33
//#define CFG_7241_DDR1_MODE_VAL        0x23
#define CFG_7241_DDR1_CONFIG2_VAL    0x9dd0e6a8


#define CFG_7241_DDR2_CONFIG_VAL    0xc7bc8cd0
#define CFG_7241_DDR2_MODE_VAL_INIT    0x133
#define CFG_7241_DDR2_EXT_MODE_VAL    0x402
#define CFG_7241_DDR2_MODE_VAL        0x33
#define CFG_7241_DDR2_CONFIG2_VAL    0x9dd0e6a8
#endif /* _SUPPORT_AR7241 */

/* DDR settings for AR7240 */

#define CFG_DDR_REFRESH_VAL     0x4f10
#define CFG_DDR_CONFIG_VAL      0xc7bc8cd0
#define CFG_DDR_MODE_VAL_INIT   0x133
#ifdef LOW_DRIVE_STRENGTH
#       define CFG_DDR_EXT_MODE_VAL    0x2
#else
#       define CFG_DDR_EXT_MODE_VAL    0x0
#endif
#define CFG_DDR_MODE_VAL        0x33

#define CFG_DDR_TRTW_VAL        0x1f
#define CFG_DDR_TWTR_VAL        0x1e

#define CFG_DDR_CONFIG2_VAL      0x9dd0e6a8
#define CFG_DDR_RD_DATA_THIS_CYCLE_VAL  0x00ff

/* DDR2 Init values */
#define CFG_DDR2_EXT_MODE_VAL    0x402


#ifdef ENABLE_DYNAMIC_CONF
    #define CFG_DDR_MAGIC           0xaabacada  
    #define CFG_DDR_MAGIC_F         (UBOOT_ENV_SEC_START + CFG_FLASH_SECTOR_SIZE - 0x30)
    #define CFG_DDR_CONFIG_VAL_F    *(volatile int *)(CFG_DDR_MAGIC_F + 4)
    #define CFG_DDR_CONFIG2_VAL_F    *(volatile int *)(CFG_DDR_MAGIC_F + 8)
    #define CFG_DDR_EXT_MODE_VAL_F  *(volatile int *)(CFG_DDR_MAGIC_F + 12)
#endif

#define CONFIG_NET_MULTI

#define CONFIG_AG7240_SPEPHY /* choose eth1 first for tftpboot interface added by tiger 07/20/09*/

#define CONFIG_MEMSIZE_IN_BYTES
#define CONFIG_PCI

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
/*
#define CONFIG_COMMANDS    (( CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_ELF | CFG_CMD_PCI | CFG_CMD_FLS |\
    CFG_CMD_MII | CFG_CMD_PING | CFG_CMD_NET | CFG_CMD_JFFS2 | CFG_CMD_ENV | CFG_CMD_PLL| \
    CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | CFG_CMD_ELF | CFG_CMD_DDR | CFG_CMD_ETHREG))
*/
/* 091123 - tiger reduced */
#define CONFIG_COMMANDS (CFG_CMD_LOADB | CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_NET)

#define CONFIG_IPADDR   192.168.1.1
#define CONFIG_SERVERIP 192.168.1.100
#define CONFIG_ETHADDR 0x00:0xaa:0xbb:0xcc:0xdd:0xee
//lzn
#define CONFIG_ETH1ADDR         00:11:0B:00:00:02

#define CFG_FAULT_ECHO_LINK_DOWN    1


#define CFG_PHY_ADDR 0 
#define CFG_AG7240_NMACS 2
#define CFG_GMII     0
#define CFG_MII0_RMII             1
#define CFG_AG7100_GE0_RMII             1

#define CFG_BOOTM_LEN    (16 << 20) /* 16 MB */
/* lsz 081222
#define DEBUG
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "hush>"
*/
#undef DEBUG
#undef CFG_HUSH_PARSER
#undef CFG_PROMPT_HUSH_PS2

/*
** Parameters defining the location of the calibration/initialization
** information for the two Merlin devices.
** NOTE: **This will change with different flash configurations**
*/

#if defined(CONFIG_K31)
#define WLANCAL                         0x9f3f1000
#else
#define WLANCAL                         0xbfff1000
#endif
#define BOARDCAL                        0xbfff0000
#define ATHEROS_PRODUCT_ID              137
#define CAL_SECTOR                      (CFG_MAX_FLASH_SECT - 1)

/* For Merlin, both PCI, PCI-E interfaces are valid */
#define AR7240_ART_PCICFG_OFFSET        12

/* move from autoconf.h of kernel src, added by tiger 20091225 */
/* For GPIO setting
 *
 * JumpStart LED
 */
#define CONFIG_GPIO_JUMPSTART_LED_BIT 0
#define CONFIG_GPIO_JUMPSTART_LED_ON 0

/*
 * Ready Status
 */
#define CONFIG_GPIO_READY_STATUS_BIT 1
#define CONFIG_GPIO_READY_STATUS_ON 0

/*
 * USB(TMS) LED
 */
#define CONFIG_GPIO_USB_LED_BIT 8
#define CONFIG_GPIO_USB_LED_ON 0

/*
 * Reset Factory Default
 */
#define CONFIG_GPIO_RESET_FAC_BIT 11
#define CONFIG_GPIO_FAC_RST_HOLD_TIME 5

/*
 * JumpStart Switch
 */
#define CONFIG_GPIO_JUMPSTART_SW_BIT 12

#include <cmd_confdefs.h>

#endif    /* __CONFIG_H */

3. Got build directory:
mv Makefile Makefile.bak
mv Makefile.ap99 Makefile
mkdir /home/YourUserName/images/ap99
make BOARD_TYPE=ap99 uboot

then you will have a u-boot.bin in /home/YouUserName/images/ap99.

4. Since the u-boot.bin shall be 128k in length. Use WinHEX or other hexadecimal editor to create a empty project, in my instance I user Winhex, use replace function to fill all bytes with FF and paste the u-boot.bin(Ctrl+A select all, Ctrl+B to write from 0x000000) to the template from the begining so that you got a 128k u-boot with FF appended.

5. Check the back of you router box, write down your MAC and PIN, write the mac and pin to your uboot.bin:
MAC 6 bytes from 0x1FC00
PIN 8 bytes from 0x1FE00

Now the u-boot is ready and save it for furture usage.

Part Three: Compile your openwrt firmware:

1. Checkout trunk and update feeds as other common tutorials
2. Modify Openwrt code to support and partition your flash:

/trunk/tools/firmware-utils/src/mktplinkfw.c

fw_max_len = 0x7c0000 /* for 8M Flash, use 0xfc0000 for 16M flash*/

target/linux/ar71xx/files/arch/mips/ar71xx/mach-tl-mr3x20.c


4M:

                 .name           = "u-boot",
                 .offset         = 0,
                 .size           = 0x020000,
                 .mask_flags     = MTD_WRITEABLE,
         }, {
                 .name           = "kernel",
                 .offset         = 0x020000,
                 .size           = 0x140000,
         }, {
                 .name           = "rootfs",
                 .offset         = 0x160000,
                 .size           = 0x290000,
         }, {
                 .name           = "art",
                 .offset         = 0x3f0000,
                 .size           = 0x010000,
                 .mask_flags     = MTD_WRITEABLE,
         }, {
                 .name           = "firmware",
                 .offset         = 0x020000,
                 .size           = 0x3d0000,
         }
};

8M:

                 .name           = "u-boot",
                 .offset         = 0,
                 .size           = 0x020000,
                 .mask_flags     = MTD_WRITEABLE,
         }, {
                 .name           = "kernel",
                 .offset         = 0x020000,
                 .size           = 0x140000,
         }, {
                 .name           = "rootfs",
                 .offset         = 0x160000,
                 .size           = 0x690000,
         }, {
                 .name           = "art",
                 .offset         = 0x7f0000,
                 .size           = 0x010000,
                 .mask_flags     = MTD_WRITEABLE,
         }, {
                 .name           = "firmware",
                 .offset         = 0x020000,
                 .size           = 0x7d0000,
         }
};


16M:

                 .name           = "u-boot",
                 .offset         = 0,
                 .size           = 0x020000,
                 .mask_flags     = MTD_WRITEABLE,
         }, {
                 .name           = "kernel",
                 .offset         = 0x020000,
                 .size           = 0x140000,
         }, {
                 .name           = "rootfs",
                 .offset         = 0x160000,
                 .size           = 0xe90000,
         }, {
                 .name           = "art",
                 .offset         = 0xff0000,
                 .size           = 0x010000,
                 .mask_flags     = MTD_WRITEABLE,
         }, {
                 .name           = "firmware",
                 .offset         = 0x020000,
                 .size           = 0xfd0000,
         }
};



0x000000000000-0x000000020000 : "u-boot"  //128k
0x000000020000-0x000000160000 : "kernel"  ///1280K
0x000000160000-0x000000ff0000 : "rootfs"   //14912K
0x0000008c0000-0x000000ff0000 : "rootfs_data" //7360k
0x000000ff0000-0x000001000000 : "art"      //64k
0x000000020000-0x000000ff0000 : "firmware" //16192k




3. menuconfig and make your image as common tutorials. save the image openwrt-ar71xx-generic-tl-mr3420-v1-squashfs-factory.bin for future usage.
4. back up your 64k art (wirelss driver data, without it your wireless does not work.) this is important! you can also use the backup one from other tp-link ar7241 chipset routers.

Part Four: Make up a flash programmer file:
1. Use Winhex to create a empty 16M template, use replace to replace all 00 to FF.
2. Open the u-boot.bin previously you created, copy all (Ctrl+A) and Write(Ctrl+b) the 128k bytes from begining to the template.
3. Open the openwrt firmware openwrt-ar71xx-generic-tl-mr3420-v1-squashfs-factory.bin write all data(about 15.75M) as step 2 from 0x000000020000 to the file.
4. Open the art file, write the 64k file to the lastest 64k from 0x000000ff0000 to your template.
5. save all to a new file such as New.bin for future usage.


Part five: Solder the chip
1. Flash the whole file to your flash chip by flash programmer ( you shall have this hardware to as help from others)
2. Solder the flash and memory chip, 64M RAM can be detected after changing the chip, no need to modify the uboot code to support 64M RAM
3. Solder the TTL pin for TTL debugging.

You will be noticed  as below infos are from the boot log in TTL:

AP99 (ar7241 - Virian) U-boot
DRAM:  
sri
ar7240_ddr_initial_config(133): virian ddr1 init
#### TAP VALUE 1 = 0xf, 2 = 0x10 [0x0: 0x1f]
64 MB
id read 0x100000ff
sector count = 256
Flash: 16 MB
Using default environment

In:    serial
Out:   serial
Err:   serial
Net:   ag7240_enet_initialize...
No valid address in Flash. Using fixed address
No valid address in Flash. Using fixed address
Virian MDC CFG Value ==> 4
: cfg1 0xf cfg2 0x7014
eth0: 00:03:7f:09:0b:ad
eth0 up
Virian MDC CFG Value ==> 4
: cfg1 0xf cfg2 0x7214
eth1: 00:03:7f:09:0b:ad
ATHRS26: resetting s26
ATHRS26: s26 reset done
eth1 up
eth0, eth1
Autobooting in 1 seconds
## Booting image at 9f020000 ...
   Uncompressing Kernel Image ... OK

...more logs ....
Creating 5 MTD partitions on "spi0.0":
0x000000000000-0x000000020000 : "u-boot"
0x000000020000-0x000000160000 : "kernel"
0x000000160000-0x000000ff0000 : "rootfs"
mtd: partition "rootfs" set to be root filesystem
mtd: partition "rootfs_data" created automatically, ofs=3A0000, len=C50000 
0x0000003a0000-0x000000ff0000 : "rootfs_data"
0x000000ff0000-0x000001000000 : "art"
0x000000020000-0x000000ff0000 : "firmware"

...more logs ....

NOW YOU GOT A UPGRADED ROUTER! ENJOY!

I'm having problems with compiling the u-boot image:

mips-linux-uclibc-objcopy --gap-fill=0xff -O srec u-boot u-boot.srec
mips-linux-uclibc-objcopy --gap-fill=0xff -O binary u-boot u-boot.bin
make[1]: Leaving directory `/root/mr3420_3220v1/ap99/boot/u-boot'
cp /root/mr3420_3220v1/build/../ap99/boot/u-boot/u-boot.bin /root/mr3420_3220v1/build/../images/ap99/u-boot.bin
cp: cannot create regular file `/root/mr3420_3220v1/build/../images/ap99/u-boot.bin': No such file or directory
make: *** [uboot] Error 1

It seems a fair bit backwards with an errror output that lacks the full path when complaining about something related to that...very much linux..its even trunktated in the log file. Not very clever. hmm
How can I enable that I get full path in terminal and log in Ubuntu?

DIR-825.b2 @ 840MHz (16/128MB) : PC Engines Alix6e2 : WR703N (8/64MB) : MR11U (8/64MB) : WR512-3GN (128MB)

Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

Lennong wrote:
pupie wrote:

......
......
NOW YOU GOT A UPGRADED ROUTER! ENJOY!

I'm having problems with compiling the u-boot image:

mips-linux-uclibc-objcopy --gap-fill=0xff -O srec u-boot u-boot.srec
mips-linux-uclibc-objcopy --gap-fill=0xff -O binary u-boot u-boot.bin
make[1]: Leaving directory `/root/mr3420_3220v1/ap99/boot/u-boot'
cp /root/mr3420_3220v1/build/../ap99/boot/u-boot/u-boot.bin /root/mr3420_3220v1/build/../images/ap99/u-boot.bin
cp: cannot create regular file `/root/mr3420_3220v1/build/../images/ap99/u-boot.bin': No such file or directory
make: *** [uboot] Error 1

It seems a fair bit backwards with an errror output that lacks the full path when complaining about something related to that...very much linux..its even trunktated in the log file. Not very clever. hmm
How can I enable that I get full path in terminal and log in Ubuntu?

I also had problem to compile u-boot by following pupie's instructions.  The output are shown below:

....../mr3420_3220v1/build$ make BOARD_TYPE=ap99 uboot
Makefile:145: "Should specify WIRELESSTOOLNAMES value"
cd /home/fling/uboot/mr3420_3220v1/build/../ap99/boot/u-boot && make ARCH=mips CROSS_COMPILE=mips-linux-uclibc- mrproper
make[1]: Entering directory `/home/fling/uboot/mr3420_3220v1/ap99/boot/u-boot'
make[1]: *** No rule to make target `mrproper'.  Stop.
make[1]: Leaving directory `/home/fling/uboot/mr3420_3220v1/ap99/boot/u-boot'
make: *** [uboot] Error 2

What I did wrong?

28 (edited by Lennong 2012-02-05 11:14:33)

Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

twinclouds wrote:
Lennong wrote:
pupie wrote:

......
......
NOW YOU GOT A UPGRADED ROUTER! ENJOY!

I'm having problems with compiling the u-boot image:

mips-linux-uclibc-objcopy --gap-fill=0xff -O srec u-boot u-boot.srec
mips-linux-uclibc-objcopy --gap-fill=0xff -O binary u-boot u-boot.bin
make[1]: Leaving directory `/root/mr3420_3220v1/ap99/boot/u-boot'
cp /root/mr3420_3220v1/build/../ap99/boot/u-boot/u-boot.bin /root/mr3420_3220v1/build/../images/ap99/u-boot.bin
cp: cannot create regular file `/root/mr3420_3220v1/build/../images/ap99/u-boot.bin': No such file or directory
make: *** [uboot] Error 1

It seems a fair bit backwards with an errror output that lacks the full path when complaining about something related to that...very much linux..its even trunktated in the log file. Not very clever. hmm
How can I enable that I get full path in terminal and log in Ubuntu?

I also had problem to compile u-boot by following pupie's instructions.  The output are shown below:

....../mr3420_3220v1/build$ make BOARD_TYPE=ap99 uboot
Makefile:145: "Should specify WIRELESSTOOLNAMES value"
cd /home/fling/uboot/mr3420_3220v1/build/../ap99/boot/u-boot && make ARCH=mips CROSS_COMPILE=mips-linux-uclibc- mrproper
make[1]: Entering directory `/home/fling/uboot/mr3420_3220v1/ap99/boot/u-boot'
make[1]: *** No rule to make target `mrproper'.  Stop.
make[1]: Leaving directory `/home/fling/uboot/mr3420_3220v1/ap99/boot/u-boot'
make: *** [uboot] Error 2

What I did wrong?

I'm not sure. Honestly, I'm really crappy at anything Linux related, perhaps only persistent enough.. It seems like you either don't have the user rights or missing a script. I did run my uboot compiling as root, just in case.

Personally I managed to dig out the uboot.bin from another folder, not indicated at all by the error printout... I have just soldered on the flash and are up and running with 16MB/64MB. However, I do not have any wifi interface at all, indicating that I got the ART on the wrong spot. Question is, do I have to reflash it again or can I "move" the ART partition from busybox?

DIR-825.b2 @ 840MHz (16/128MB) : PC Engines Alix6e2 : WR703N (8/64MB) : MR11U (8/64MB) : WR512-3GN (128MB)

Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

Hi Lennong

Make directory in your /home/lennong/images/ap99

Do not compile as a root user

                        -Map u-boot.map -o u-boot
mips-linux-uclibc-objcopy --gap-fill=0xff -O srec u-boot u-boot.srec
mips-linux-uclibc-objcopy --gap-fill=0xff -O binary u-boot u-boot.bin
make[1]: Leaving directory `/home/xopal/uboot/ap99/boot/u-boot'
cp /home/xopal/uboot/build/../ap99/boot/u-boot/u-boot.bin /home/xopal/uboot/build/../images/ap99/u-boot.bin

Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

xopal wrote:

Hi Lennong

Make directory in your /home/lennong/images/ap99

Do not compile as a root user

                        -Map u-boot.map -o u-boot
mips-linux-uclibc-objcopy --gap-fill=0xff -O srec u-boot u-boot.srec
mips-linux-uclibc-objcopy --gap-fill=0xff -O binary u-boot u-boot.bin
make[1]: Leaving directory `/home/xopal/uboot/ap99/boot/u-boot'
cp /home/xopal/uboot/build/../ap99/boot/u-boot/u-boot.bin /home/xopal/uboot/build/../images/ap99/u-boot.bin

Hi!

I actually tried exactly that before compiling as root. I will try again. It seems like my uboot.bin hasn't picked up the partitioning properly as I get really weird offsets (sorry for the garbage, havn't soldered on the resistor yet):

C¡H¨Õ½½Ñ1.1.4 (Feb  5 2012 - 13:09:14)

AP99 (ar7241 - Virian) U-boot
DRAM:
sri
ar7240_ddr_initial_config(133): virian ddr1 init
¤¤¤$¢AVALUE 1 = 0xf, 2 = 0x10 [0x0: 0x1f]
64 MB
Z
0x100000ff
sector count = 256
Flash: 16 MB
U®Ëëdefault environment

¨*IIS NOT CALIBRATED!!!
In:    serial
Out:   serial
Err:   serial
ªÑé   ag7240_enet_initialize...
No valid address in Flash. Using fixed address
No valid address in Flash. Using fixed address
UK¥
¹MDC CFG Value ==> 4
: cfg1 0xf cfg2 0x7014
Y
 ÒÒÒº2é09:0b:ad
Y
 ªÁ5
    Virian MDC CFG Value ==> 4
: cfg1 0xf cfg2 0x7214
Y+ÒÒÒº2é09:0b:ad
ATHRS26: resetting s26
PJ5%²ÒÉ6 reset done
Y+ªÁ5
     eth0, eth1
Autobooting in 1 seconds
¤$½½Ñ¥¹image at 9f020000 ...
   Uncompressing Kernel Image ... jªH¨HhE
ÉÑ¥¹kernel ...

¡H¨è
    ¹]ÉÑkernel loader for AR7XXX/AR9XXX
Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
Looking for OpenWrt image... found at 0xbf022000
Decompressing kernel... ÖË«

*WÉÑ¥¹kernel at 80060000...

[    0.000000] Linux version 2.6.39.4 (mr@ubuntu) (gcc version 4.5.4 20120105 (prerelease) (L            inaro GCC 4.5-2012.01) ) #6 Sun Feb 5 12:06:34 WIT 2012
[    0.000000] bootconsole [early0] enabled
[    0.000000] CPU revision is: 00019374 (MIPS 24Kc)
[    0.000000] SoC: Atheros AR7241 rev 1
[    0.000000] Clocks: CPU:400.000MHz, DDR:400.000MHz, AHB:200.000MHz, Ref:5.000MHz
[    0.000000] Determined physical RAM map:
[    0.000000]  memory: 04000000 @ 00000000 (usable)
Ø   0.000000] Initrd not found or empty - disabling initrd
[    0.000000] Zone PFN ranges:
[    0.000000]   Normal   0x00000000 -> 0x00004000
[    0.000000] Movable zone start PFN for each node
[    0.000000] early_node_map[1] active PFN ranges
[    0.000000]     0: 0x00000000 -> 0x00004000
+rêBuilt 1 zonelists in Zone order, mobility grouping on.  Total pages: 16256
[    0.000000] Kernel command line:  board=TL-MR3420 console=ttyS0,115200 rootfstype=squashfs            ,jffs2 noinitrd
[    0.000000] PID hash table entries: 256 (order: -2, 1024 bytes)
[    0.000000] Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
[    0.000000] Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
+rêPrimary instruction cache 64kB, VIPT, 4-way, linesize 32 bytes.
[    0.000000] Primary data cache 32kB, 4-way, VIPT, cache aliases, linesize 32 bytes
[    0.000000] Writing ErrCtl register=00000000
[    0.000000] Readback ErrCtl register=00000000
+rêMemory: 61832k/65536k available (2014k kernel code, 3704k reserved, 402k data, 188k init,             0k highmem)
[    0.000000] SLUB: Genslabs=9, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[    0.000000] NR_IRQS:80
[    0.000000] Calibrating delay loop... &S½
                                            [    0.080000] pid_max: default: 32768 minimum: 3            01
[    0.080000] Mount-cache hash table entries: 512
+rÊêNET: Registered protocol family 16
+rêMIPS: machine is TP-LINK TL-MR3420
+rºêregistering PCI controller with io_map_base unset
+rº¢êbio: create slab <bio-0> at 0
+rºªêpci 0000:00:00.0: invalid calibration data
[    0.750000] pci 0000:00:00.0: BAR 0: assigned [mem 0x10000000-0x1000ffff 64bit]
[    0.760000] pci 0000:00:00.0: BAR 0: set to [mem 0x10000000-0x1000ffff 64bit] (PCI address             [0x10000000-0x1000ffff])
[    0.770000] PCI: mapping irq 72 to pin1@0000:00:00.0
+rººêSwitching to clocksource MIPS
+rºÂêNET: Registered protocol family 2
[    0.780000] IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.780000] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
[    0.790000] TCP bind hash table entries: 2048 (order: 1, 8192 bytes)
[    0.790000] TCP: Hash tables configured (established 2048 bind 2048)
[    0.800000] TCP reno registered
[    0.800000] UDP hash table entries: 256 (order: 0, 4096 bytes)
[    0.810000] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
[    0.810000] NET: Registered protocol family 1
+rÂêsquashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.840000] JFFS2 version 2.2 (NAND) (SUMMARY) (LZMA) (RTIME) (CMODE_PRIORITY) (c) 2001-20            06 Red Hat, Inc.
+r廐msgmni has been set to 120
[    0.860000] io scheduler noop registered
[    0.860000] io scheduler deadline registered (default)
[    0.870000] Serial: 8250/16550 driver, 1 ports, IRQ sharing disabled
+rÂÊêserial8250.0: ttyS0 at MMIO 0x18020000 (irq = 11) is a 16550A
[    0.900000] console [ttyS0] enabled, bootconsole disabled
[    0.900000] console [ttyS0] enabled, bootconsole disabled
+rÊêAtheros AR71xx SPI Controller driver version 0.2.4
+rÊêm25p80 spi0.0: found mx25l12805d, expected m25p80
[    0.930000] m25p80 spi0.0: mx25l12805d (16384 Kbytes)
+rÊê5 tp-link partitions found on MTD device spi0.0
[    0.940000] Creating 5 MTD partitions on "spi0.0":
[    0.940000] 0x000000000000-0x000000020000 : "u-boot"
+r滐0x000000020000-0x0000000f7600 : "kernel"
[    0.950000] mtd: partition "kernel" must either start or end on erase block boundary or be             smaller than an erase block -- forcing read-only
+r漐0x0000000f7600-0x000000ff0000 : "rootfs"
[    0.970000] mtd: partition "rootfs" must either start or end on erase block boundary or be             smaller than an erase block -- forcing read-only
+rÊÊêmtd: partition "rootfs" set to be root filesystem
[    0.990000] mtd: partition "rootfs_data" created automatically, ofs=260000, len=D90000
[    1.000000] 0x000000260000-0x000000ff0000 : "rootfs_data"
+rê0x000000ff0000-0x000001000000 : "art"
+rê0x000000020000-0x000000ff0000 : "firmware"
+rºêag71xx_mdio: probed
+rºêeth0: Atheros AG71xx at 0xba000000, irq 5
+rʲêeth0: Found an AR7240/AR9330 built-in switch
+rÊÂêeth1: Atheros AG71xx at 0xb9000000, irq 4
+rªÊêAtheros AR71xx hardware watchdog driver version 0.1.0
[    2.590000] TCP westwood registered
[    2.600000] NET: Registered protocol family 17
[    2.600000] 802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
[    2.610000] All bugs added by David S. Miller <davem@redhat.com>
+r²êVFS: Mounted root (squashfs filesystem) readonly on device 31:2.
+r²êFreeing unused kernel memory: 188k freed
+ªrêinput: gpio-keys-polled as /devices/platform/gpio-keys-polled/input/input0
+ªr¢êButton Hotplug driver version 0.4.1
KÉ¥¹¥Ñ-
%ÍÍthe [f] key and hit [enter] to enter failsafe mode
K
 +ÂrʲêJFFS2 notice: (421) jffs2_build_xattr_subsystem: complete building xattr subsystem, 1 of xdatum (1 u¡¥¹to jffs2 orphan) and 9 of xref (0 dead, 2 orphan) found.
KJ¹¥Ñ-
C!Å
Ípress Enter to activate this console. +r²ªêCompat-wireless backport release: compat-wireless-2011-11-29
[   10.650000] Backport based on wireless-testing.git master-2011-12-01
DIR-825.b2 @ 840MHz (16/128MB) : PC Engines Alix6e2 : WR703N (8/64MB) : MR11U (8/64MB) : WR512-3GN (128MB)

31

Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

twinclouds wrote:

During the flash process, the image is loaded to 0x81000000 and then transferred to 0x9f020000.  Since the flash ROM is 4M long, it's length is 0x400000.  What does 0x81 and 0x9f in these addresses mean?

OpenWrt / WRT160NL flashing and kernel panic

Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

Hi Lennong

You lost the art.bin part of your fimware, thats why you got message "IIS NOT CALIBRATED", the wifi part will not start.

Do back up the art.bin file before you upgrade the chip.

33 (edited by Lennong 2012-02-05 16:08:07)

Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

xopal wrote:

Hi Lennong

You lost the art.bin part of your fimware, thats why you got message "IIS NOT CALIBRATED", the wifi part will not start.

Do back up the art.bin file before you upgrade the chip.

I did read the chip in a reader and extracted the full image and ART from there. It is in the new image but on the wrong spot. According to OP it should be on 0x3f0000 and 0x010000 forward on a 4MB chip, but it was actually located on 0x3f1000 and forward. I did put it on 0xff0000 and forward as OP did on the 16MB chip, but it didnt fly. I'm going to dig around for an extracted ART, possibly request from forum members and do a comparison between them, could be useful.

DIR-825.b2 @ 840MHz (16/128MB) : PC Engines Alix6e2 : WR703N (8/64MB) : MR11U (8/64MB) : WR512-3GN (128MB)

34

Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

I'm not quite sure if it works, but maybe it works to just do an "mtd write art.bin art". It just depends if the ART-partition is write protected.
Or, since you have already a serial link, enter uboot and flash via tftp (similar to this: http://wiki.openwrt.org/toh/tp-link/tl-mr3420#flash.via.tftp). You probably have to replace all 0x9f020000 with 9fff0000 and 0x3c0000 with 10000.
If you don't have a tftp server running already, you could also upload the art.bin via serial link, it should just take a few seconds: http://wiki.openwrt.org/toh/tp-link/tl- … 232.method

Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

fyi wrote:
twinclouds wrote:

During the flash process, the image is loaded to 0x81000000 and then transferred to 0x9f020000.  Since the flash ROM is 4M long, it's length is 0x400000.  What does 0x81 and 0x9f in these addresses mean?

OpenWrt / WRT160NL flashing and kernel panic

Thanks.

36 (edited by Lennong 2012-02-06 03:43:20)

Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

Lennong wrote:
xopal wrote:

Hi Lennong

You lost the art.bin part of your fimware, thats why you got message "IIS NOT CALIBRATED", the wifi part will not start.

Do back up the art.bin file before you upgrade the chip.

I did read the chip in a reader and extracted the full image and ART from there. It is in the new image but on the wrong spot. According to OP it should be on 0x3f0000 and 0x010000 forward on a 4MB chip, but it was actually located on 0x3f1000 and forward. I did put it on 0xff0000 and forward as OP did on the 16MB chip, but it didnt fly. I'm going to dig around for an extracted ART, possibly request from forum members and do a comparison between them, could be useful.

It seems like the OP has put in a bit of wrong code in the ap99.h:

#ifdef CONFIG_K31
    #define CFG_FLASH_SECTOR_SIZE   (256*1024)
    #define CFG_FLASH_SIZE          0x1000000 /* Total flash size */
#else
    #define CFG_FLASH_SECTOR_SIZE   (64*1024) /* NEED TO CHECK FLASH DATA SHEET 64k only*/
    #if (FLASH_SIZE == 16)
        #define CFG_FLASH_SIZE          0x01000000 /* Total flash size */ <- Should this not be 0x01600000, indicating 16MB???
    #else
        #if (FLASH_SIZE == 8)
            #define CFG_FLASH_SIZE          0x00800000 /* Total flash size */
        #else
            #define CFG_FLASH_SIZE          0x00400000 /* Total flash size */
        #endif
    #endif
#endif

This would actually expain why my MTD looks like it does:

[    0.940000] Creating 5 MTD partitions on "spi0.0":
[    0.940000] 0x000000000000-0x000000020000 : "u-boot"
[    0.950000] 0x000000020000-0x000000100000 : "kernel"
[    0.960000] 0x000000100000-0x000000ff0000 : "rootfs"
[    0.960000] mtd: partition "rootfs" set to be root filesystem
[    0.970000] split_squashfs: no squashfs found in "spi0.0"
[    0.970000] 0x000000ff0000-0x000001000000 : "art"
[    0.980000] 0x000000020000-0x000000ff0000 : "firmware"

This indicates that the u-boot and ART is in the right place (according to OP), BUT the
genererated firmware is messed up. The kernel is on 0x000000020000-0x000000100000, when the OP has it on 0x000000020000-0x000000160000. (indicating the "missing" 6MB)

I also did plug in a downloaded 4MB image from trunk and dropped it inside the 16MB image I compiled to verify the offset for ART. This resulted in this:

[    0.930000] 5 tp-link partitions found on MTD device spi0.0
[    0.940000] Creating 5 MTD partitions on "spi0.0":
[    0.940000] 0x000000000000-0x000000020000 : "u-boot"
[    0.950000] 0x000000020000-0x000000101000 : "kernel"
[    0.950000] mtd: partition "kernel" must either start or end on erase block b              oundary or be smaller than an erase block -- forcing read-only
[    0.970000] 0x000000101000-0x000000ff0000 : "rootfs"
[    0.970000] mtd: partition "rootfs" must either start or end on erase block b              oundary or be smaller than an erase block -- forcing read-only
[    0.990000] mtd: partition "rootfs" set to be root filesystem
[    0.990000] mtd: partition "rootfs_data" created automatically, ofs=270000, l              en=D80000
[    1.000000] 0x000000270000-0x000000ff0000 : "rootfs_data"
[    1.010000] 0x000000ff0000-0x000001000000 : "art"
[    1.020000] 0x000000020000-0x000000ff0000 : "firmware"

It seems like the partitioning is a bit different, starting from "kernel". This verifies that along the line I need to move the offset according to that ART was located at  0x3f1000 and forward on my board, not  0x3f0000 and forward as OP had it. A bit strange as I use the same package as him to generate u-boot.bin. Anyway, I will reflash it today with some changes and see what gives.

DIR-825.b2 @ 840MHz (16/128MB) : PC Engines Alix6e2 : WR703N (8/64MB) : MR11U (8/64MB) : WR512-3GN (128MB)

37 (edited by xopal 2012-02-06 06:21:44)

Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

Should this not be 0x01600000, indicating 16MB???

Open the scientific calculator , to convert from dec to hex

Decimal----------Hexadecimal

16 ---------------10 (0x01000000)  16MB
8-----------------8  (0x00800000)   8MB
4-----------------4  (0x00400000)   4MB


May this help you

Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

xopal wrote:

Should this not be 0x01600000, indicating 16MB???

Open the scientific calculator , to convert from dec to hex

Decimal----------Hexadecimal

16 ---------------10 (0x01000000)  16MB
8-----------------8  (0x00800000)   8MB
4-----------------4  (0x00400000)   4MB


May this help you

Aha, hehe! There you go! Thanks!

This shows how much I really know...still fun though. Going to try some flashing.

DIR-825.b2 @ 840MHz (16/128MB) : PC Engines Alix6e2 : WR703N (8/64MB) : MR11U (8/64MB) : WR512-3GN (128MB)

Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

Ok, did some more testing before desolder the chip. When I flash it with a compiled squash image I get this:

5 tp-link partitions found on MTD device spi0.0
[    0.940000] Creating 5 MTD partitions on "spi0.0":
[    0.940000] 0x000000000000-0x000000020000 : "u-boot"
[    0.950000] 0x000000020000-0x0000000f7600 : "kernel"
[    0.950000] mtd: partition "kernel" must either start or end on erase block boundary or be smaller than an erase block -- forcing read-only
[    0.970000] 0x0000000f7600-0x000000ff0000 : "rootfs"
[    0.970000] mtd: partition "rootfs" must either start or end on erase block boundary or be smaller than an erase block -- forcing read-only
[    0.990000] mtd: partition "rootfs" set to be root filesystem
[    0.990000] mtd: partition "rootfs_data" created automatically, ofs=260000, len=D90000
[    1.000000] 0x000000260000-0x000000ff0000 : "rootfs_data"
[    1.010000] 0x000000ff0000-0x000001000000 : "art"
[    1.020000] 0x000000020000-0x000000ff0000 : "firmware"

but when flashing a compiled jffs2 I get:

[    0.940000] Creating 5 MTD partitions on "spi0.0":
[    0.940000] 0x000000000000-0x000000020000 : "u-boot"
[    0.950000] 0x000000020000-0x000000100000 : "kernel"
[    0.960000] 0x000000100000-0x000000ff0000 : "rootfs"
[    0.960000] mtd: partition "rootfs" set to be root filesystem
[    0.970000] split_squashfs: no squashfs found in "spi0.0"
[    0.970000] 0x000000ff0000-0x000001000000 : "art"
[    0.980000] 0x000000020000-0x000000ff0000 : "firmware"

This looks healthier even though my "kernel" partition is on 0x000000020000-0x000000100000, while OP's is on 0x000000020000-0x000000160000.

Whats going on? My "kernel" partition is smaller, how can this be?

I have also backed up the ART from both the squash and the jffs2 installed images. They both are identical to the ART I have on the initial image I pulled from the 4MB chip. So the ART is present, but quite possibly on the wrong offset, taken the difference on the offset initially, located at  0x3f1000 and forward on my board, and 0x3f0000 and forward for OP. I could really use someones input with a backup of their ART partition.

DIR-825.b2 @ 840MHz (16/128MB) : PC Engines Alix6e2 : WR703N (8/64MB) : MR11U (8/64MB) : WR512-3GN (128MB)

Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

xopal wrote:

Hi Lennong

Make directory in your /home/lennong/images/ap99

Do not compile as a root user

                        -Map u-boot.map -o u-boot
mips-linux-uclibc-objcopy --gap-fill=0xff -O srec u-boot u-boot.srec
mips-linux-uclibc-objcopy --gap-fill=0xff -O binary u-boot u-boot.bin
make[1]: Leaving directory `/home/xopal/uboot/ap99/boot/u-boot'
cp /home/xopal/uboot/build/../ap99/boot/u-boot/u-boot.bin /home/xopal/uboot/build/../images/ap99/u-boot.bin

Looking at your print it seems to me that you are not getting the u-boot.bin copied to that folder. ..."/home/xopal/uboot/build/../images/ap99/u-boot.bin" indicates another location. Or?

DIR-825.b2 @ 840MHz (16/128MB) : PC Engines Alix6e2 : WR703N (8/64MB) : MR11U (8/64MB) : WR512-3GN (128MB)

Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

make[1]: Leaving directory `/home/xopal/uboot/ap99/boot/u-boot'
cp /home/xopal/uboot/build/../ap99/boot/u-boot/u-boot.bin /home/xopal/uboot/build/../images/ap99/u-boot.bin
xopal@xopal-OEM:~/uboot/build$ cd ../images/ap99/
xopal@xopal-OEM:~/uboot/images/ap99$ ls
u-boot.bin
xopal@xopal-OEM:~/uboot/images/ap99$ ls -la
total 136
drwxrwxr-x 2 xopal xopal   4096 2011-11-24 05:30 .
drwxrwxr-x 3 xopal xopal   4096 2011-11-24 05:09 ..
-rwxr-xr-x 1 xopal xopal 127180 2012-02-06 18:41 u-boot.bin
xopal@xopal-OEM:~/uboot/images/ap99$

How do you manage to put uboot.bin + firmware + art.bin stuff in one file ?, let's check part four of OP tutorial, i think you miss something.

Sry for my english.

Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

xopal wrote:
make[1]: Leaving directory `/home/xopal/uboot/ap99/boot/u-boot'
cp /home/xopal/uboot/build/../ap99/boot/u-boot/u-boot.bin /home/xopal/uboot/build/../images/ap99/u-boot.bin
xopal@xopal-OEM:~/uboot/build$ cd ../images/ap99/
xopal@xopal-OEM:~/uboot/images/ap99$ ls
u-boot.bin
xopal@xopal-OEM:~/uboot/images/ap99$ ls -la
total 136
drwxrwxr-x 2 xopal xopal   4096 2011-11-24 05:30 .
drwxrwxr-x 3 xopal xopal   4096 2011-11-24 05:09 ..
-rwxr-xr-x 1 xopal xopal 127180 2012-02-06 18:41 u-boot.bin
xopal@xopal-OEM:~/uboot/images/ap99$

How do you manage to put uboot.bin + firmware + art.bin stuff in one file ?, let's check part four of OP tutorial, i think you miss something.

Sry for my english.

Strange that you get it copied there and I am not. I have tried both with user and root, same result. However, the u-boot.bin is available in the directory it is supposed to be copied from.

As for the editing the image, its all done in winhex. Very simple and straightforward. Only threshold is to deal with the offsets and hex values contra decimal.
I'm at the moment at my local soldering guy so I will know the result in a ew moments. One of few good things about Indonesia is that labor costs nothing, I get soldering done with airguns and good tools for $1/hour. No use of risking itself then..

DIR-825.b2 @ 840MHz (16/128MB) : PC Engines Alix6e2 : WR703N (8/64MB) : MR11U (8/64MB) : WR512-3GN (128MB)

Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

You have to start all over again, check if one of your folder occupied by root, if it does , you can't do anything it was locked by root.

Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

xopal wrote:

You have to start all over again, check if one of your folder occupied by root, if it does , you can't do anything it was locked by root.

I actually did solved it, I did a mistake but now its solved. Thanks!

DIR-825.b2 @ 840MHz (16/128MB) : PC Engines Alix6e2 : WR703N (8/64MB) : MR11U (8/64MB) : WR512-3GN (128MB)

Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

Ok, with the proper offset of ART I'm up and running. Wifi is up now. Still have that strange differences between squash and jffs2 though. As said before, my "kernel" is all over the place. I think it perhaps got something to do with my compiling. From here on it's more related to the "firmware" partition, u-boot and ART is healthy, so no more de/resoldering. I'm happy with 16MB/64MB on this thing, did this mostly as a practice object before attacking the MR11U and 703N. It seems a bit hard to find the GPL code for that though. If anyone has seen that around please notify me.

Thanks for the input!

DIR-825.b2 @ 840MHz (16/128MB) : PC Engines Alix6e2 : WR703N (8/64MB) : MR11U (8/64MB) : WR512-3GN (128MB)

Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

Lennong wrote:

...... I'm happy with 16MB/64MB on this thing, did this mostly as a practice object before attacking the MR11U and 703N. It seems a bit hard to find the GPL code for that though. If anyone has seen that around please notify me.

Thanks for the input!

https://forum.openwrt.org/viewtopic.php?pid=156369#p156369
But I don't know how to use it.

Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

Hi twinclouds,

The GPL code file is too big and my internet is going slow, can you describe what is the content of that file. I don't need the toolchain part i just need the uboot source., can you upload it some where ?.

Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

xopal wrote:

Hi twinclouds,

The GPL code file is too big and my internet is going slow, can you describe what is the content of that file. I don't need the toolchain part i just need the uboot source., can you upload it some where ?.

Indeed, they are very large.  Under the top directory GPL/branch_hornet_linux/, there are the following subdirectories:

drwxr-xr-x  5 fling fling     4096 2011-12-11 18:49 ap121
drwxr-xr-x 18 fling fling     4096 2011-11-09 01:21 apps
drwxr-xr-x  2 fling fling     4096 2011-12-11 18:49 filesystem
drwxr-xr-x  4 fling fling     4096 2011-11-09 01:20 kernel_modules
drwxr-xr-x  2 fling fling     4096 2011-11-09 01:20 toolchain
drwxr-xr-x  3 fling fling     4096 2011-11-10 01:50 toolchain_src
drwxr-xr-x  5 fling fling     4096 2011-12-11 18:49 util
drwxr-xr-x  3 fling fling     4096 2011-11-09 01:21 web_server

Do you know which one will be useful for you?  I would guess ap121 but it will be 82 MB after compression.

Moreover, which will be a good place for uploading?

Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

ap121 is ok, check your message box to access my ftp server

50 (edited by twinclouds 2012-02-16 06:48:40)

Re: TP-Link MR3420v1 16M flash /64M Memory hardware mod with uboot bin

I received a moded 703n (8M/64M).  This guy simply used original 4M uboot and it works fine with my 8M rootfs.  What is the difference between 4M and 8M uboot?

Edit (02/15/2012):
I figured this out.  A 4M uboot cannot write anything longer than 4M.  However, the Openwrt can detect flash memory size on its own.  Thus, to flash a rootfs larger than 4M, one need to first install a 4M rootfs and then use ssh or luci to install a new rootfs, which can be larger than 4M.  A two step process but not too bad.