These are not errors, just warnings from Makefile.

Just a small sneak peak from upcoming, new version:

*********************************************
*        U-Boot 1.1.4  (Dec  1 2013)        *
*********************************************

AP121 (AR9331) U-Boot for TL-MR3020

DRAM:   64 MB DDR 16-bit
FLASH:  Winbond W25Q128 (16 MB)
CLOCKS: 400/400/200/33 MHz (CPU/RAM/AHB/SPI)

LED on during eth initialization...

Hit any key to stop autobooting:  0

uboot> printclocks
Current clocks (approximated):
- CPU: 400 MHz
- RAM: 400 MHz
- AHB: 200 MHz
- SPI:  33 MHz

Clocks configuration stored in FLASH (approximated):
- CPU: 200 MHz
- RAM: 200 MHz
- AHB: 200 MHz
- SPI:  33 MHz

Reference clock: 25 MHz
uboot> help setclocks
setclocks range refdiv divint outdiv cpu_div ram_div ahb_div spi_div
        - calculates and stores CPU_PLL_CONFIG and CLOCK_CONTROL registers in FLASH
        - default configuration for 400/400/200/33 MHz:
          0 1 32 1 1 1 2 3 (25 MHz ref, PLL -> ((25 / 1) * 32) / (1 / 2 ^ 1) = 400 MHz)
          0 1 20 1 1 1 2 3 (40 MHz ref, PLL -> ((40 / 1) * 20) / (1 / 2 ^ 1) = 400 MHz)

        - formulas for PLL and clocks calculations:
          PLL = ((ref / refdiv) * divint) / (1 / (2 ^ outdiv))
          CPU = PLL / cpu_div
          RAM = PLL / ram_div
          AHB = PLL / ahb_div
          SPI = AHB / (2 * spi_div)

          *ref - reference clock (25 or 40 MHz)

New functionalities:
- O/C recovery mode (press and hold reset button during power up == boot with default clocks)
- configuration for CPU/RAM/AHB and SPI clocks can be stored in FLASH and changed in U-Boot console
- more commands for compressed U-Boot images
- solved: OFW kernel loading bug
- solved: setmac command
- AR9341 support
- etc.

Can you give me the uboot image download link?

Is AR9341 supported?
I checked the makefile and it doesn't seem to be there.

Hi pepe2k

I just wanted to thank you for your work on the modification from U-boot.

I'm only playing with a wr703 for two weeks now, before i had one i figured out that
the version off the original bootloader was very critical and you need a serial connection
to fix things if something went wrong, not a thing i want to do.

So i made a 'roadmap' on how to program my new 16mb flash with U-boot (yours), MAC
data (what a waste of flash a whole 64kb block gone for just a few MAC adress bytes),
firmware (OpenWRT) and ART data.

After programming my flash and soldering it back in i noticed that my editor had changed
all 0x00 in 0x20 in the ART section, damm no wifi.

So i made a new ART 64kb block, booted the wr703 with a 3sec hold on the reset switch,
and was able to upload the new ART block throught a normal web gui...

Wow!, this is super! user friendly, it looks that if you use your modified U-boot there is almost
no way to brick your router...

Grtzz  Mark

Censored
datasheet

Censored
datasheet

Hello Mark!

I'm glad that you like it!
Have you tried O/C already (this functionality is available only in source, but if you want I can build an image for you)?

Regards!

pepe2k wrote:

Hello Mark!

I'm glad that you like it!
Have you tried O/C already (this functionality is available only in source, but if you want I can build an image for you)?

Regards!

No i had no time to play with it and i still have to install a toolchain first, one of the first things i want to
try is to run Oscam on my wr703
But if you could make an Uboot image with o/c functionality i would be glad to test, how can i set frequency's?
or is this set during compile? if so could you set the maximum stable settings...

dziękuję  Mark

Mark_V wrote:

pepe2k wrote:

Hello Mark!

I'm glad that you like it!
Have you tried O/C already (this functionality is available only in source, but if you want I can build an image for you)?

Regards!

No i had no time to play with it and i still have to install a toolchain first, one of the first things i want to
try is to run Oscam on my wr703
But if you could make an Uboot image with o/c functionality i would be glad to test, how can i set frequency's?
or is this set during compile? if so could you set the maximum stable settings...

dziękuję  Mark

Today I pushed new functionality for PLL/clocks changing, with predefined list of available configurations.
Just run "setclocks" command and you will see something like this:

uboot> setcl
Current clocks (approximated):
- CPU: 400 MHz
- RAM: 400 MHz
- AHB: 200 MHz
- SPI:  33 MHz
- REF:  25 MHz

Available PLL and clocks configurations: 23

      | CPU | RAM | AHB | SPI | [ ]
  ---------------------------------
   1. | 200 | 200 | 100 |  25 | [ ]
   2. | 200 | 200 | 200 |  33 | [ ]
   3. | 225 | 225 | 112 |  28 | [ ]
   4. | 225 | 225 | 225 |  28 | [ ]
   5. | 250 | 250 | 125 |  31 | [ ]
   6. | 250 | 250 | 250 |  31 | [ ]
   7. | 300 | 300 | 150 |  25 | [ ]
   8. | 325 | 325 | 162 |  27 | [ ]
   9. | 350 | 350 | 175 |  29 | [ ]
  10. | 360 | 360 | 180 |  30 | [ ]
  11. | 400 | 400 | 200 |  33 | [ ]
  12. | 412 | 412 | 206 |  34 | [ ]
  13. | 425 | 425 | 212 |  35 | [ ]
  14. | 437 | 437 | 218 |  27 | [ ]
  15. | 450 | 450 | 225 |  28 | [ ]
  16. | 460 | 460 | 230 |  29 | [ ]
  17. | 475 | 475 | 237 |  30 | [ ]
  18. | 487 | 487 | 243 |  30 | [ ]
  19. | 500 | 500 | 250 |  31 | [ ]
  20. | 500 | 250 | 250 |  31 | [ ]
  21. | 525 | 262 | 131 |  33 | [ ]
  22. | 560 | 280 | 140 |  35 | [ ]
  23. | 600 | 300 | 200 |  33 | [ ]

[*] = currently selected profile (stored in FLASH).
All clocks in MHz, run 'setclocks X' to choose one.

** Notice:
   you should always make a backup of your device
   entire FLASH content before making any changes

Using "setclocks X" you can choose profile and save it in FLASH. After reboot, the device will use new clocks configuration.

If something goes wrong (e.g. device won't start)... there is a recovery mode: remove power cable, push and hold the "reset" button and plug the power cable again (still holding reset button). The device will start with default clocks (400/400/200 MHz) and you will be able to remove ("clearclocks") or choose other configuration.

And here is an image for WR703N (tested): http://www.tech-blog.pl/pliki/u-boot_mo … 012014.rar

Have a nice... overclocking time!

Mark_V wrote:

pepe2k wrote:

Hello Mark!

I'm glad that you like it!
Have you tried O/C already (this functionality is available only in source, but if you want I can build an image for you)?

Regards!

No i had no time to play with it and i still have to install a toolchain first, one of the first things i want to
try is to run Oscam on my wr703
But if you could make an Uboot image with o/c functionality i would be glad to test, how can i set frequency's?
or is this set during compile? if so could you set the maximum stable settings...

dziękuję  Mark

Today I pushed new functionality for PLL/clocks changing, with predefined list of available configurations.
Just run "setclocks" command and you will see something like this:

uboot> setcl
Current clocks (approximated):
- CPU: 400 MHz
- RAM: 400 MHz
- AHB: 200 MHz
- SPI:  33 MHz
- REF:  25 MHz

Available PLL and clocks configurations: 23

      | CPU | RAM | AHB | SPI | [ ]
  ---------------------------------
   1. | 200 | 200 | 100 |  25 | [ ]
   2. | 200 | 200 | 200 |  33 | [ ]
   3. | 225 | 225 | 112 |  28 | [ ]
   4. | 225 | 225 | 225 |  28 | [ ]
   5. | 250 | 250 | 125 |  31 | [ ]
   6. | 250 | 250 | 250 |  31 | [ ]
   7. | 300 | 300 | 150 |  25 | [ ]
   8. | 325 | 325 | 162 |  27 | [ ]
   9. | 350 | 350 | 175 |  29 | [ ]
  10. | 360 | 360 | 180 |  30 | [ ]
  11. | 400 | 400 | 200 |  33 | [ ]
  12. | 412 | 412 | 206 |  34 | [ ]
  13. | 425 | 425 | 212 |  35 | [ ]
  14. | 437 | 437 | 218 |  27 | [ ]
  15. | 450 | 450 | 225 |  28 | [ ]
  16. | 460 | 460 | 230 |  29 | [ ]
  17. | 475 | 475 | 237 |  30 | [ ]
  18. | 487 | 487 | 243 |  30 | [ ]
  19. | 500 | 500 | 250 |  31 | [ ]
  20. | 500 | 250 | 250 |  31 | [ ]
  21. | 525 | 262 | 131 |  33 | [ ]
  22. | 560 | 280 | 140 |  35 | [ ]
  23. | 600 | 300 | 200 |  33 | [ ]

[*] = currently selected profile (stored in FLASH).
All clocks in MHz, run 'setclocks X' to choose one.

** Notice:
   you should always make a backup of your device
   entire FLASH content before making any changes

Using "setclocks X" you can choose profile and save it in FLASH. After reboot, the device will use new clocks configuration.

If something goes wrong (e.g. device won't start)... there is a recovery mode: remove power cable, push and hold the "reset" button and plug the power cable again (still holding reset button). The device will start with default clocks (400/400/200 MHz) and you will be able to remove ("clearclocks") or choose other configuration.

And here is an image for WR703N (tested): http://www.tech-blog.pl/pliki/u-boot_mo … 012014.rar

Have a nice... overclocking time!

By using instructions found in the ar7242-manual, now i can make my device changing pll clocks without rebooting device, in real time!
without error in kernel also with working wifi(or ethernet) connection(via putty and io tool)

[...]

now we need to do something with the kernel, also desync the speed on UART...
probably kernel does not support overclocking in real time

By using instructions found in the ar7242-manual, now i can make my device changing pll clocks without rebooting device, in real time!
without error in kernel also with working wifi(or ethernet) connection(via putty and io tool)

The secret is simple, no need to immediately set the required frequency to CPU!
You just need to gently (bit by bit) to switch to the target PLL value.

for example default value for 400_400_200(ar724x):

root@OpenWrt:~# io -4 0x18050000
18050000:  00040828
root@OpenWrt:~#
root@OpenWrt:~# time sleep 1 <= Feels Like, one seconds has passed
real    0m 1.00s
user    0m 0.00s
sys     0m 0.00s
root@OpenWrt:~#

try to downgrade the pll(gently):

#!/bin/sh
io -4 0x18050000 0x50828 && \ <= base value 0x40828 swith to Bypass PLL(bit16) 400_400_200
io -4 0x18050000 0x50827 && \
io -4 0x18050000 0x50826 && \
io -4 0x18050000 0x50825 && \
io -4 0x18050000 0x50824 && \
io -4 0x18050000 0x50823 && \
io -4 0x18050000 0x50822 && \
io -4 0x18050000 0x50821 && \
io -4 0x18050000 0x50820 && \
io -4 0x18050000 0x5081f && \
io -4 0x18050000 0x5081e && \
io -4 0x18050000 0x5081d && \
io -4 0x18050000 0x5081c && \
io -4 0x18050000 0x5081b && \
io -4 0x18050000 0x5081a && \
io -4 0x18050000 0x50819 && \
io -4 0x18050000 0x50818 && \
io -4 0x18050000 0x50817 && \
io -4 0x18050000 0x50816 && \
io -4 0x18050000 0x50815 && \
io -4 0x18050000 0x50814 && \
io -4 0x18050000 0x50813 && \
io -4 0x18050000 0x50812 && \
io -4 0x18050000 0x50811 && \
io -4 0x18050000 0x50810 && \ <=160_160_80
io -4 0x18050000 0x5080f      <= unknown, minimum for me, if less - CPU will reboot

#===overclocking===
#io -4 0x18050000 0x50829 && \
#io -4 0x18050000 0x5082a && \
#io -4 0x18050000 0x5082b && \
#io -4 0x18050000 0x5082c && \
#io -4 0x18050000 0x5082d && \
#io -4 0x18050000 0x5082e && \
#io -4 0x18050000 0x5082f && \
#io -4 0x18050000 0x50830 && \
#io -4 0x18050000 0x50831      <= 487_487_243 maximum for me, if more - CPU will reboot

test sleep command(with minimum pll = 0x5080f):

root@OpenWrt:~# time sleep 1 <= Feels Like,!three! seconds has passed
real    0m 1.00s
user    0m 0.00s
sys     0m 0.00s
root@OpenWrt:~#

now we need to do something with the kernel, also desync the speed on UART...
probably kernel does not support overclocking in real time

Are you following the instruction from page 51 (below) or 22... or do you make only one write to the CPU_PLL_CONFIG register (0x18050000)?

To update the PLL, following is an example:
...

Are you checking/polling bit "UPDATING" during this process? There is also a statement that CPU resets during switch from REF_CLK to clock from PLL (page 22).

0 CLOCK_SWITCH Clock switch enables switching from the basic REF_CLK to the CPU_PLL
clock after the CPU_PLL clock is stable

I can see that in your previous post, all hex values for CPU_PLL_CONFIG register have BYPASS bit set to 1, was it a mistake?

If the CPU_CLOCK_CONTROL register bit
RESET_SWITCH (bit [1]) is set to 1, jump
directly to Step 5.