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Topic: AR7241 two flash chips? (TL-WR841N v7)

The content of this topic has been archived on 6 Apr 2018. There are no obvious gaps in this topic, but there may still be some posts missing at the end.

Does anyone know if the AR7241 supports two SPI flash chips?

I noticed that various Buffalo devices (WZR-HP-AG300H, WZR-HP-G300NH2, WZR-HP-G450H) have two devices.  They do this by  the code (mach-wzr-hp-ag300h.c) calling ath79_register_m25p80_multi() rather than the normal ath79_register_m25p80().  When you follow this through I spotted this code (arch/mips/include/asm/mach-ath79/ar71xx_regs.h)

#define AR71XX_SPI_IOC_DO       BIT(0)  /* Data Out pin */
#define AR71XX_SPI_IOC_CLK      BIT(8)  /* CLK pin */
#define AR71XX_SPI_IOC_CS(n)    BIT(16 + (n))
#define AR71XX_SPI_IOC_CS0      AR71XX_SPI_IOC_CS(0)
#define AR71XX_SPI_IOC_CS1      AR71XX_SPI_IOC_CS(1)
#define AR71XX_SPI_IOC_CS2      AR71XX_SPI_IOC_CS(2)
#define AR71XX_SPI_IOC_CS_ALL   (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | \
                                 AR71XX_SPI_IOC_CS2)

So I tried soldering a Spansion 25FL064K on top of the cFeng 25F32 in my TL-WR841N v7, with all the legs connected together except pin 1 (CS).    I patched the code to call ath79_register_m25p80_multi instead of the normal call in mach-tl-mr3x20.c (which is where the machine def for the WR841N v7 lives).  I then took CS on a flying lead and poked around the GPIO pins of the AR7241 while rebooting the router, looking for the boot messages to change.  But I always get this:

[    0.750000] ath79-spi ath79-spi: master is unqueued, this is deprecated
[    0.760000] m25p80 spi0.0: found en25q32b, expected m25p80
[    0.760000] m25p80 spi0.0: en25q32b (4096 Kbytes)
[    0.770000] 5 tp-link partitions found on MTD device spi0.0
[    0.770000] Creating 5 MTD partitions on "spi0.0":

So spi0.1 is never detected.

Then something dawned on me.  The Buffalo devices don't use the AR7241, they use other Atheros SoCs (eg AR7242).  I noticed there are no AR7241 devices in the ToH with more than 8MB flash.  So anyone know if the AR7241 supports two flash chips, and if so which pin is CS1?

Alternatively, is there an easy way to tell Linux to use a GPIO as CS not via the SPI controller?

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