I was *unsuccessful. Can you please point me in the right direction on how to capture the boot log? Any help will be greatly appreciated.
Answer the rest of my post.
if you can use a UART adapter you can boot openwrt in a minute, i have an idea of the board, the only thing that is missing in my mind is the two lte/4g slots.
make sure you use tx of the adapter on rx on the router, rx on the adapter to tx on the router, gnd to gnd, and no 3.3v at all.
Thanks for the reply. Is this the right cable?
Ok, I connected the cable as suggested. Rebooted the router. I am using Putty to collect the log but what's being pulsed to screen is gibrish. What am I doing wrong?
Wrong speed set in the terminal application, I'd guess.
Try 115200 8N1, if not, go for lower speeds.
Thank you! That sure did the trick. The log is too big. Is there a way to attach it? Could I email it to one of you guys?
Post it on pastebin, or split it up into several posts.
Error writing session log (raw mode) to file: putty.log
===================================================================
MT7621 stage1 code Mar 12 2015 14:43:30 (ASIC)
CPU=500000000 HZ BUS=166666666 HZ
==================================================================
Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x21100000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-1066Mhz ===
PLL4 FB_DL: 0xd, 1/0 = 518/506 35000000
PLL2 FB_DL: 0x12, 1/0 = 522/502 49000000
PLL3 FB_DL: 0x13, 1/0 = 518/506 4D000000
do DDR setting..[01F40000]
Apply DDR3 Setting...(use customer AC)
0 8 16 24 32 40 48 56 64 72 80 88 96 104 11 2 120
-------------------------------------------------------------------------- ------
0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0007:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0008:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0009:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000E:| 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
000F:| 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
0010:| 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
0011:| 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
0012:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0013:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DRAMC_DQSCTL1[0e0]=13000000
DRAMC_DQSGCTL[124]=80000033
rank 0 coarse = 15
rank 0 fine = 80
B:| 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0
opt_dle value:9
DRAMC_DDR2CTL[07c]=C287221D
DRAMC_PADCTL4[0e4]=000022B3
DRAMC_DQIDLY1[210]=09080809
DRAMC_DQIDLY2[214]=06080708
DRAMC_DQIDLY3[218]=09080707
DRAMC_DQIDLY4[21c]=09070B08
DRAMC_R0DELDLY[018]=00002223
==================================================================
RX DQS perbit delay software calibration
==================================================================
1.0-15 bit dq delay value
==================================================================
bit| 0 1 2 3 4 5 6 7 8 9
--------------------------------------
0 | 8 7 7 9 8 7 8 6 6 6
10 | 8 9 8 10 7 9
--------------------------------------
==================================================================
2.dqs window
x=pass dqs delay value (min~max)center
y=0-7bit DQ of every group
input delay:DQS0 =35 DQS1 = 34
==================================================================
bit DQS0 bit DQS1
0 (1~67)34 8 (1~65)33
1 (1~68)34 9 (0~66)33
2 (1~67)34 10 (1~67)34
3 (1~70)35 11 (2~66)34
4 (1~69)35 12 (1~68)34
5 (1~70)35 13 (1~66)33
6 (1~70)35 14 (1~68)34
7 (1~70)35 15 (1~67)34
==================================================================
3.dq delay value last
==================================================================
bit| 0 1 2 3 4 5 6 7 8 9
--------------------------------------
0 | 9 8 8 9 8 7 8 6 7 7
10 | 8 9 8 11 7 9
==================================================================
==================================================================
TX perbyte calibration
==================================================================
DQS loop = 15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqsdly_pass[0]=15, finish count=1
dqs_perbyte_dly.last_dqsdly_pass[1]=15, finish count=2
DQ loop=15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqdly_pass[0]=15, finish count=1
dqs_perbyte_dly.last_dqdly_pass[1]=15, finish count=2
byte:0, (DQS,DQ)=(8,8)
byte:1, (DQS,DQ)=(8,8)
DRAMC_DQODLY1[200]=88888888
DRAMC_DQODLY2[204]=88888888
20,data:88
[EMI] DRAMC calibration passed
===================================================================
MT7621 stage1 code done
CPU=500000000 HZ BUS=166666666 HZ
===================================================================
U-Boot 1.1.3 (Apr 11 2015 - 20:07:37)
SoC:MediaTek MT7621
DRAM: 512MB(448MB LowMem,64MB HighMem)
relocate_code Pointer at: 93fa8000
Config XHCI 40M PLL
flash manufacture id: ef, device id 40 18
Flash:W25Q128BV Size:16MB
*** Warning - bad CRC, using default environment
_______________________________________________________________
| ____ _ ____ |
| | _ \ __ _ _ __ __| | ___ _ __ __ _| __ ) _____ __ |
| | |_) / _` | '_ \ / _` |/ _ \| '__/ _` | _ \ / _ \ \/ / |
| | __/ (_| | | | | (_| | (_) | | | (_| | |_) | (_) > < |
| |_| \__,_|_| |_|\__,_|\___/|_| \__,_|____/ \___/_/\_\ |
| |
| PandoraBox Ralink/MTK Platform |
| The best solution for you |
| Copyright 2015 D-Team Technology Co.,Ltd. SZ |
| Board:AmazingBox |
| |
| ZBT-CN<zbt-china.com> |
|______________________________________________________________|
===============Board Info==================
CPU Frequency:880MHz
Detected Memory:320MiB
Bootloader Version:4.3.1.0
--------------------------------------------
ASIC MT7621A DualCore (MAC to MT7530 Mode)
DRAM_CONF_FROM: Auto-Detection
DRAM_TYPE: DDR3
DRAM bus: 16 bit
Xtal Mode=3 OCP Ratio=1/3
Flash component: SPI Flash
Date:Apr 11 2015 Time:20:07:37
============================================
icache: sets:256, ways:4, linesz:32 ,total:32KiB
dcache: sets:256, ways:4, linesz:32 ,total:32KiB
============================================
#Reset_MT7530
GSW VLAN:LLLW
GPIO_MODE init:
I2C:GPIO
UART_F:GPIO
GE2:GPIO
WDT_RST:GPIO
GPIO_MODE_REGs: 0x4853d
READY_LED_BIT:14.
Please choose the operation:
1: Load system code to SDRAM via TFTP.
2: Load system code then write to Flash via TFTP.
3: Boot system code via Flash (default).
4: Entr boot command line interface.
7: Load Boot Loader code then write to Flash via Serial.
9: Load Boot Loader code then write to Flash via TFTP. 0
3: System Boot system code via Flash.
Press Reset button enter upgrade mode!
## Booting image at bc050000 ...
Image Name: MIPS OpenWrt Linux-5.15.102
Image Type: MIPS Linux Kernel Image (uncompressed)
Data Size: 3017318 Bytes = 2.9 MB
Load Address: 80001000
Entry Point: 80001000
Verifying Checksum ... OK
OK
No initrd
## Transferring control to Linux (at address 80001000) ...
## Giving linux memsize in MB, 512
Use the </> button (in the post window) around the posted cli (putty) text.
See if you can interrupt the boot menu, and check what happens when you press and hold the reset button while powering on the device.
You could also try booting the wax202 initramfs from https://downloads.openwrt.org/releases/22.03.3/targets/ramips/mt7621/ using option 1 in u-boot.
My apologies. I have never done this ... when you say boot from that image. Do you mean to flash the router with the specified image, boot and capture?
This is about your posts, not the device.
Yes, and no, image will be in ram only, there will be no flashing.
Boot and explore.
Seems your device is a ZBT clone, see if any of the supported devices in the OpenWrt download dir matches the specs of the WS7915AX.
Boot that initramfs instead of the WAX202s.
Thank you. The WAX202 is almost identical. How can I boot from the image without flashing the router?
I already wrote it in on of the previous posts.
So, none of the information below is what you need?
=~=~=~=~=~=~=~=~=~=~=~= PuTTY log 2023.03.21 16:00:15 =~=~=~=~=~=~=~=~=~=~=~=
===================================================================
MT7621 stage1 code Mar 12 2015 14:43:30 (ASIC)
CPU=500000000 HZ BUS=166666666 HZ
==================================================================
Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x21100000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-1066Mhz ===
PLL4 FB_DL: 0xd, 1/0 = 518/506 35000000
PLL2 FB_DL: 0x12, 1/0 = 522/502 49000000
PLL3 FB_DL: 0x13, 1/0 = 516/508 4D000000
do DDR setting..[01F40000]
Apply DDR3 Setting...(use customer AC)
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120
--------------------------------------------------------------------------------
0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0007:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0008:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0009:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
000E:| 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
000F:| 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
0010:| 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
0011:| 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
0012:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0013:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DRAMC_DQSCTL1[0e0]=13000000
DRAMC_DQSGCTL[124]=80000033
rank 0 coarse = 15
rank 0 fine = 80
B:| 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0
opt_dle value:9
DRAMC_DDR2CTL[07c]=C287221D
DRAMC_PADCTL4[0e4]=000022B3
DRAMC_DQIDLY1[210]=09080709
DRAMC_DQIDLY2[214]=05080708
DRAMC_DQIDLY3[218]=0A090708
DRAMC_DQIDLY4[21c]=0A080B09
DRAMC_R0DELDLY[018]=00002323
==================================================================
RX DQS perbit delay software calibration
==================================================================
1.0-15 bit dq delay value
==================================================================
bit| 0 1 2 3 4 5 6 7 8 9
--------------------------------------
0 | 8 7 7 9 8 7 8 5 6 7
10 | 8 9 8 10 7 9
--------------------------------------
==================================================================
2.dqs window
x=pass dqs delay value (min~max)center
y=0-7bit DQ of every group
input delay:DQS0 =35 DQS1 = 35
==================================================================
bit DQS0 bit DQS1
0 (1~68)34 8 (1~66)33
1 (1~69)35 9 (2~68)35
2 (1~68)34 10 (1~68)34
3 (1~69)35 11 (2~66)34
4 (1~70)35 12 (0~68)34
5 (1~69)35 13 (1~67)34
6 (1~70)35 14 (1~68)34
7 (0~70)35 15 (1~67)34
==================================================================
3.dq delay value last
==================================================================
bit| 0 1 2 3 4 5 6 7 8 9
--------------------------------------
0 | 9 7 8 9 8 7 8 5 8 7
10 | 9 10 9 11 8 10
==================================================================
==================================================================
TX perbyte calibration
==================================================================
DQS loop = 15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqsdly_pass[0]=15, finish count=1
dqs_perbyte_dly.last_dqsdly_pass[1]=15, finish count=2
DQ loop=15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqdly_pass[0]=15, finish count=1
dqs_perbyte_dly.last_dqdly_pass[1]=15, finish count=2
byte:0, (DQS,DQ)=(8,8)
byte:1, (DQS,DQ)=(8,8)
DRAMC_DQODLY1[200]=88888888
DRAMC_DQODLY2[204]=88888888
20,data:88
[EMI] DRAMC calibration passed
===================================================================
MT7621 stage1 code done
CPU=500000000 HZ BUS=166666666 HZ
===================================================================
U-Boot 1.1.3 (Apr 11 2015 - 20:07:37)
SoC:MediaTek MT7621
DRAM: 512MB(448MB LowMem,64MB HighMem)
relocate_code Pointer at: 93fa8000
Config XHCI 40M PLL
flash manufacture id: ef, device id 40 18
Flash:W25Q128BV Size:16MB
*** Warning - bad CRC, using default environment
_______________________________________________________________
| ____ _ ____ |
| | _ \ __ _ _ __ __| | ___ _ __ __ _| __ ) _____ __ |
| | |_) / _` | '_ \ / _` |/ _ \| '__/ _` | _ \ / _ \ \/ / |
| | __/ (_| | | | | (_| | (_) | | | (_| | |_) | (_) > < |
| |_| \__,_|_| |_|\__,_|\___/|_| \__,_|____/ \___/_/\_\ |
| |
| PandoraBox Ralink/MTK Platform |
| The best solution for you |
| Copyright 2015 D-Team Technology Co.,Ltd. SZ |
| Board:AmazingBox |
| |
| ZBT-CN<zbt-china.com> |
|______________________________________________________________|
===============Board Info==================
CPU Frequency:880MHz
Detected Memory:320MiB
Bootloader Version:4.3.1.0
--------------------------------------------
ASIC MT7621A DualCore (MAC to MT7530 Mode)
DRAM_CONF_FROM: Auto-Detection
DRAM_TYPE: DDR3
DRAM bus: 16 bit
Xtal Mode=3 OCP Ratio=1/3
Flash component: SPI Flash
Date:Apr 11 2015 Time:20:07:37
============================================
icache: sets:256, ways:4, linesz:32 ,total:32KiB
dcache: sets:256, ways:4, linesz:32 ,total:32KiB
============================================
#Reset_MT7530
GSW VLAN:LLLW
GPIO_MODE init:
I2C:GPIO
UART_F:GPIO
GE2:GPIO
WDT_RST:GPIO
GPIO_MODE_REGs: 0x4853d
READY_LED_BIT:14.
Please choose the operation:
1: Load system code to SDRAM via TFTP.
2: Load system code then write to Flash via TFTP.
3: Boot system code via Flash (default).
4: Entr boot command line interface.
7: Load Boot Loader code then write to Flash via Serial.
9: Load Boot Loader code then write to Flash via TFTP.
0
3: System Boot system code via Flash.
Press Reset button enter upgrade mode!
## Booting image at bc050000 ...
Image Name: MIPS OpenWrt Linux-5.15.102
Image Type: MIPS Linux Kernel Image (uncompressed)
Data Size: 3017318 Bytes = 2.9 MB
Load Address: 80001000
Entry Point: 80001000
Verifying Checksum ... OK
OK
No initrd
## Transferring control to Linux (at address 80001000) ...
## Giving linux memsize in MB, 512
You've already posted it once, and it contains some usable info, but you'll need to collect more.
I am having some difficulties finding a device with MT7621/ Dual-core/880Mhz MT7915DN MT7905DN.
The Totolink R5000 is the closest but doesn't have the MT7905DN.
do not warry all have the same radio, is an mt7915 DBDC. all devices are the same, try to boot an image with nor flash, wax202 have nand. so you can use cudy ax, tenbay, asus ax1800, totolink, all this device have the same radio. but do not flash the image, just try initram.bin
i can help with radio, mt7915, the switch, DTS for this, but i cannot help on lte/4g side, so if expert come in we can easy add support.
1 Like
Please, please edit your posts to put the logs in code tags, this is unreadable as is.
Code tags are Preformatted text
With readable logs folks can assist