Hello.
Having U-boot is working well on OpenWrt driven board. Being compiled using OpenWrt make
command it works fine.
But trying to rebuild it with debugging information in build_dir/target...
folder for debugging purposes it fails on initcall_run_list()
function at lib/initcall.c:17
:
Start address 0x87800000, load size 592375
Transfer rate: 69 KB/sec, 12341 bytes/write.
(gdb) s
reset () at arch/arm/cpu/armv7/start.S:40
40 b save_boot_params
(gdb) delete
(gdb) b initcall_run_list
Breakpoint 1 at 0x87856dec: file lib/initcall.c, line 17.
(gdb) s
save_boot_params () at arch/arm/cpu/armv7/start.S:116
116 b save_boot_params_ret @ back to my caller
(gdb) c
Continuing.
Breakpoint 1, initcall_run_list (init_sequence=init_sequence@entry=0x87870048 <init_sequence_f>) at lib/initcall.c:17
17 for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
(gdb) s
14 {
(gdb) s
17 for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
(gdb) s
21 if (gd->flags & GD_FLG_RELOC)
(gdb) s
22 reloc_ofs = gd->reloc_off;
(gdb) s
27 if (gd->flags & GD_FLG_RELOC)
(gdb) s
31 ret = (*init_fnc_ptr)();
(gdb) s
^Cundefined_instruction () at arch/arm/lib/vectors.S:229
229 get_bad_stack
same trying to walk until there by single steps:
Start address 0x87800000, load size 592375
Transfer rate: 69 KB/sec, 12341 bytes/write.
(gdb) s
reset () at arch/arm/cpu/armv7/start.S:40
40 b save_boot_params
(gdb) s
save_boot_params () at arch/arm/cpu/armv7/start.S:116
116 b save_boot_params_ret @ back to my caller
(gdb)
save_boot_params_ret () at arch/arm/cpu/armv7/start.S:56
56 mrs r0, cpsr
(gdb)
57 and r1, r0, #0x1f @ mask mode bits
(gdb)
58 teq r1, #0x1a @ test for HYP mode
(gdb)
59 bicne r0, r0, #0x1f @ clear all mode bits
(gdb)
60 orrne r0, r0, #0x13 @ set SVC mode
(gdb) s
61 orr r0, r0, #0xc0 @ disable FIQ and IRQ
(gdb) s
62 msr cpsr,r0
(gdb) s
71 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register
(gdb) s
72 bic r0, #CR_V @ V = 0
(gdb) s
73 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register
(gdb) s
76 ldr r0, =_start
(gdb) s
77 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
(gdb) s
82 bl cpu_init_cp15
(gdb) s
cpu_init_cp15 () at arch/arm/cpu/armv7/start.S:139
139 mov r0, #0 @ set up for MCR
(gdb) s
140 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
(gdb) s
141 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
(gdb) s
142 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
(gdb) s
143 mcr p15, 0, r0, c7, c10, 4 @ DSB
(gdb) s
144 mcr p15, 0, r0, c7, c5, 4 @ ISB
(gdb) s
149 mrc p15, 0, r0, c1, c0, 0
(gdb) s
150 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
(gdb) s
151 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
(gdb) s
152 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
(gdb) s
153 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
(gdb) s
157 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
(gdb) s
159 mcr p15, 0, r0, c1, c0, 0
(gdb) s
190 mov r5, lr @ Store my Caller
(gdb) s
191 mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR)
(gdb) s
192 mov r3, r1, lsr #20 @ get variant field
(gdb) s
193 and r3, r3, #0xf @ r3 has CPU variant
(gdb) s
194 and r4, r1, #0xf @ r4 has CPU revision
(gdb) s
195 mov r2, r3, lsl #4 @ shift variant field for combined value
(gdb) s
196 orr r2, r4, r2 @ r2 has combined CPU variant + revision
(gdb) s
298 mov pc, r5 @ back to my caller
(gdb) s
save_boot_params_ret () at arch/arm/cpu/armv7/start.S:84
84 bl cpu_init_crit
(gdb) s
cpu_init_crit () at arch/arm/cpu/armv7/start.S:318
318 b lowlevel_init @ go setup pll,mux,memory
(gdb) s
lowlevel_init () at arch/arm/cpu/armv7/lowlevel_init.S:32
32 ldr sp, =CONFIG_SYS_INIT_SP_ADDR
(gdb) s
lowlevel_init () at arch/arm/cpu/armv7/lowlevel_init.S:34
34 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
(gdb) s
45 sub sp, sp, #GD_SIZE
(gdb) s
46 bic sp, sp, #7
(gdb) s
47 mov r9, sp
(gdb) s
53 push {ip, lr}
(gdb) s
68 bl s_init
(gdb)
s_init () at arch/arm/cpu/armv7/mx6/soc.c:588
588 if (is_mx6sx() || is_mx6ul() || is_mx6ull())
(gdb) s
get_cpu_rev () at arch/arm/cpu/armv7/mx6/soc.c:69
69 u32 reg = readl(&anatop->digprog_sololite);
(gdb) s
70 u32 type = ((reg >> 16) & 0xff);
(gdb)
73 if (type != MXC_CPU_MX6SL) {
(gdb)
74 reg = readl(&anatop->digprog);
(gdb)
76 cfg = readl(&scu->config) & 3;
(gdb)
77 type = ((reg >> 16) & 0xff);
(gdb)
76 cfg = readl(&scu->config) & 3;
(gdb)
78 if (type == MXC_CPU_MX6DL) {
(gdb)
83 if (type == MXC_CPU_MX6Q) {
(gdb)
89 major = ((reg >> 8) & 0xff);
(gdb)
90 if ((major >= 1) &&
(gdb)
67 {
(gdb)
98 return (type << 12) | (reg + (0x10 * (major + 1)));
(gdb)
99 }
(gdb)
get_cpu_rev () at arch/arm/cpu/armv7/mx6/soc.c:69
69 u32 reg = readl(&anatop->digprog_sololite);
(gdb)
70 u32 type = ((reg >> 16) & 0xff);
(gdb)
73 if (type != MXC_CPU_MX6SL) {
(gdb)
74 reg = readl(&anatop->digprog);
(gdb)
76 cfg = readl(&scu->config) & 3;
(gdb)
77 type = ((reg >> 16) & 0xff);
(gdb)
76 cfg = readl(&scu->config) & 3;
(gdb)
78 if (type == MXC_CPU_MX6DL) {
(gdb)
83 if (type == MXC_CPU_MX6Q) {
(gdb)
89 major = ((reg >> 8) & 0xff);
(gdb)
90 if ((major >= 1) &&
(gdb)
67 {
(gdb)
98 return (type << 12) | (reg + (0x10 * (major + 1)));
(gdb)
99 }
(gdb)
get_cpu_rev () at arch/arm/cpu/armv7/mx6/soc.c:69
69 u32 reg = readl(&anatop->digprog_sololite);
(gdb)
70 u32 type = ((reg >> 16) & 0xff);
(gdb)
73 if (type != MXC_CPU_MX6SL) {
(gdb)
74 reg = readl(&anatop->digprog);
(gdb)
76 cfg = readl(&scu->config) & 3;
(gdb)
77 type = ((reg >> 16) & 0xff);
(gdb)
76 cfg = readl(&scu->config) & 3;
(gdb)
78 if (type == MXC_CPU_MX6DL) {
(gdb)
83 if (type == MXC_CPU_MX6Q) {
(gdb)
89 major = ((reg >> 8) & 0xff);
(gdb)
90 if ((major >= 1) &&
(gdb)
67 {
(gdb)
98 return (type << 12) | (reg + (0x10 * (major + 1)));
(gdb)
99 }
(gdb)
lowlevel_init () at arch/arm/cpu/armv7/lowlevel_init.S:69
69 pop {ip, pc}
(gdb)
save_boot_params_ret () at arch/arm/cpu/armv7/start.S:88
88 bl _main
(gdb)
_main () at arch/arm/lib/crt0.S:76
76 ldr r0, =(CONFIG_SYS_INIT_SP_ADDR)
(gdb) s
78 bic r0, r0, #7 /* 8-byte alignment for ABI compliance */
(gdb)
79 mov sp, r0
(gdb)
_main () at arch/arm/lib/crt0.S:80
80 bl board_init_f_alloc_reserve
(gdb)
board_init_f_alloc_reserve (top=9568000) at common/init/board_init.c:53
53 top = rounddown(top-sizeof(struct global_data), 16);
(gdb)
56 }
(gdb)
_main () at arch/arm/lib/crt0.S:81
81 mov sp, r0
(gdb)
_main () at arch/arm/lib/crt0.S:83
83 mov r9, r0
(gdb)
84 bl board_init_f_init_reserve
(gdb)
board_init_f_init_reserve (base=9566720) at common/init/board_init.c:111
111 memset(gd_ptr, '\0', sizeof(*gd));
(gdb)
101 {
(gdb)
111 memset(gd_ptr, '\0', sizeof(*gd));
(gdb)
memset () at arch/arm/lib/memset.S:24
24 ands r3, r0, #3 @ 1 unaligned?
(gdb)
25 mov ip, r0 @ preserve r0 as return value
(gdb)
26 bne 6f @ 1
(gdb)
30 1: orr r1, r1, r1, lsl #8
(gdb)
31 orr r1, r1, r1, lsl #16
(gdb)
32 mov r3, r1
(gdb)
33 cmp r2, #16
(gdb)
34 blt 4f
(gdb)
69 stmfd sp!, {r4-r8, lr}
(gdb)
memset () at arch/arm/lib/memset.S:70
70 mov r4, r1
(gdb)
71 mov r5, r1
(gdb)
72 mov r6, r1
(gdb)
73 mov r7, r1
(gdb)
74 mov r8, r1
(gdb)
75 mov lr, r1
(gdb)
77 cmp r2, #96
(gdb)
78 tstgt ip, #31
(gdb)
79 ble 3f
(gdb)
91 3: subs r2, r2, #64
(gdb)
92 stmiage ip!, {r1, r3-r8, lr}
(gdb)
93 stmiage ip!, {r1, r3-r8, lr}
(gdb)
94 bgt 3b
(gdb)
91 3: subs r2, r2, #64
(gdb)
92 stmiage ip!, {r1, r3-r8, lr}
(gdb)
93 stmiage ip!, {r1, r3-r8, lr}
(gdb)
94 bgt 3b
(gdb)
91 3: subs r2, r2, #64
(gdb)
92 stmiage ip!, {r1, r3-r8, lr}
(gdb)
93 stmiage ip!, {r1, r3-r8, lr}
(gdb)
94 bgt 3b
(gdb)
91 3: subs r2, r2, #64
(gdb)
92 stmiage ip!, {r1, r3-r8, lr}
(gdb)
93 stmiage ip!, {r1, r3-r8, lr}
(gdb)
94 bgt 3b
(gdb)
95 ldmfdeq sp!, {r4-r8, pc}
(gdb)
97 tst r2, #32
(gdb)
98 stmiane ip!, {r1, r3-r8, lr}
(gdb)
99 tst r2, #16
(gdb)
100 stmiane ip!, {r4-r7}
(gdb)
101 ldmfd sp!, {r4-r8, lr}
(gdb)
memset () at arch/arm/lib/memset.S:105
105 4: tst r2, #8
(gdb)
106 stmiane ip!, {r1, r3}
(gdb)
107 tst r2, #4
(gdb)
108 strne r1, [ip], #4
(gdb)
113 5: tst r2, #2
(gdb)
114 strbne r1, [ip], #1
(gdb)
115 strbne r1, [ip], #1
(gdb)
116 tst r2, #1
(gdb)
117 strbne r1, [ip], #1
(gdb)
118 ret lr
(gdb)
board_init_f_init_reserve (base=9566720) at common/init/board_init.c:117
117 base += roundup(sizeof(struct global_data), 16);
(gdb)
126 gd->malloc_base = base;
(gdb)
130 }
(gdb)
_main () at arch/arm/lib/crt0.S:86
86 mov r0, #0
(gdb)
87 bl board_init_f
(gdb)
board_init_f (boot_flags=0) at common/board_f.c:930
930 gd->have_console = 0;
(gdb)
929 gd->flags = boot_flags;
(gdb)
932 if (initcall_run_list(init_sequence_f))
(gdb)
930 gd->have_console = 0;
(gdb)
932 if (initcall_run_list(init_sequence_f))
(gdb)
initcall_run_list (init_sequence=init_sequence@entry=0x87870048 <init_sequence_f>) at lib/initcall.c:17
17 for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
(gdb)
14 {
(gdb)
17 for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
(gdb)
21 if (gd->flags & GD_FLG_RELOC)
(gdb)
22 reloc_ofs = gd->reloc_off;
(gdb)
27 if (gd->flags & GD_FLG_RELOC)
(gdb)
31 ret = (*init_fnc_ptr)();
(gdb)
^C
Program received signal SIGTRAP, Trace/breakpoint trap.
0xdeadbeee in ?? ()
So any idea what is wrong? Seems I am missing something obvious.
Here environment variables I set up for manual compilation in build_dir
folder:
export PATH=/home/al/imx6ull/imx6ull-openwrt/build_dir/target-arm_cortex-a7+neon-vfpv4_musl_eabi/linux-imx6ull_cortexa7/linux-4.14.199/scripts/dtc/:/home/al/imx6ull/imx6ull-openwrt/staging_dir/target-arm_cortex-a7+neon-vfpv4_musl_eabi/host/bin:/home/al/imx6ull/imx6ull-openwrt/staging_dir/hostpkg/bin:/home/al/imx6ull/imx6ull-openwrt/staging_dir/toolchain-arm_cortex-a7+neon-vfpv4_gcc-7.5.0_musl_eabi/bin:/home/al/imx6ull/imx6ull-openwrt/staging_dir/host/bin:/home/al/.npm-global/bin:/home/al/.local/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin
export STAGING_DIR=/home/al/imx6ull/imx6ull-openwrt/staging_dir/
export CROSS_COMPILE=arm-openwrt-linux-muslgnueabi-
export ARCH=arm
expord CC=arm-openwrt-linux-muslgnueabi-gcc