U-boot ddr timings file

Unfortunately, this is highly SoC specific. Some vendors provide some Excel sheets to enter details about both the RAM chip(s) (usually from their datasheet(s)) and further details about the specific hardware design (e.g. swizzle and trace lengths) and generate either pseudocode (e.g. later to be pasted into SPL part of U-Boot) or further artefacts to continue the tuning workflow. Such RAM tuning may involve further tools which may be used to stress the system at various operating conditions (e.g. across the whole rated temperature range usually run inside a climate chamber) to identify and calibrate them RAM timings. To get a feel of what exactly I am talking about I may refer you to the following page from NXP about their mostly public i.MX 8M family DDR tooling: https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/1104467. Now, if you reveal what exact vendor and SoC you are targeting, we may find out how exactly their tooling may look like.

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