Hello,
as you may or may not know, some of the X5000Rs started using Zbit Flash chip which is currently incompatible with the general OpenWrt releases for the model. My question is, is there a way to determine what Flash chip I've got without opening up the case?
Here's the log from the stock firmware.
Jan 1 00:00:05 syslogd started: BusyBox v1.24.2
Jan 1 00:00:06 C8343R: firmware version: 67.56.51.52-6118_8bc4b86
Jan 1 00:00:06 kernel: klogd started: BusyBox v1.24.2 (2020-11-02 15:44:05 CST)
Jan 1 00:00:06 kernel: [ 0.000000] Linux version 3.4.113 (gitlab-runner@Gitlab-CD) (gcc version 4.4.7 (GCC) ) #1 SMP Mon Nov 2 15:38:33 CST 2020
Jan 1 00:00:06 kernel: [ 0.000000]
Jan 1 00:00:06 kernel: [ 0.000000] MediaTek SoC: MT7621A, RevID: 0103, RAM: DDR3, XTAL: 40MHz
Jan 1 00:00:06 kernel: [ 0.000000] CPU/OCP/SYS frequency: 880/293/220 MHz
Jan 1 00:00:06 kernel: [ 0.000000] MT7621:ECO(0103) has PCIe reset BUG!!!
Jan 1 00:00:06 kernel: [ 0.000000] MT7621: PCIe host/device reset
Jan 1 00:00:06 kernel: [ 0.000000] prom memory:256MB
Jan 1 00:00:06 kernel: [ 0.000000] CPU revision is: 0001992f (MIPS 1004Kc)
Jan 1 00:00:06 kernel: [ 0.000000] Determined physical RAM map:
Jan 1 00:00:06 kernel: [ 0.000000] memory: 10000000 @ 00000000 (usable)
Jan 1 00:00:06 kernel: [ 0.000000] Zone PFN ranges:
Jan 1 00:00:06 kernel: [ 0.000000] Normal 0x00000000 -> 0x00010000
Jan 1 00:00:06 kernel: [ 0.000000] Movable zone start PFN for each node
Jan 1 00:00:06 kernel: [ 0.000000] Early memory PFN ranges
Jan 1 00:00:06 kernel: [ 0.000000] 0: 0x00000000 -> 0x00010000
Jan 1 00:00:06 kernel: [ 0.000000] On node 0 totalpages: 65536
Jan 1 00:00:06 kernel: [ 0.000000] free_area_init_node: node 0, pgdat 80416900, node_mem_map 81000000
Jan 1 00:00:06 kernel: [ 0.000000] Normal zone: 512 pages used for memmap
Jan 1 00:00:06 kernel: [ 0.000000] Normal zone: 0 pages reserved
Jan 1 00:00:06 kernel: [ 0.000000] Normal zone: 65024 pages, LIFO batch:15
Jan 1 00:00:06 kernel: [ 0.000000] Detected 3 available secondary CPU(s)
Jan 1 00:00:06 kernel: [ 0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
Jan 1 00:00:06 kernel: [ 0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
Jan 1 00:00:06 kernel: [ 0.000000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
Jan 1 00:00:06 kernel: [ 0.000000] PERCPU: Embedded 7 pages/cpu @81203000 s6016 r8192 d14464 u32768
Jan 1 00:00:06 kernel: [ 0.000000] pcpu-alloc: s6016 r8192 d14464 u32768 alloc=8*4096
Jan 1 00:00:06 kernel: [ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
Jan 1 00:00:06 kernel: [ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65024
Jan 1 00:00:06 kernel: [ 0.000000] Kernel command line: console=ttyS0,115200n8 root=/dev/mtdblock4 rootfstype=squashfs
Jan 1 00:00:06 kernel: [ 0.000000] PID hash table entries: 1024 (order: 0, 4096 bytes)
Jan 1 00:00:06 kernel: [ 0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
Jan 1 00:00:06 kernel: [ 0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
Jan 1 00:00:06 kernel: [ 0.000000] Writing ErrCtl register=0001057a
Jan 1 00:00:06 kernel: [ 0.000000] Readback ErrCtl register=0001057a
Jan 1 00:00:06 kernel: [ 0.000000] Memory: 255236k/262144k available (3335k kernel code, 6908k reserved, 848k data, 228k init, 0k highmem)
Jan 1 00:00:06 kernel: [ 0.000000] Hierarchical RCU implementation.
Jan 1 00:00:06 kernel: [ 0.000000] NR_IRQS:72
Jan 1 00:00:06 kernel: [ 0.000000] MIPS GIC RevID: 3.0
Jan 1 00:00:06 kernel: [ 0.000000] Setting up vectored interrupts
Jan 1 00:00:06 kernel: [ 0.000000] console [ttyS0] enabled
Jan 1 00:00:06 kernel: [ 0.004000] Calibrating delay loop... 577.53 BogoMIPS (lpj=1155072)
Jan 1 00:00:06 kernel: [ 0.040000] pid_max: default: 32768 minimum: 301
Jan 1 00:00:06 kernel: [ 0.044000] Mount-cache hash table entries: 512
Jan 1 00:00:06 kernel: [ 0.048000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
Jan 1 00:00:06 kernel: [ 0.056000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
Jan 1 00:00:06 kernel: [ 0.060000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
Jan 1 00:00:06 kernel: [ 0.068000] CPU revision is: 0001992f (MIPS 1004Kc)
Jan 1 00:00:06 kernel: [ 0.104000] Synchronize counters for CPU 1: done.
Jan 1 00:00:06 kernel: [ 0.112000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
Jan 1 00:00:06 kernel: [ 0.116000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
Jan 1 00:00:06 kernel: [ 0.124000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
Jan 1 00:00:06 kernel: [ 0.132000] CPU revision is: 0001992f (MIPS 1004Kc)
Jan 1 00:00:06 kernel: [ 0.168000] Synchronize counters for CPU 2: done.
Jan 1 00:00:06 kernel: [ 0.176000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
Jan 1 00:00:06 kernel: [ 0.180000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
Jan 1 00:00:06 kernel: [ 0.188000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
Jan 1 00:00:06 kernel: [ 0.196000] CPU revision is: 0001992f (MIPS 1004Kc)
Jan 1 00:00:06 kernel: [ 0.228000] Synchronize counters for CPU 3: done.
Jan 1 00:00:06 kernel: [ 0.236000] Brought up 4 CPUs
Jan 1 00:00:06 kernel: [ 0.240000] NET: Registered protocol family 16
Jan 1 00:00:06 kernel: [ 0.252000] MT7621:PCIe device GPIO reset
Jan 1 00:00:06 kernel: [ 0.652000] MT7621 PCIe PHY initialize
Jan 1 00:00:06 kernel: [ 1.800000] PCIE2 no card, disable it(RST&CLK)
Jan 1 00:00:06 kernel: [ 1.804000] PCIE0:link up
Jan 1 00:00:06 kernel: [ 1.804000] PCIE1:link up
Jan 1 00:00:06 kernel: [ 1.808000] PCIE2:link down
Jan 1 00:00:06 kernel: [ 1.808000] mt762x-pcie:register pci controller
Jan 1 00:00:06 kernel: [ 1.812000] FPU Affinity set after 4664 emulations
Jan 1 00:00:06 kernel: [ 1.820000] bio: create slab <bio-0> at 0
Jan 1 00:00:06 kernel: [ 1.824000] SCSI subsystem initialized
Jan 1 00:00:06 kernel: [ 1.828000] PCI host bridge to bus 0000:00
Jan 1 00:00:06 kernel: [ 1.832000] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff]
Jan 1 00:00:06 kernel: [ 1.836000] pci_bus 0000:00: root bus resource [io 0x1e160000-0x1e16ffff]
Jan 1 00:00:06 kernel: [ 1.840000] pci 0000:00:00.0: [0e8d:0801] type 01 class 0x060400
Jan 1 00:00:06 kernel: [ 1.840000] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x7fffffff]
Jan 1 00:00:06 kernel: [ 1.840000] pci 0000:00:00.0: reg 0x14: [mem 0x00000000-0x0000ffff]
Jan 1 00:00:06 kernel: [ 1.840000] pci 0000:00:00.0: supports D1
Jan 1 00:00:06 kernel: [ 1.840000] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
Jan 1 00:00:06 kernel: [ 1.840000] pci 0000:00:01.0: [0e8d:0801] type 01 class 0x060400
Jan 1 00:00:06 kernel: [ 1.840000] pci 0000:00:01.0: reg 0x10: [mem 0x00000000-0x7fffffff]
Jan 1 00:00:06 kernel: [ 1.840000] pci 0000:00:01.0: reg 0x14: [mem 0x00000000-0x0000ffff]
Jan 1 00:00:06 kernel: [ 1.840000] pci 0000:00:01.0: supports D1
Jan 1 00:00:06 kernel: [ 1.840000] pci 0000:00:01.0: PME# supported from D0 D1 D3hot
Jan 1 00:00:06 kernel: [ 1.840000] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
Jan 1 00:00:06 kernel: [ 1.844000] pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
Jan 1 00:00:06 kernel: [ 1.848000] pci 0000:01:00.0: [14c3:7916] type 00 class 0x000280
Jan 1 00:00:06 kernel: [ 1.848000] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
Jan 1 00:00:06 kernel: [ 1.848000] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
Jan 1 00:00:06 kernel: [ 1.848000] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
Jan 1 00:00:06 kernel: [ 1.848000] pci 0000:01:00.0: supports D1 D2
Jan 1 00:00:06 kernel: [ 1.848000] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
Jan 1 00:00:06 kernel: [ 1.848000] pci 0000:02:00.0: [14c3:7915] type 00 class 0x000280
Jan 1 00:00:06 kernel: [ 1.848000] pci 0000:02:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
Jan 1 00:00:06 kernel: [ 1.848000] pci 0000:02:00.0: reg 0x18: [mem 0x00000000-0x00003fff@
I was thinking, perhaps loading the Zbit compatible firmware and then somehow determining the Flash chip used is possible? Is it okay to load even if I don't have a Zbit chip?