Tenbay kuwifi T-MB5EU

i'm trying to understand why this device have this kind of info about radio. any clue? why is like that? tree radio, two or one DBDC?

WLAN Hardware:
MediaTek MT7905, MediaTek MT7975 MT7915E
WLAN 2.4GHz:
b/g/n/ax
WLAN 5.0GHz:
a/n/ac/ax

well for sure that chipset is not there

commit says

MediaTek MT7621 SoC
256M DDR3
16MB BoHong SPI-NOR
MediaTek MT7905+7975 2x2T2R DBDC bgnax / acax

1 Like

in openwrt boot log

[    9.306971] mt7915e_hif 0000:01:00.0: enabling device (0000 -> 0002)
[    9.317163] mt7621-pci 1e140000.pcie: bus=2 slot=1 irq=24
[    9.322613] pci 0000:00:01.0: enabling device (0006 -> 0007)
[    9.328263] mt7915e 0000:02:00.0: enabling device (0000 -> 0002)
[    9.442250] random: crng init done
[    9.459315] mt7915e 0000:02:00.0: HW/SW Version: 0x8a108a10, Build Time: 20201105222230a
[    9.459315]
[    9.777202] mt7915e 0000:02:00.0: WM Firmware Version: ____000000, Build Time: 20201105222304
[    9.810736] mt7915e 0000:02:00.0: WA Firmware Version: DEV_000000, Build Time: 20201105222323
[    9.956325] PPP generic driver version 2.4.2

7905 and 7975 are the RF companion chips to the 7915, which convert and amplify 2.4 and 5 Ghz repectively. Only the 7915 is connected to the PCIe bus.

so really this is driving me crazy, why the drivers work only for xiaomi ax 1800 series?, so the drivers need be edited on antenna side? or where?

also how include that? in openwrt dts? i get error about mt7621.dtsi

pcie@1e140000 {
		reg = <0x1e140000 0x40000>;
		interrupts = <0x0 0x4 0x4 0x0 0x18 0x4 0x0 0x19 0x4>;
		pinctrl-0 = <0xd>;
		compatible = "mediatek,mt7621-pci";
		clock-names = "pcie0", "pcie1", "pcie2";
		reset-gpios = <0xf 0x13 0x1>;
		reset-names = "pcie0", "pcie1", "pcie2";
		bus-range = <0x0 0xff>;
		device_type = "pci";
		clocks = <0xe 0x18 0xe 0x19 0xe 0x1a>;
		reset-gpio-names = "pcie";
		ranges = <0x2000000 0x0 0x0 0x60000000 0x0 0x10000000 0x1000000 0x0 0x0 0x1e160000 0x0 0x10000>;
		resets = <0x3 0x18 0x3 0x19 0x3 0x1a>;
		status = "okay";
		#address-cells = <0x3>;
		#size-cells = <0x2>;
		pinctrl-names = "default";
		interrupt-parent = <0x1>;

		pcie0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			device_type = "pci";
			#address-cells = <0x3>;
			#size-cells = <0x2>;
		};

		pcie1 {
			reg = <0x800 0x0 0x0 0x0 0x0>;
			device_type = "pci";
			#address-cells = <0x3>;
			#size-cells = <0x2>;
		};

		pcie2 {
			reg = <0x1000 0x0 0x0 0x0 0x0>;
			device_type = "pci";
			#address-cells = <0x3>;
			#size-cells = <0x2>;
		};

original dts file ( chinese firmware )

/dts-v1/;

/ {
	model = "MediaTek MT7621 DM2 T-MB5EU-V01-NOR";
	compatible = "mediatek,mt7621-rfb-ax-nor", "mediatek,mt7621-soc";
	#address-cells = <0x1>;
	#size-cells = <0x1>;

	gsw {
		mediatek,mdio = <0xc>;
		interrupts = <0x0 0x17 0x4>;
		mediatek,mcm;
		compatible = "mediatek,mt753x";
		mt7530,direct-phy-access;
		reset-names = "mcm";
		mediatek,phy-poll;
		mediatek,portmap = "wllll";
		resets = <0x3 0x2>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		interrupt-parent = <0x1>;

		port@6 {
			reg = <0x6>;
			compatible = "mediatek,mt753x-port";
			phy-mode = "trgmii";

			fixed-link {
				full-duplex;
				speed = <0x3e8>;
			};
		};

		mdio-bus {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
		};
	};

	pcie@1e140000 {
		reg = <0x1e140000 0x40000>;
		interrupts = <0x0 0x4 0x4 0x0 0x18 0x4 0x0 0x19 0x4>;
		pinctrl-0 = <0xd>;
		compatible = "mediatek,mt7621-pci";
		clock-names = "pcie0", "pcie1", "pcie2";
		reset-gpios = <0xf 0x13 0x1>;
		reset-names = "pcie0", "pcie1", "pcie2";
		bus-range = <0x0 0xff>;
		device_type = "pci";
		clocks = <0xe 0x18 0xe 0x19 0xe 0x1a>;
		reset-gpio-names = "pcie";
		ranges = <0x2000000 0x0 0x0 0x60000000 0x0 0x10000000 0x1000000 0x0 0x0 0x1e160000 0x0 0x10000>;
		resets = <0x3 0x18 0x3 0x19 0x3 0x1a>;
		status = "okay";
		#address-cells = <0x3>;
		#size-cells = <0x2>;
		pinctrl-names = "default";
		interrupt-parent = <0x1>;

		pcie0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			device_type = "pci";
			#address-cells = <0x3>;
			#size-cells = <0x2>;
		};

		pcie1 {
			reg = <0x800 0x0 0x0 0x0 0x0>;
			device_type = "pci";
			#address-cells = <0x3>;
			#size-cells = <0x2>;
		};

		pcie2 {
			reg = <0x1000 0x0 0x0 0x0 0x0>;
			device_type = "pci";
			#address-cells = <0x3>;
			#size-cells = <0x2>;
		};
	};

	cpus {

		cpu@0 {
			compatible = "mips,mips1004Kc";
		};

		cpu@1 {
			compatible = "mips,mips1004Kc";
		};
	};

	crypto@1e004000 {
		reg = <0x1e004000 0x1000>;
		interrupts = <0x0 0x13 0x4>;
		compatible = "mediatek,mtk-eip93";
		status = "okay";
		interrupt-parent = <0x1>;
	};

	i2c@1 {
		gpios = <0xf 0x7 0x0 0xf 0x8 0x0>;
		compatible = "i2c-gpio";
		#address-cells = <0x1>;
		i2c-gpio,delay-us = <0x2>;
		#size-cells = <0x0>;

		aw9523@b6 {
			reg = <0x5b>;
			gpios = <0xf 0x6 0x1>;
			#gpio-cells = <0x2>;
			compatible = "awinic,aw9523b";
			phandle = <0x16>;
			gpio-controller;
			linux,phandle = <0x16>;
		};
	};

	sdhci@1e130000 {
		reg = <0x1e130000 0x4000>;
		interrupts = <0x0 0x14 0x4>;
		compatible = "mediatek,mt7621-sdhci";
		status = "disabled";
		interrupt-parent = <0x1>;
	};

	usb-phy@1e1d0000 {
		reg = <0x1e1d0000 0x300>;
		compatible = "mediatek,mt7621-u3phy", "mediatek,mt2701-u3phy";
		ranges;
		status = "okay";
		#address-cells = <0x1>;
		#size-cells = <0x1>;

		usb-phy@0x1e1d0800 {
			reg = <0x1e1d0800 0x100>;
			clock-names = "ref";
			#phy-cells = <0x1>;
			clocks = <0x10>;
			phandle = <0x11>;
			linux,phandle = <0x11>;
		};

		usb-phy@0x1e1d0900 {
			reg = <0x1e1d0900 0x700>;
			clock-names = "ref";
			#phy-cells = <0x1>;
			clocks = <0x10>;
			phandle = <0x12>;
			linux,phandle = <0x12>;
		};

		usb-phy@0x1e1d1000 {
			reg = <0x1e1d1000 0x100>;
			clock-names = "ref";
			#phy-cells = <0x1>;
			clocks = <0x10>;
			phandle = <0x13>;
			linux,phandle = <0x13>;
		};
	};

	hnat@1e100000 {
		reg = <0x1e100000 0x3000>;
		mtketh-ppd = "eth0";
		mtketh-wan = "eth0";
		compatible = "mediatek,mtk-hnat_v1";
		reset-names = "mtketh";
		resets = <0xb 0x0>;
		status = "okay";
		ext-devices = "rax0", "ra0", "rax1", "ra1", "rax2", "ra2", "rax3", "ra3", "rax4", "ra4", "rax5", "ra5", "rax6", "ra6", "rax7", "ra7", "apclix0", "apcli0";
		mtketh-max-gmac = <0x2>;
	};

	rstctrl {
		#reset-cells = <0x1>;
		compatible = "ralink,rt2880-reset";
		phandle = <0x3>;
		linux,phandle = <0x3>;
	};

	sysclock50M@0 {
		#clock-cells = <0x0>;
		compatible = "fixed-clock";
		clock-frequency = <0x2faf080>;
		phandle = <0x2>;
		linux,phandle = <0x2>;
	};

	apll@0 {
		#clock-cells = <0x0>;
		compatible = "fixed-clock";
		clock-frequency = <0x1017df80>;
		phandle = <0x5>;
		linux,phandle = <0x5>;
	};

	chosen {
		bootargs = "console=ttyS0,115200";
	};

	raeth@1e100000 {
		reg = <0x1e100000 0xe000>;
		interrupts = <0x0 0x3 0x4>;
		compatible = "mediatek,mt7621-eth";
		status = "disabled";
		mediatek,ethsys = <0xb>;
		interrupt-parent = <0x1>;
	};

	gpio-keys-polled {
		compatible = "gpio-keys-polled";
		poll-interval = <0x14>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;

		wps {
			gpios = <0x16 0x8 0x1>;
			label = "wps";
			linux,code = <0x211>;
		};

		reset {
			gpios = <0x16 0x9 0x1>;
			label = "reset-factory";
			linux,code = <0x198>;
		};
	};

	gpio-leds {
		compatible = "gpio-leds";

		sys_led@10 {
			gpios = <0x16 0xa 0x1>;
			label = "sys_led";
			default-state = "off";
		};

		ether@0 {
			gpios = <0x16 0x0 0x1>;
			label = "RGB_BLUE";
			default-state = "off";
		};

		status@1 {
			gpios = <0x16 0x1 0x1>;
			label = "RGB_RED";
			default-state = "off";
		};

		wlan@11 {
			gpios = <0x16 0xb 0x1>;
			label = "RGB_GREEN";
			linux,default-trigger = "heartbeat";
		};
	};

	palmbus@1e000000 {
		reg = <0x1e000000 0x100000>;
		compatible = "palmbus";
		ranges = <0x0 0x1e000000 0xfffff>;
		#address-cells = <0x1>;
		#size-cells = <0x1>;

		nand@3000 {
			reg = <0x3000 0x800>;
			pinctrl-0 = <0xa>;
			ecc-engine = <0x9>;
			compatible = "mediatek,mt7621-nfc";
			status = "disabled";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			pinctrl-names = "default";

			flash@0 {
				reg = <0x0>;
				nand-ecc-mode = "hw";

				partitions {
					compatible = "fixed-partitions";
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					partition@100000 {
						reg = <0x100000 0x80000>;
						label = "Factory";
					};

					partition@180000 {
						reg = <0x180000 0x7e60000>;
						label = "firmware";
					};

					partition@0 {
						reg = <0x0 0x80000>;
						label = "Bootloader";
					};

					partition@80000 {
						reg = <0x80000 0x80000>;
						label = "Config";
					};
				};
			};
		};

		i2c@900 {
			reg = <0x900 0x100>;
			pinctrl-0 = <0x4>;
			compatible = "mediatek,mt7621-i2c";
			reset-names = "i2c";
			clocks = <0x2>;
			resets = <0x3 0x10>;
			status = "disabled";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			pinctrl-names = "default";
		};

		i2s@a00 {
			reg = <0xa00 0x100>;
			dmas = <0x6 0x4 0x6 0x6>;
			interrupts = <0x0 0x10 0x4>;
			txdma-req = <0x2>;
			compatible = "mediatek,mt7621-i2s";
			reset-names = "i2s";
			clocks = <0x5>;
			resets = <0x3 0x11>;
			status = "disabled";
			rxdma-req = <0x3>;
			dma-names = "tx", "rx";
			interrupt-parent = <0x1>;
		};

		spi@b00 {
			reg = <0xb00 0x100>;
			pinctrl-0 = <0x8>;
			compatible = "mediatek,mt7621-spi";
			reset-names = "spi";
			clocks = <0x7>;
			resets = <0x3 0x12>;
			status = "okay";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			pinctrl-names = "default";

			m25p80@0 {
				reg = <0x0>;
				compatible = "jedec,spi-nor";
				m25p,chunked-io = <0x20>;
				spi-max-frequency = <0x989680>;
				#address-cells = <0x1>;
				#size-cells = <0x1>;

				partition@0 {
					reg = <0x0 0x30000>;
					label = "Bootloader";
				};

				partition@30000 {
					reg = <0x30000 0x10000>;
					label = "Config";
				};

				partition@40000 {
					reg = <0x40000 0x10000>;
					label = "Product";
				};

				partition@50000 {
					reg = <0x50000 0x40000>;
					label = "Factory";
				};

				partition@90000 {
					reg = <0x90000 0xf70000>;
					label = "firmware";
				};
			};
		};

		uartlite@c00 {
			reg = <0xc00 0x100>;
			interrupts = <0x0 0x1a 0x4>;
			reg-shift = <0x2>;
			no-loopback-test;
			compatible = "mediatek,mt6577-uart", "ns16550a";
			clock-frequency = <0x2faf080>;
			clocks = <0x2>;
			reg-io-width = <0x4>;
			interrupt-parent = <0x1>;
		};

		gdma@2800 {
			reg = <0x2800 0x800>;
			interrupts = <0x0 0xd 0x4>;
			compatible = "mtk,rt3883-gdma";
			reset-names = "dma";
			#dma-requests = <0x10>;
			resets = <0x3 0xe>;
			status = "disabled";
			#dma-channels = <0x10>;
			#dma-cells = <0x1>;
			phandle = <0x6>;
			linux,phandle = <0x6>;
			interrupt-parent = <0x1>;
		};

		sysc@0 {
			reg = <0x0 0x100>;
			compatible = "mtk,mt7621-sysc";
		};

		memc@5000 {
			reg = <0x5000 0x1000>;
			compatible = "mtk,mt7621-memc";
		};

		uartfull@d00 {
			reg = <0xd00 0x100>;
			interrupts = <0x0 0x1b 0x4>;
			reg-shift = <0x2>;
			no-loopback-test;
			compatible = "mediatek,mt6577-uart", "ns16550a";
			clock-frequency = <0x2faf080>;
			clocks = <0x2>;
			status = "disabled";
			reg-io-width = <0x4>;
			interrupt-parent = <0x1>;
		};

		uartfull@e00 {
			reg = <0xe00 0x100>;
			interrupts = <0x0 0x1c 0x4>;
			reg-shift = <0x2>;
			no-loopback-test;
			compatible = "mediatek,mt6577-uart", "ns16550a";
			clock-frequency = <0x2faf080>;
			clocks = <0x2>;
			status = "disabled";
			reg-io-width = <0x4>;
			interrupt-parent = <0x1>;
		};

		ecc@3800 {
			reg = <0x3800 0x800>;
			compatible = "mediatek,mt7621-ecc";
			status = "okay";
			phandle = <0x9>;
			linux,phandle = <0x9>;
		};

		wdt@100 {
			reg = <0x100 0x100>;
			compatible = "mtk,mt7621-wdt";
		};

		hsdma@7000 {
			reg = <0x7000 0x1000>;
			interrupts = <0x0 0xb 0x4>;
			compatible = "mediatek,mt7621-hsdma";
			reset-names = "hsdma";
			#dma-requests = <0x1>;
			resets = <0x3 0x5>;
			status = "disabled";
			#dma-channels = <0x1>;
			#dma-cells = <0x1>;
			interrupt-parent = <0x1>;
		};

		gpio@600 {
			reg = <0x600 0x100>;
			interrupts = <0x0 0xc 0x4>;
			compatible = "mtk,mt7621-gpio";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			interrupt-parent = <0x1>;

			bank@0 {
				reg = <0x0>;
				#gpio-cells = <0x2>;
				compatible = "mtk,mt7621-gpio-bank";
				phandle = <0xf>;
				gpio-controller;
				linux,phandle = <0xf>;
			};

			bank@1 {
				reg = <0x1>;
				#gpio-cells = <0x2>;
				compatible = "mtk,mt7621-gpio-bank";
				gpio-controller;
			};

			bank@2 {
				reg = <0x2>;
				#gpio-cells = <0x2>;
				compatible = "mtk,mt7621-gpio-bank";
				gpio-controller;
			};
		};
	};

	ethernet@1e100000 {
		reg = <0x1e100000 0xe000>;
		interrupts = <0x0 0x3 0x4>;
		compatible = "mediatek,mt7621-eth", "syscon";
		status = "okay";
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		mediatek,ethsys = <0xb>;
		interrupt-parent = <0x1>;

		mac@0 {
			reg = <0x0>;
			compatible = "mediatek,eth-mac";
			phy-mode = "trgmii";

			fixed-link {
				full-duplex;
				pause;
				speed = <0x3e8>;
			};
		};

		mdio-bus {
			#address-cells = <0x1>;
			phandle = <0xc>;
			#size-cells = <0x0>;
			linux,phandle = <0xc>;

			ethernet-phy@1f {
				reg = <0x1f>;
				phy-mode = "rgmii";
			};
		};
	};

	sysclock125M@0 {
		#clock-cells = <0x0>;
		compatible = "fixed-clock";
		clock-frequency = <0x7735940>;
		phandle = <0x10>;
		linux,phandle = <0x10>;
	};

	aliases {
		serial0 = "/palmbus@1e000000/uartlite@c00";
	};

	interrupt-controller@1fbc0000 {
		reg = <0x1fbc0000 0x2000>;
		compatible = "mti,gic";
		mti,reserved-cpu-vectors = <0x7>;
		#interrupt-cells = <0x3>;
		phandle = <0x1>;
		interrupt-controller;
		linux,phandle = <0x1>;

		timer {
			interrupts = <0x1 0x1 0x0>;
			compatible = "mti,gic-timer";
			clocks = <0x14>;
		};
	};

	pinctrl {
		pinctrl-0 = <0x15>;
		compatible = "mtk,mtkmips-pinmux";
		pinctrl-names = "default";

		i2c {
			phandle = <0x4>;
			linux,phandle = <0x4>;

			i2c {
				mtk,function = "i2c";
				mtk,group = "i2c";
			};
		};

		spi {
			phandle = <0x8>;
			linux,phandle = <0x8>;

			spi {
				mtk,function = "spi";
				mtk,group = "spi";
			};
		};

		mdio {

			mdio {
				mtk,function = "mdio";
				mtk,group = "mdio";
			};
		};

		nand {
			phandle = <0xa>;
			linux,phandle = <0xa>;

			sdhci-nand {
				mtk,function = "nand2";
				mtk,group = "sdhci";
			};

			spi-nand {
				mtk,function = "nand1";
				mtk,group = "spi";
			};
		};

		pcie {
			phandle = <0xd>;
			linux,phandle = <0xd>;

			pcie {
				mtk,function = "gpio";
				mtk,group = "pcie";
			};
		};

		sdhci {

			sdhci {
				mtk,function = "sdhci";
				mtk,group = "sdhci";
			};
		};

		uart1 {

			uart1 {
				mtk,function = "uart1";
				mtk,group = "uart1";
			};
		};

		uart2 {

			uart2 {
				mtk,function = "uart2";
				mtk,group = "uart2";
			};
		};

		uart3 {

			uart3 {
				mtk,function = "uart3";
				mtk,group = "uart3";
			};
		};

		pinctrl0 {
			phandle = <0x15>;
			linux,phandle = <0x15>;

			uart2 {
				mtk,function = "uart2";
				mtk,group = "uart2";
			};

			uart3 {
				mtk,function = "gpio";
				status = "okay";
				mtk,group = "uart3";
			};

			rgmii2 {
				mtk,function = "gpio";
				status = "okay";
				mtk,group = "rgmii2";
			};
		};

		rgmii1 {

			rgmii1 {
				mtk,function = "rgmii1";
				mtk,group = "rgmii1";
			};
		};

		rgmii2 {

			rgmii2 {
				mtk,function = "rgmii2";
				mtk,group = "rgmii2";
			};
		};
	};

	ethsys@1e000000 {
		reg = <0x1e000000 0x8000>;
		compatible = "mediatek,mt7621-ethsys", "syscon";
		phandle = <0xb>;
		linux,phandle = <0xb>;
	};

	usb@1e1c0000 {
		reg = <0x1e1c0000 0x1000 0x1e1d0700 0x100>;
		phys = <0x11 0x3 0x12 0x4 0x13 0x3>;
		interrupts = <0x0 0x16 0x4>;
		reg-names = "mac", "ippc";
		compatible = "mediatek,mt7621-xhci", "mediatek,mt2701-xhci";
		clock-names = "sys_ck", "free_ck", "ahb_ck", "dma_ck";
		clocks = <0x10 0x10 0x10 0x10>;
		status = "okay";
		interrupt-parent = <0x1>;
	};

	sysbusclock@0 {
		#clock-cells = <0x0>;
		compatible = "mtk,mt7621-sys-bus-clock";
		phandle = <0x7>;
		linux,phandle = <0x7>;
	};

	cpuclock@0 {
		#clock-cells = <0x0>;
		compatible = "mtk,mt7621-cpu-clock";
		phandle = <0x14>;
		linux,phandle = <0x14>;
	};

	cpuintc@0 {
		compatible = "mti,cpu-interrupt-controller";
		#interrupt-cells = <0x1>;
		#address-cells = <0x0>;
		interrupt-controller;
	};

	clkctrl {
		#clock-cells = <0x1>;
		compatible = "ralink,rt2880-clock";
		phandle = <0xe>;
		linux,phandle = <0xe>;
	};
};

1 Like

i'll try that tomorrow,

see, now is rigth

so you have build for tenbay with RT1800 GPL, just replacing the dts?

sure it work, you need reset the radio to default, or the device to default,are you talking about the firmware that came with ip address 192.168.1.187 and dhcp disabled?
it do not work in wwan firewall wan zone, but if you create a wwan interface add firewall to lan zone it work right in repeter.