I see mach armada-370, armada-xp and armada-msys in kernel config
MV-AC3_GPL/tplink/buildroot-marvell$ grep MACH build/mv-ac3/build/linux-custom/.config
CONFIG_MACH_MVEBU_ANY=y
CONFIG_MACH_MVEBU_V7=y
CONFIG_MACH_ARMADA_370=y
# CONFIG_MACH_ARMADA_375 is not set
# CONFIG_MACH_ARMADA_38X is not set
# CONFIG_MACH_ARMADA_39X is not set
CONFIG_MACH_ARMADA_XP=y
# CONFIG_MACH_DOVE is not set
CONFIG_MACH_MSYS=y
The build produced two "new" dtbs, so I guess it must be one of these
MV-AC3_GPL/tplink/buildroot-marvell$ ls -lt ./build/mv-ac3/build/linux-custom/arch/arm/boot/dts/ |head
total 11048
-rwxr-xr-x 1 nobody nobody 10802 Feb 18 11:32 msys-ac3-rd.dtb
-rw-r--r-- 1 nobody nobody 10802 Feb 18 11:32 msys-ac3_tl-sg2210hp-m2.dtb
-rwxr-xr-x 1 nobody nobody 2234 Aug 30 2021 ste-ccu8540.dts
-rwxr-xr-x 1 nobody nobody 1546 Aug 30 2021 ste-ccu9540.dts
-rwxr-xr-x 1 nobody nobody 32659 Aug 30 2021 ste-dbx5x0.dtsi
-rwxr-xr-x 1 nobody nobody 9564 Aug 30 2021 ste-href-ab8500.dtsi
MV-AC3_GPL/tplink/buildroot-marvell$ find ./build/mv-ac3/build/linux-custom/arch/arm/ -name "*.dts" | grep msys
./build/mv-ac3/build/linux-custom/arch/arm/boot/dts/msys-ac3-db.dts
./build/mv-ac3/build/linux-custom/arch/arm/boot/dts/msys-ac3-rd.dts
./build/mv-ac3/build/linux-custom/arch/arm/boot/dts/msys-ac3_tl-sg2210hp-m2.dts
Both of these use msys-single.dtsi
/*
* Device Tree Include file for Marvell Msys family SoC
*
* Copyright (C) 2015 Marvell
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*
* Contains definitions specific to the Msys SoC that are not
* common to all Armada SoCs.
*/
#include "armada-370-xp.dtsi"
/ {
model = "Marvell Msys family SoC";
compatible = "marvell,msys", "marvell,armada-370-xp";
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <0>;
resets = <&cpurst 0>;
};
};
soc {
compatible = "marvell,armadaxp-mbus", "simple-bus";
pcie-mem-aperture = <0xe8000000 0x7e00000>;
pcie-io-aperture = <0xefe00000 0x100000>;
bootrom {
compatible = "marvell,bootrom";
reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
};
dfx: dfx-server {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
coreclk: mvebu-sar@f8204 {
compatible = "marvell,msys-core-clock";
reg = <0xf8204 0x4>;
#clock-cells = <1>;
};
soc-id@f8244 {
compatible = "marvell,msys-soc-id";
reg = <0xf8244 0x4>;
};
coredivclk: corediv-clock@f8268 {
compatible = "marvell,msys-corediv-clock";
reg = <0xf8268 0xc>;
#clock-cells = <1>;
clocks = <&coreclk 3>;
clock-output-names = "nand";
};
};
ireg: internal-regs {
reg = <MBUS_ID(0xf0, 0x01) 0 0x100000>;
sdramc@1400 {
compatible = "marvell,armada-xp-sdram-controller";
reg = <0x1400 0x500>;
};
L2: l2-cache {
compatible = "marvell,aurora-system-cache";
reg = <0x08000 0x1000>;
cache-id-part = <0x100>;
cache-level = <2>;
cache-unified;
wt-override;
};
spi0: spi@10600 {
compatible = "marvell,armada-xp-spi",
"marvell,orion-spi";
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
};
i2c0: i2c@11000 {
reg = <0x11000 0x20>;
status = "okay";
clock-frequency = <100000>;
};
pinctrl@18000 {
reg = <0x18000 0x20>;
devbus_pins: devbus-pins {
marvell,pins = "mpp0", "mpp1", "mpp2",
"mpp3", "mpp5", "mpp6",
"mpp7", "mpp8", "mpp9",
"mpp10", "mpp11", "mpp12",
"mpp16", "mpp17",
"mpp20", "mpp21", "mpp22",
"mpp23", "mpp24", "mpp25",
"mpp26", "mpp27", "mpp28",
"mpp29", "mpp30";
marvell,function = "dev";
};
nand_pins: nand-pins {
marvell,pins = "mpp4", "mpp16", "mpp19",
"mpp20", "mpp21", "mpp22",
"mpp23", "mpp24", "mpp25",
"mpp26", "mpp27", "mpp28",
"mpp29", "mpp30";
marvell,function = "nf";
};
sdio_pins: sdio-pins {
marvell,pins = "mpp5", "mpp6", "mpp7",
"mpp8", "mpp9", "mpp10";
marvell,function = "sdio";
};
spi_pins: spi-pins {
marvell,pins = "mpp0", "mpp1", "mpp2",
"mpp3";
marvell,function = "spi";
};
uart1_pins: uart1-pins {
marvell,pins = "mpp11", "mpp12";
marvell,function = "uart1";
};
pp_pin: pp-pin {
marvell,pins = "mpp13";
marvell,function = "pp";
};
i2c0_pins: i2c0-pins {
marvell,pins = "mpp14", "mpp15";
marvell,function = "i2c0";
};
slvsmi_pins: slvsmi-pins {
marvell,pins = "mpp31", "mpp32";
marvell,function = "slvsmi";
};
};
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
};
gpio1: gpio@18180 {
compatible = "marvell,orion-gpio";
reg = <0x18180 0x40>;
ngpios = <1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <87>;
};
system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";
reg = <0x18200 0x500>;
};
gateclk: clock-gating-control@18220 {
compatible = "marvell,msys-gating-clock";
reg = <0x18220 0x4>;
clocks = <&coreclk 0>;
#clock-cells = <1>;
};
timer@20300 {
compatible = "marvell,armada-xp-timer";
clocks = <&coreclk 0>, <&refclk>;
clock-names = "nbclk", "fixed";
};
cpurst: cpurst@20800 {
compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x10>;
#reset-cells = <1>;
};
interrupt-controller@20a00 {
reg = <0x20a00 0x2d0>, <0x21070 0x58>, <0x21870 0x390>;
};
pmsu@22000 {
compatible = "marvell,msys-pmsu";
reg = <0x22000 0x1000>, <0x20984 0x4>;
};
/* Overwrite FIFO size */
eth0: ethernet@70000 {
tx-csum-limit = <9800>;
};
eth1: ethernet@74000 {
tx-csum-limit = <9800>;
};
xor@f0800 {
compatible = "marvell,orion-xor";
reg = <0xF0800 0x100
0xF0A00 0x100>;
clocks = <&gateclk 22>;
};
system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";
reg = <0x18200 0x500>;
};
gateclk: clock-gating-control@18220 {
compatible = "marvell,msys-gating-clock";
reg = <0x18220 0x4>;
clocks = <&coreclk 0>;
#clock-cells = <1>;
};
timer@20300 {
compatible = "marvell,armada-xp-timer";
clocks = <&coreclk 0>, <&refclk>;
clock-names = "nbclk", "fixed";
};
cpurst: cpurst@20800 {
compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x10>;
#reset-cells = <1>;
};
interrupt-controller@20a00 {
reg = <0x20a00 0x2d0>, <0x21070 0x58>, <0x21870 0x390>;
};
pmsu@22000 {
compatible = "marvell,msys-pmsu";
reg = <0x22000 0x1000>, <0x20984 0x4>;
};
/* Overwrite FIFO size */
eth0: ethernet@70000 {
tx-csum-limit = <9800>;
};
eth1: ethernet@74000 {
tx-csum-limit = <9800>;
};
xor@f0800 {
compatible = "marvell,orion-xor";
reg = <0xF0800 0x100
0xF0A00 0x100>;
clocks = <&gateclk 22>;
status = "okay";
xor00 {
interrupts = <51>;
dmacap,memcpy;
dmacap,xor;
};
xor01 {
interrupts = <52>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
};
};
clocks {
/* 25 MHz reference crystal */
refclk: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
};
};
And have some small differences:
MV-AC3_GPL/tplink/buildroot-marvell$ diff -u ./build/mv-ac3/build/linux-custom/arch/arm/boot/dts/msys-ac3-rd.dts ./build/mv-ac3/build/linux-custom/arch/arm/boot/dts/msys-ac3_tl-sg2210hp-m2.dts
--- ./build/mv-ac3/build/linux-custom/arch/arm/boot/dts/msys-ac3-rd.dts 2021-08-30 03:54:24.000000000 +0200
+++ ./build/mv-ac3/build/linux-custom/arch/arm/boot/dts/msys-ac3_tl-sg2210hp-m2.dts 2021-08-30 03:54:24.000000000 +0200
@@ -139,17 +139,17 @@
reg = <0x01000000 0x3f000000>;
};
};
-
+
system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";
- rst-gpio = <17>;
+ rst-gpio = <28>;
rst-invt = <1>;
};
};
i2c-gpio{
compatible = "i2c-gpio";
- gpios=<&gpio0 4 0 &gpio0 28 0>;
+ gpios=<&gpio0 18 0 &gpio0 4 0>;
i2c-gpio,delay-us = <5>;
i2c-gpio,timeout-ms = <10>;
status = "okay";
So OpenWrt target should mvebu, right...
