This may not help, but have you tried using my proposed driver for upstream? The patch set is a bit more invasive than the current driver, but I'm quite confident setting pin directions and values works correctly with that one. I've used it to test SFP modules and LM75A sensors on my Cisco SG220-26P. Hardware details might differ, of course, but at least bitbanged I2C works with the driver.
Not yet, it's next on my list to try.
I just need to figure out the MDIO pins.
Ok, got it compiled and DTS sorted out but it's the same.
For whatever reason, it's floating at 0.2V.
It just makes no sense
Does the RTL8382 have an MDIO controller?
1 Like
For the RTL8231? It does, the RTL8382 isn't too dissimilar from the RTL8380, just supports more ethernet ports IIRC. I think I had an MDIO-controller implementation written for that auxilairy bus, but I may have to dig quite deep to find it (if I still have it somewhere...).
Does it also have the PHY-s on the AUX MDIO or they are SMI only?
I know that I am asking annoying questions, but this design is quite confusing for me.
No worries about the questions 
The phy-s are on a different bus.
This is all kind of contradictory to the designs I am used to, been working with various ARM/ARM64 router/switch platforms for too long it seems.
1 Like
Sounds like you've been spending too much time with sane hardware. The registers space for the networking part is pure chaos!
1 Like
I would call it semi-sane at best, Qualcomm and Marvell really like to do funny stuff, especially in the networking PHY-s.
And don't get me started on the CPLD implementations on Marvell Prestera switches.
Thanks kobi. I tried the image and also a fresh build from brainslayer/openwrt#pie-5.10-rtl9313, but boot still hangs with CPU stalls.
The design of the rtl838x is clearly geared towards being cheap. The rtl8231 gpio expander using an smi bus reduces the pincount and doubles also as a led controller. Register space and most of the sdk code seem to be auto generated from randomly made vhdl. But the weirdness can be actual fun to figure out, also because it is always dangerous to rely on expectations: Bits and registers change meanings and who would have thought of breaking mips timer irqs just for the fun of it it seems...
Could you post a boot log? Either the fix is wrong or there is another difference. The one I thought to have fixed does BTW not impair the functionality. There is a table for port masks that can only be written to, not read like in newer chips, so one has to keep a shadow table to keep track of what was written. Trying to read hangs the CPU is my guess.
Hello,
I am trying to get OpenWRT running on a D-Link DGS-1210-26.
I have access to the serial console and I am able to interrupt the boot process by pressing Esc. Unfortunately I am not able to enter any command at the u-boot prompt. I only see the ouput "DDP Timeout" about every 15 seconds.
Since interrupting the boot process works reliable and I am able to enter commands after the stock image has loaded I don't think that this is a soldering/cabling issue.
Here is some output from the switch and the boot log:
DGS-1210-26> show flash information
Flash ID : MX25L25635F
Flash size : 32MB
Partition Used Available Use%
Boot 1000000 0 100
Image1 12460064 1695712 88
Image2 12460064 1695712 88
FileSystem 290816 3641344 7
DGS-1210-26> show boot_file
Bootup Firmware : image_1
Bootup Configuration : config_1
DGS-1210-26> show switch
System name :
System Contact :
System Location :
System up time : 0 days, 0 hrs, 3 min, 4 secs
System Time : 01/01/2020 00:39:45
System hardware version : F2
System firmware version : 6.20.007
System boot version : 1.01.001
[...]
DGS-1210-26> reboot
% Device will reboot, please wait a few minutes to re-login.
DGS-1210-26> System will Reboot....
U-Boot 2011.12.(2.1.5.67086)-Candidate1 (Jun 22 2020 - 14:56:47)
Board: RTL838x CPU:500MHz LXB:200MHz MEM:300MHz
DRAM: 128 MB
SPI-F: 1x32 MB
Loading 1024B env. variables from offset 0x80000
Board Model = DGS-1210-26-F1 Cameo_bdinfo_get_BoardID [293]
Switch Model: RTL8382M_8218B_INTPHY_8218B_2FIB_1G_DEMO (Port Count: 26)
Switch Chip: RTL8382
**************************************************
#### RTL8218B config - MAC ID = 0 ####
Now External 8218B
**************************************************
#### RTL8218B config - MAC ID = 8 ####
Now Internal PHY
**************************************************
#### RTL8218B config - MAC ID = 16 ####
Now External 8218B
Net: Net Initialization Skipped
rtl8380#0
Hit Esc key to stop autoboot: 0
Force port28 link up 1G
Please wait for PHY init-time ...
u-boot>#
DDP Timeout.
DDP Timeout.
DDP Timeout.
Any ideas what could be wrong?
Problem solved. Forgot to press Ctrl+C ... 
Yeah, the price was most likely the most important factor when they were designing this.
It honestly looks like they described it in VHDL and then cost-optimized it for production.
A little bit of weirdness is fun, but when you start breaking stuff you would expect to universal for that ISA, then it starts being tricky.
I personally have no experience nor desire to deal with debugging IRQ-s or basic stuff like that, this is where ARM is really good with their GIC.
Hi,
I tried to read through all of the thread but lots of it I don't understand when it comes to the development parts.
I was really happy when release 21.02 announced it will support the Realtek target in switches. Eversince then I've been looking forward to having a Switch running OpenWrt with the following specs.
- 24+ 1G Twisted Pair ports
- 4+ 10G SFP+ Ports
- Layer3 static routing for IPv4/IPv6 Dual Stack
I found this kind of affordable switch from fs.com that has RTL9301 SoC.
https://www.fs.com/products/134655.html
How likely is it that this or another device within that pricerange will ever be supported and if so, would I also be able to filter traffic when I run it as a Layer3 routing device?
I would even be willing to put a little bit of money into the bucket in order to help make this dream reality, yet I'm not a company and cannot afford to put lots into it.
I've written an Ansible role to handle OpenWrt devices and it would be very welcome if my Switch would also be able to run OpenWrt.
Thanks @anon13997276 for the formidable work.
That's a nice find! Thanks for sharing. I have very good experience with fs.com when it comes to transceivers and fiber, so to me that's quite a lot more interesting than most cheap devices out there.
I only wish they would publish such details so you didn't have to ask for each device.
EDIT: Looks like some of their other switches are Realtek based too. Downloaded https://img-en.fs.com/file/user_manual/s2800s-series-switches-fsos_v1.0.2.9_software.zip from https://www.fs.com/products/129514.html, unpacked with binwalk -Me and got
bjorn@miraculix:/tmp$ cat _S2800S\ Series\ Switches\ FSOS_v1.0.2.9_Software.bix.extracted/_vmlinux_org.bin.extracted/_28A000.extracted/cpio-root/etc/version
Realtek/RTL8380 Version 3.2.0 -- 2021ๅนด 09ๆ 02ๆฅ ๆๆๅ 09:36:44 CST
1 Like
Indeed a very nice find! At present you should be able to adapt OpenWRT master to run on this device with a suitable .dts. The 24 GBit ports very likely will work as we have support for all PHYs that have so far been seen with the RTL devices (Realtek and Aquantia). There is support for L3 routing and firewall offloading, but this will need thorough testing before it should be used in any kind of security sensitive setting. Also this support is not complete (no egress filtering, no IPv6 routing support) and it uses a relatively young Linux API, for which there is no GUI in OpenWRT. The Ethernet driver is not very performant (120MBit/s in master) and limited by the weak CPU (MIPS 34Kc on the RTL930x), for which VSMP and compiler optimization support is missing presently. So the L3 offloading support would absolutely be necessary. The hardware also allows offloading of PPPoE tunneling, but this is also not supported (it might be as easy as enabling a hardware switch, but again there is a testing to be done). Also the 10GBit SFP+ ports probably will not work yet, as they would need to be initialized by u-boot, which is usually not done, with the only known exception so far being the Ubiquiti USW switch which has only SFP+ ports. 4 SFP ports also means the need to use the hardware I2C driver, for which a PR is waiting for someone to review since quite some time. Presently we are trying to improve the RTL9300 hardware support with a detour via the RTL931x architecture which is more accessible. For that architecture we have SMP running in development branches and are able to get the SFP+ ports running independently of u-boot. So support is coming, only the time-frame is a bit vague 
3 Likes
@anon13997276 I've written an alternative implementation for CPU affinity support, on top of my per-parent-interrupt patches (RFC v2 and current patches). Feel free to give it a spin by copying the source file to your OpenWrt build:
3 Likes
Hi Sander,
great that you work on this! I will absolutely give it a try in the next days. I am presently on vacation in the north of Germany and a bit limited with my devices. I am finally preparing a PR with all the stuff Sebastian and I did since the summer. So finally the split into the 4 sub-targets including compiler and kernel config optimizations. The idea is to have RTL838X with 4kec and no MIPS16 instructions, then RTL839X with 24Kc, MIPS16 and VSMP but presently no IRQ balancing for the Ethernet driver, then RTL930X with 24Kc but without VSMP because the IRQ balancing for the RLT9300 timer does not work and then the RTL931X with true SMP. I will try to see whether your IRQ patches allow to enable IRQ balancing for the RTL9300 timer so we can have VSMP on the RTL9300. I don't have my usual test setup though which puts lots of traffic through and into the switch to provoke Ethernet receive IRQs, RX ring buffer overflow IRQs and link status change IRQs (a script on a PC up and downing a link). For the IRQ balancing, one needs a set_affinity() function though, the RTL9300 timer needs to call this depending on which CPU is being initialized, I'll take the current one here: https://github.com/bkobl/openwrt/blob/vsmp/target/linux/realtek/files-5.10/drivers/irqchip/irq-realtek-rtl.c#L70
The PR I prepare is here:
https://github.com/bkobl/openwrt/tree/vsmp
There are still more than 10k lines of code to merge into that PR, though. All the RTL931X support and quite a bit more on RTL9300, plus Link Aggregation (Sebastian did that and it's more than 4 thousand lines alone if I see correctly) support and finally the GS1900-48 for the RTL839x sub-arch, one of the Zyxel XGS12XX for RTL9300 and the RTL931X EdgeCore, to have devices that allow to test code on all SoC families directly in master. I want to have it all in, because there are tons of bug-fixes in there we found by stress testing and with Sebastian's test setup plus clean-ups made possible by having the 4 archs now in parallel. I guess I am back to big PRs with fun features after my little I2C-driver test balloon PR has not attracted any attention in the past more than 2 weeks
I would hope we can put the MIPS generic patch on top of the different sub-archs to clean things up further, then.
2 Likes
I have compiled OpenWRT for a D-Link DGS-1210-26 using master branch and the DTS provided by @lorenz. Unfortunately it hangs when rebooting the device.
Reboot works if I add reboot=warm or reboot=soft to bootargs. However the SoC seems to be in an undefined state afterwards. I can no longer load an image using TFTP, pinging the TFTP server also fails.
Resetting the CPU using "reset" in U-Boot does not help either. I have to unplug the power in order to recover from this state.
When I try to load the stock firmware from flash after OpenWRT was running the boot process hangs:
Starting kernel ...
Linux version 2.6.19 (simon@208Server) (gcc version 3.4.4 mipssde-6.03.00-20051020) #20 PREEMPT Mon Jun 22 15:09:26 CST 2020
CPU revision is: 00019070
Determined physical RAM map:
memory: 02000000 @ 00000000 (usable)
User-defined physical RAM map:
memory: 07a00000 @ 00000000 (usable)
Built 1 zonelists. Total pages: 30988
Kernel command line: console=ttyS0,115200 mem=122M noinitrd root=/dev/mtdblock4 rw rootfstype=squashfs csb=0x0142DBF4 cso=0x0866F1AF csf=0x56B69CCF sfin=<NULL>,32MB,10887200;10887200
Primary instruction cache 16kB, physically tagged, 4-way, linesize 16 bytes.
Primary data cache 16kB, 2-way, linesize 16 bytes.
Synthesized TLB refill handler (20 instructions).
Synthesized TLB load handler fastpath (32 instructions).
Synthesized TLB store handler fastpath (32 instructions).
Synthesized TLB modify handler fastpath (31 instructions).
PID hash table entries: 512 (order: 9, 2048 bytes)
Got reserved at 3c1f8000
Any ideas how to solve this issue?