767

I just would like to choose a reliable 8 port POE gigabit switch.
What would recommend? I saw this e.g. is already supported:

1 Like
768

For hardware recommendations please open a new topic in the Hardware Questions and Recommendations category of this forum.

Thanks! :slight_smile:

1 Like
769

Luckily most of these larger RTL93XX based switches seem to have a dedicated RJ45 console port on them, so no need for UART or breaking the case open right?

770

This command does not exist from what I am seeing?

771

Manufacture told my client, In current MIPS architecture, our porting did not use DTS, as mentioned we have existing image can be used.

What does this mean?

772

I'm trying to set up bonding between the switch and a VMWare ESXI host and it doesn't seem to work (GS1900-8). I've set up a bond interface with lan6, lan7, lan8 participating in the bond (802.3ad), added the bond to the bridge, and I had to factory reset afterwards because the switch just stopped responding :smile: Has anyone tried and succeeded with setting up bonding on these devices? The stock firmware allows me to do so (and it worked perfectly), so the hardware supports it.

773

You should give this tree a try:

A lot of work was done on the link aggregation code and it should work fine now. If feedback is positive we can try to push it into master, it builds on the current PR with many other new features.

774

Hey,
Thanks for the link. I'm tried having a look at the commit history to figure out what changed, but the branch's so ahead of the main branch that this is basically impossible (at least for a not so talented engineer like me :smiley: ) - can you point out the relevant commits that established the LAG support? Is there any way I could contribute, eg. an issue tracker of sorts where I can find tasks to pick up or something like that?
Do you have any documentation on how to set up a local dev env and maybe a debugger?

775

This is a DSA switch driver, its interface to userland is via callbacks in the dsa_switch_ops structure in target/linux/realtek/files-5.10/drivers/net/dsa/dsa.c The relevant callbacks for port binding (Link Aggregation) are

	.port_lag_change	= rtl83xx_port_lag_change,
	.port_lag_join		= rtl83xx_port_lag_join,
	.port_lag_leave		= rtl83xx_port_lag_leave,
	.port_pre_bridge_flags  = rtl83xx_port_pre_bridge_flags,
	.port_bridge_flags  = rtl83xx_port_bridge_flags,

In the rtl83xx_switch_ops structure instance. These are used on the 838x and 839x switches. It should be sufficient to copy over these function from within dsa.c to the in-tree dsa.c and make sure the variables, register names and other structure are also being copied also. There is an rtl838x.h file with the relevant definitions. I would copy what is obvious and then build the code to let the compiler tell me what is missing. Note that I did not write the code, but I am sure you can contact BrainSlayer over github for help.

776

Hi there!

I have a D-Link DGS-1210-26 (so not the apparently more popular -28) that I want to get running with OpenWrt. I have created an initial .dts file based on the -28 and most things non-switch related seem to work fine.

However, I seem to have a similar problem with that "PIE" engine, almost no packets are passed between two ports in the same VLAN and I get those same hex values listed from the bootloader.

Curiously, everything works fine in VLAN 100, but configured with any other VLAN id (tagged or not, switch part of the network or not) no packets get through. Maybe that VLAN has some left over state from the bootloader, or it is related to the fact that it is configured first, somehow.

I am slowly making my way through all these messages in this thread, but at first glance I couldn't quite figure out if where this patch of yours is included?

Also still missing is testing of the SFP slots, and their I2C lines do not seem to want to work for me (the GPIO lines of the rtl8231 stay always at +3.3V).

Happy to help out any way I can to make this switch work with OpenWRT!

Thanks,
Lorenz

777

Hi,

this should do the trick, just checkout this pull-request and make sure you compile the TESTING_KERNEL (linux 5.10):

778

try this patch:
https://patchwork.ozlabs.org/project/openwrt/patch/20210930171541.13804-1-fercerpav@gmail.com/

This patch fixes the same issue of RTL8231 on my ApresiaLightGS120GT-SS (RTL8382M, 16 + 4 combo)

1 Like
779

Careful that you apply this patch to the 5.10 RTL8231 driver (it is patching the 5.4 one), the PR works with the 5.10 port made by @musashino.

1 Like
780

Thanks very much, with that and the patch from @musashino everything seems to work now, even the SFP slots!

For reference, this is my current device tree file, the two SFP slots are directly attached to the main chip on pins 94-97 and 99-102, as described in Section 6.5.5 of the datasheet, so I presume that phy-mode = "1000base-x"; is correct. It works in any case. The I2C connections I traced out are identical to those recently posted for the DGS-1210-10P H/W:R1, which is encouraging. I couldn't find a connection to the TX-fault pin of the SFP slots to any of the pins of the RTL8231.

rtl8382_d-link_dgs-1210-26.dts:

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

#include "rtl8382_d-link_dgs-1210.dtsi"

/ {
        compatible = "d-link,dgs-1210-26", "realtek,rtl838x-soc";
        model = "D-Link DGS-1210-26";

        /* Left SFP slot, port 25 */
        i2c0: i2c-gpio-0 {
                compatible = "i2c-gpio";
                sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
                scl-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
                i2c-gpio,delay-us = <2>;
                #address-cells = <1>;
                #size-cells = <0>;
        };

        sfp0: sfp-p25 {
                compatible = "sff,sfp";
                i2c-bus = <&i2c0>;
                los-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
                mod-def0-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
                tx-disable-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
        };

        /* Right SFP slot, port 26 */
        i2c1: i2c-gpio-1 {
                compatible = "i2c-gpio";
                sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
                scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
                i2c-gpio,delay-us = <2>;
                #address-cells = <1>;
                #size-cells = <0>;
        };

        sfp1: sfp-p26 {
                compatible = "sff,sfp";
                i2c-bus = <&i2c1>;
                los-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
                mod-def0-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
                tx-disable-gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
        };
};

&gpio1 {
        status = "okay";
};

&ethernet0 {
        mdio: mdio-bus {
                compatible = "realtek,rtl838x-mdio";
                regmap = <&ethernet0>;
                #address-cells = <1>;
                #size-cells = <0>;

                EXTERNAL_PHY(0)
                EXTERNAL_PHY(1)
                EXTERNAL_PHY(2)
                EXTERNAL_PHY(3)
                EXTERNAL_PHY(4)
                EXTERNAL_PHY(5)
                EXTERNAL_PHY(6)
                EXTERNAL_PHY(7)

                INTERNAL_PHY(8)
                INTERNAL_PHY(9)
                INTERNAL_PHY(10)
                INTERNAL_PHY(11)
                INTERNAL_PHY(12)
                INTERNAL_PHY(13)
                INTERNAL_PHY(14)
                INTERNAL_PHY(15)

                EXTERNAL_PHY(16)
                EXTERNAL_PHY(17)
                EXTERNAL_PHY(18)
                EXTERNAL_PHY(19)
                EXTERNAL_PHY(20)
                EXTERNAL_PHY(21)
                EXTERNAL_PHY(22)
                EXTERNAL_PHY(23)

                INTERNAL_PHY(24)
                INTERNAL_PHY(26)
        };
};

&switch0 {
        ports {
                #address-cells = <1>;
                #size-cells = <0>;

                SWITCH_PORT(0, 1, qsgmii)
                SWITCH_PORT(1, 2, qsgmii)
                SWITCH_PORT(2, 3, qsgmii)
                SWITCH_PORT(3, 4, qsgmii)
                SWITCH_PORT(4, 5, qsgmii)
                SWITCH_PORT(5, 6, qsgmii)
                SWITCH_PORT(6, 7, qsgmii)
                SWITCH_PORT(7, 8, qsgmii)

                SWITCH_PORT(8, 9, internal)
                SWITCH_PORT(9, 10, internal)
                SWITCH_PORT(10, 11, internal)
                SWITCH_PORT(11, 12, internal)
                SWITCH_PORT(12, 13, internal)
                SWITCH_PORT(13, 14, internal)
                SWITCH_PORT(14, 15, internal)
                SWITCH_PORT(15, 16, internal)

                SWITCH_PORT(16, 17, qsgmii)
                SWITCH_PORT(17, 18, qsgmii)
                SWITCH_PORT(18, 19, qsgmii)
                SWITCH_PORT(19, 20, qsgmii)
                SWITCH_PORT(20, 21, qsgmii)
                SWITCH_PORT(21, 22, qsgmii)
                SWITCH_PORT(22, 23, qsgmii)
                SWITCH_PORT(23, 24, qsgmii)

                port@24 {
                        reg = <24>;
                        label = "lan25";
                        phy-mode = "1000base-x";
                        managed = "in-band-status";
                        sfp = <&sfp0>;
                };

                port@26 {
                        reg = <26>;
                        label = "lan26";
                        phy-mode = "1000base-x";
                        managed = "in-band-status";
                        sfp = <&sfp1>;
                };

                port@28 {
                        ethernet = <&ethernet0>;
                        reg = <28>;
                        phy-mode = "internal";
                        fixed-link {
                                speed = <1000>;
                                full-duplex;
                        };
                };
        };
};

I believe this model might be able to use all 24 copper ports as well as the 2 SFP slots at the same time (as per the diagram in section 3.4 of the datasheet) - but I have not tried this yet.

3 Likes
781

Even in ApresiaLightGS120GT-SS, TX-Fault lines are not connected.

RTL8231 GPIO pin assignment:

0
1   SFP     P18 I2C (SDA)
2   SFP     P18 I2C (SCL)
3   SFP     P18 MOD0
4   SFP     P18 LOS
5
6   SFP     P17 I2C (SDA)
7   SFP     P17 I2C (SCL)
8   SFP     P17 MOD0
9   SFP     P17 LOS
10  LED     "LOOP"
11  SFP     P20 I2C (SDA)
12  SFP     P20 I2C (SCL)
13  SFP     P20 MOD0
14  SFP     P20 LOS
15
16
17
18
19
20
21
22  SFP     P19 I2C (SDA)
23  SFP     P19 I2C (SCL)
24  SFP     P19 MOD0
25  SFP     P19 LOS
26
27
28
29
30
31
32
33  Button  "RESET"
34  SYS     SoC RESET?
35
36  LED     unused LED (LED chip is soldered, but no hole on the case)

Note:

  • 4x TX-Disable lines are provided by RTL8214FC
  • this switch seems to be almost the same as D-Link DGS-1210-16 Rev.G
1 Like
782

Okay, almost: reset no longer works, which it did in a master from last week or so. I get the same console message as for the working case,

[  909.732969] PLL control register: efffffff, applying reset value efffffff

but then it stays there and I have to power-cycle.

783

I recognized it as a potential issue in 5.10, but until now there was no report from anyone other than me and I couldn't determine if it was my environment-specific issue...

784

Oh, no, the reset bug on the 838x platform is back. This is bad, because it depends on the device you are using. The strange PLL message is there to help you understand what is going on.

What is happening is the following: The Flash on this platform can be addressed in a 3 or with a 4 byte wide mode. It depends on the type of flash being used, in particular its size. The flash driver once Linux is running can basically do whatever it wants, but U-Boot expects a certain state when it boots up and tries to read the flash. Interestingly, the reset does not reset the 3/4-byte mode and PLL upon reset (there are other things you can mess up which will prevent the device from booting even after the reset, I have found quite a few by accident). So you see this reset and then nothing happens any longer, because the reset happened, it is only u-boot that gets stuck and cannot boot.

The original flash driver carefully tried to avoid this effect together with the reset code. Because it depends on the device, you can easily fix it for one type and break it for another. It took a lot of time and effort from several developers to find a solution that actually worked on all devices. The new flash driver looks suspiciously free of the 3/4 byte hacks that were being used...

2 Likes
785

(Nearly?) all switches I've worked with until now have a GPIO pin (usually from an RTL8231, but can also be an internal one) wired to the SoC's hard reset pin. This GPIO can be used with the gpio-restart driver, and works reliably in my experience. This could help avoiding the current hacks.

2 Likes
786

I did some tests with 5.10:

Panasonic Switch-M8eG PN28080K (RTL8380M, 8 + 1 sfp)

Flash: MX25L25635F

current master 
BusyBox v1.34.0 (2021-09-29 11:36:23 UTC) built-in shell (ash)

  _______                     ________        __
 |       |.-----.-----.-----.|  |  |  |.----.|  |_
 |   -   ||  _  |  -__|     ||  |  |  ||   _||   _|
 |_______||   __|_____|__|__||________||__|  |____|
          |__| W I R E L E S S   F R E E D O M
 -----------------------------------------------------
 OpenWrt SNAPSHOT, r17668-6b4fa00317
 -----------------------------------------------------
=== WARNING! =====================================
There is no root password defined on this device!
Use the "passwd" command to set up a new password
in order to prevent unauthorized SSH logins.
--------------------------------------------------
root@OpenWrt:/# devmem 0x1b000ff8
0x0000000F
root@OpenWrt:/tmp# reboot
root@OpenWrt:/tmp# [  351.064036] device switch left promiscuous mode
[  351.966128] switch: port 5(lan5) entered disabled state
...
[  354.088495] device lan8 left promiscuous mode
[  354.146298] switch: port 8(lan8) entered disabled state
[  356.249143] reboot: Restarting system
[  356.297476] System restart.
[  356.334214] PLL control register: f, applying reset value efffffff
(stuck)
disable restoring pll reset value 
BusyBox v1.34.0 (2021-09-29 11:36:23 UTC) built-in shell (ash)

  _______                     ________        __
 |       |.-----.-----.-----.|  |  |  |.----.|  |_
 |   -   ||  _  |  -__|     ||  |  |  ||   _||   _|
 |_______||   __|_____|__|__||________||__|  |____|
          |__| W I R E L E S S   F R E E D O M
 -----------------------------------------------------
 OpenWrt SNAPSHOT, r17668-6b4fa00317
 -----------------------------------------------------
=== WARNING! =====================================
There is no root password defined on this device!
Use the "passwd" command to set up a new password
in order to prevent unauthorized SSH logins.
--------------------------------------------------
root@OpenWrt:/# devmem 0x1b000ff8
0x0000000F
root@OpenWrt:/tmp# reboot
root@OpenWrt:/tmp# [  351.064036] device switch left promiscuous mode
[  351.966128] switch: port 5(lan5) entered disabled state
[  352.230914] device lan1 left promiscuous mode
[  352.288754] switch: port 1(lan1) entered disabled state
[  352.643363] device lan2 left promiscuous mode
[  352.701220] switch: port 2(lan2) entered disabled state
[  353.237457] device lan3 left promiscuous mode
[  353.295279] switch: port 3(lan3) entered disabled state
[  353.379522] device lan4 left promiscuous mode
[  353.437359] switch: port 4(lan4) entered disabled state
[  353.520759] device lan5 left promiscuous mode
[  353.578602] switch: port 5(lan5) entered disabled state
[  353.659985] rtl83xx-switch switch@1b000000 lan5: Link is Down
[  353.735740] RTL8380 Link change: status: 1, ports 1000
[  353.805556] device lan6 left promiscuous mode
[  353.863374] switch: port 6(lan6) entered disabled state
[  353.947058] device lan7 left promiscuous mode
[  354.004852] switch: port 7(lan7) entered disabled state
[  354.088495] device lan8 left promiscuous mode
[  354.146298] switch: port 8(lan8) entered disabled state
[  356.249143] reboot: Restarting system
[  356.297476] System restart.
[  356.334214] PLL control register: f, applying reset value efffffff


U-Boot 2011.12.pre45842-1.00.22-svn5720 (Mar 12 2015 - 19:04:09)

Board: RTL838x CPU:500MHz LXB:200MHz MEM:300MHz
DRAM:  128 MB
SPI-F: 1x32 MB
...

APRESIA ApresiaLightGS120GT-SS (RTL8382M, 16 + 4 combo)

Flash: MX25L25635F

current master / disable restoring pll reset value 
BusyBox v1.34.0 (2021-09-29 11:36:23 UTC) built-in shell (ash)

  _______                     ________        __
 |       |.-----.-----.-----.|  |  |  |.----.|  |_
 |   -   ||  _  |  -__|     ||  |  |  ||   _||   _|
 |_______||   __|_____|__|__||________||__|  |____|
          |__| W I R E L E S S   F R E E D O M
 -----------------------------------------------------
 OpenWrt SNAPSHOT, r17664-8f5ee58e4a
 -----------------------------------------------------
=== WARNING! =====================================
There is no root password defined on this device!
Use the "passwd" command to set up a new password
in order to prevent unauthorized SSH logins.
--------------------------------------------------
root@OpenWrt:/# devmem 0x1b000ff8 32
0xEFFFFFFF
root@OpenWrt:/# reboot
root@OpenWrt:/# [  142.612286] device switch left promiscuous mode
[  143.495717] switch: port 20(lan9) entered disabled state
...
[  144.921043] device lan9 left promiscuous mode
[  144.926393] switch: port 20(lan9) entered disabled state
[  144.934678] in rtl838x_eth_stop
[  144.938429] rtl838x-eth 1b00a300.ethernet eth0: Link is Down
[  145.460657] rtl83xx-switch switch@1b000000 lan9: Link is Down
[  145.467183] RTL8380 Link change: status: 1, ports 100
[  147.727787] reboot: Restarting system
[  147.731908] System restart.
[  147.735022] PLL control register: efffffff, applying reset value efffffff
(stuck)
disable restoring pll reset value + set BIT(30)=0 in 0x1B000FF8 
BusyBox v1.34.0 (2021-09-29 11:36:23 UTC) built-in shell (ash)

  _______                     ________        __
 |       |.-----.-----.-----.|  |  |  |.----.|  |_
 |   -   ||  _  |  -__|     ||  |  |  ||   _||   _|
 |_______||   __|_____|__|__||________||__|  |____|
          |__| W I R E L E S S   F R E E D O M
 -----------------------------------------------------
 OpenWrt SNAPSHOT, r17665-bb2cf2b4f7
 -----------------------------------------------------
=== WARNING! =====================================
There is no root password defined on this device!
Use the "passwd" command to set up a new password
in order to prevent unauthorized SSH logins.
--------------------------------------------------
root@OpenWrt:/# devmem 0x1b000ff8 32
0xEFFFFFFF
root@OpenWrt:/# devmem 0x1b000ff8 32 0xAFFFFFFF
root@OpenWrt:/# devmem 0x1b000ff8 32
0xAFFFFFFF
root@OpenWrt:/# reboot
root@OpenWrt:/# [  514.782439] device switch left promiscuous mode
[  515.650467] switch: port 20(lan9) entered disabled state
...
[  517.092571] device lan9 left promiscuous mode
[  517.097924] switch: port 20(lan9) entered disabled state
[  517.106389] in rtl838x_eth_stop
[  517.110059] rtl838x-eth 1b00a300.ethernet eth0: Link is Down
[  517.632361] rtl83xx-switch switch@1b000000 lan9: Link is Down
[  517.638887] RTL8380 Link change: status: 1, ports 100
[  519.897804] reboot: Restarting system
[  519.901924] System restart.
[  519.905038] PLL control register: afffffff, applying reset value efffffff


U-Boot 2011.12.(2.1.5.67086)-Candidate1 (Apr 21 2020 - 16:39:05)
1.00.013

Board: RTL838x CPU:500MHz LXB:200MHz MEM:300MHz
DRAM:  256 MB
SPI-F: 1x32 MB
...

The address mode of the flash controller may be reset by the kernel before system reset.

BTW, Panasonic Switch-M*eG PN28xx0K series also have a GPIO pin on PCA9539 for hard-reset.