Support for RTL838x based managed switches

For Developers
727

Thank you, I tried your patch with the following change, it solves the issue. :wink:

additional change 
diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl839x.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl839x.c
index bdf60f0671..480a0f45a2 100644
--- a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl839x.c
+++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl839x.c
@@ -495,7 +495,7 @@ int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
 	if (port > 63 || page > 4095 || reg > 31)
 		return -ENOTSUPP;
 
-	if (port > 52 && version <= 2)
+	if (port >= 52 && version <= 2)
 		return -EIO;
 
 	mutex_lock(&smi_lock);
728

Excellent! On my version of GS1900-48 it also works, although the real test would be a device with more than 52 ports. Will you submit this as a patch?
In the longer term, a really clean solution would be to sort out the calling of the read/write functions to the PHY. It might be possible to modify rtl839x_mdio_read(), which is called in contexts where the MDIO-bus is available to do the version check, to do the SoC revision check. That function has access to the version via the mdio bus having a private data member for a driver (which is the Ethernet driver, not the DSA switch driver, where currently the version is stored, the Ethernet hardware of the SoCs seems to be much more stable and revision independent). Then one would need to stop calling ```
rtl839x_read_phy
directly. But it could be messy, because I am not sure everywhere the mdio-bus structure pointer is available for the call. At least the phy driver code could be cleaned up that way by using everywhere phy_read() and phy_write(), which is a convenience function to call the right rtlxxxx_mdio_read(), it is on my TODO list since quite some time...

1 Like
729

Is 52 not enough for RTL839x SoC? Looking at Realtek's product pages, RTL8393M seems to support the largest number of ports (52) in the series.

If you are OK, could you please put a commit into your PR that is currently open?

730

OK, I thought that they supported up to 56, because that is where the CPU-port sits. I'll add this to the open PR.

1 Like
731

Understand, I looked at the following and knew that the port is up to 52 on RTL839x...

732

Adding the compatible property works, adding the magic is not necessary and leads to a kernel panic when booting the flashed sysupgrade:

Boot log 
Starting kernel ...

[    0.000000] Linux version 5.4.143 (edwin@medusa) (gcc version 10.3.0 (OpenWrt GCC 10.3.0 r17476-27a99e40f7)) #0 Sat Sep 11 08:16:17 2021
[    0.000000] RTL838X model is ffffffff
[    0.000000] RTL839X model is 83936802
[    0.000000] SoC Type: RTL8393
[    0.000000] Kernel command line: 
[    0.000000] printk: bootconsole [early0] enabled
[    0.000000] CPU0 revision is: 00019555 (MIPS 34Kc)
[    0.000000] MIPS: machine is Zyxel GS1900-48
[    0.000000] Registering _machine_restart
[    0.000000] Initrd not found or empty - disabling initrd
[    0.000000] Using appended Device Tree.
[    0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[    0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[    0.000000] Zone ranges:
[    0.000000]   Normal   [mem 0x0000000000000000-0x0000000007ffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000000000000-0x0000000007ffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff]
[    0.000000] On node 0 totalpages: 32768
[    0.000000]   Normal zone: 288 pages used for memmap
[    0.000000]   Normal zone: 0 pages reserved
[    0.000000]   Normal zone: 32768 pages, LIFO batch:7
[    0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
[    0.000000] pcpu-alloc: [0] 0 
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 32480
[    0.000000] Kernel command line: console=ttyS0,115200
[    0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes, linear)
[    0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes, linear)
[    0.000000] Writing ErrCtl register=000297f0
[    0.000000] Readback ErrCtl register=000297f0
[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[    0.000000] Memory: 121908K/131072K available (5122K kernel code, 169K rwdata, 1116K rodata, 1200K init, 199K bss, 9164K reserved, 0K cma-reserved)
[    0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[    0.000000] NR_IRQS: 32
[    0.000000] random: get_random_bytes called from start_kernel+0x288/0x468 with crng_init=0
[    0.000000] timer_probe: no matching timers found
[    0.000000] CPU frequency from device tree: 700MHz
[    0.000000] clocksource: MIPS: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 5460744132 ns
[    0.000009] sched_clock: 32 bits at 350MHz, resolution 2ns, wraps every 6135667710ns
[    0.009211] Calibrating delay loop... 464.48 BogoMIPS (lpj=2322432)
[    0.076462] pid_max: default: 32768 minimum: 301
[    0.082092] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
[    0.090663] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
[    0.106718] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.118307] futex hash table entries: 256 (order: -1, 3072 bytes, linear)
[    0.126404] pinctrl core: initialized pinctrl subsystem
[    0.133119] NET: Registered protocol family 16
[    0.170068] workqueue: max_active 576 requested for napi_workq is out of range, clamping between 1 and 512
[    0.185124] clocksource: Switched to clocksource MIPS
[    0.192234] NET: Registered protocol family 2
[    0.197467] IP idents hash table entries: 2048 (order: 2, 16384 bytes, linear)
[    0.206600] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
[    0.216476] TCP established hash table entries: 1024 (order: 0, 4096 bytes, linear)
[    0.225471] TCP bind hash table entries: 1024 (order: 0, 4096 bytes, linear)
[    0.233767] TCP: Hash tables configured (established 1024 bind 1024)
[    0.241434] UDP hash table entries: 256 (order: 0, 4096 bytes, linear)
[    0.249136] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes, linear)
[    0.257642] NET: Registered protocol family 1
[    0.267498] workingset: timestamp_bits=14 max_order=15 bucket_order=1
[    0.282574] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.289423] jffs2: version 2.2 (NAND) (SUMMARY) (ZLIB) (LZMA) (RTIME) (CMODE_PRIORITY) (c) 2001-2006 Red Hat, Inc.
[    0.321687] pinctrl-single bb001000.pinmux: 32 pins, size 4
[    0.328597] Probing RTL8231 GPIOs
[    0.332415] rtl8231_init called, MDIO bus ID: 3
[    0.339323] Probing RTL838X GPIOs
[    0.383174] Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
[    0.391721] printk: console [ttyS0] disabled
[    0.396788] b8002000.uart: ttyS0 at MMIO 0xb8002000 (irq = 31, base_baud = 12500000) is a 16550A
[    0.407123] printk: console [ttyS0] enabled
[    0.407123] printk: console [ttyS0] enabled
[    0.417059] printk: bootconsole [early0] disabled
[    0.417059] printk: bootconsole [early0] disabled
[    0.429074] b8002100.uart: ttyS1 at MMIO 0xb8002100 (irq = 30, base_baud = 12500000) is a 16550A
[    0.581123] brd: module loaded
[    0.585200] Initializing rtl838x_nor_driver
[    0.590213] SPI resource base is b8001200
[    0.594990] Address mode is 3 bytes
[    0.599193] rtl838x_nor_init called
[    0.608329] rtl838x-nor b8001200.spi: mx25l12805d (16384 Kbytes)
[    0.615593] 7 fixed-partitions partitions found on MTD device rtl838x_nor
[    0.623690] Creating 7 MTD partitions on "rtl838x_nor":
[    0.629965] 0x000000000000-0x000000040000 : "u-boot"
[    0.636999] 0x000000040000-0x000000050000 : "u-boot-env"
[    0.644404] 0x000000050000-0x000000060000 : "u-boot-env2"
[    0.651961] 0x000000060000-0x000000160000 : "jffs"
[    0.658800] 0x000000160000-0x000000260000 : "jffs2"
[    0.665742] 0x000000260000-0x000000930000 : "firmware"
[    0.687164] 0x000000930000-0x000001000000 : "runtime2"
[    0.695644] libphy: Fixed MDIO Bus: probed
[    0.702988] Probing RTL838X eth device pdev: 87c9aa00, dev: 87c9aa10
[    0.727116] Found SoC ID: 8393: RTL8393, family 8390
[    0.733065] Using MAC 0000588bf3fe05d5
[    0.737974] libphy: rtl839x-eth-mdio: probed
[    0.865657] rtl8393_serdes_probe: id: 48
[    0.870352] Realtek RTL8393 SERDES mdio-bus:30: Detected internal RTL8390 SERDES
[    0.881114] rtl8393_serdes_probe: id: 49
[    0.885858] Realtek RTL8393 SERDES mdio-bus:31: Detected internal RTL8390 SERDES
[    0.897300] NET: Registered protocol family 10
[    0.907738] Segment Routing with IPv6
[    0.912219] NET: Registered protocol family 17
[    0.917931] 8021q: 802.1Q VLAN Support v1.8
[    0.923812] i2c-gpio i2c-gpio-0: Slow GPIO pins might wreak havoc into I2C/SMBus bus timing
[    0.933992] i2c-gpio i2c-gpio-0: using lines 184 (SDA) and 185 (SCL)
[    0.941930] i2c-gpio i2c-gpio-1: Slow GPIO pins might wreak havoc into I2C/SMBus bus timing
[    0.952079] i2c-gpio i2c-gpio-1: using lines 190 (SDA) and 191 (SCL)
[    0.959998] libphy: SFP I2C Bus: probed
[    0.964925] sfp sfp-p9: Host maximum power 1.0W
[    0.970796] libphy: SFP I2C Bus: probed
[    0.975795] sfp sfp-p10: Host maximum power 1.0W
[    1.090200] libphy: rtl838x slave mii: probed
[    1.096959] In rtl83xx_vlan_setup
[    1.100924] UNKNOWN_MC_PMASK: 001fffffffffffff
[    1.106268] VLAN profile 0: L2 learning: 1, UNKN L2MC FLD PMSK 511,          UNKN IPMC FLD PMSK 511, UNKN IPv6MC FLD PMSK: 511
[    1.106275] VLAN profile 0: raw 000001ff, 003fe3ff
[    2.307765] sfp sfp-p10: please wait, module slow to respond
[    2.595107] random: fast init done
[    3.236770] rtl83xx-switch switch@bb000000 lan01 (uninitialized): PHY [mdio-bus:00] driver [Realtek RTL8218B (external)]
[    3.252411] rtl83xx-switch switch@bb000000 lan02 (uninitialized): PHY [mdio-bus:01] driver [Realtek RTL8218B (external)]
[    3.268054] rtl83xx-switch switch@bb000000 lan03 (uninitialized): PHY [mdio-bus:02] driver [Realtek RTL8218B (external)]
[    3.283243] rtl83xx-switch switch@bb000000 lan04 (uninitialized): PHY [mdio-bus:03] driver [Realtek RTL8218B (external)]
[    3.298884] rtl83xx-switch switch@bb000000 lan05 (uninitialized): PHY [mdio-bus:04] driver [Realtek RTL8218B (external)]
[    3.314526] rtl83xx-switch switch@bb000000 lan06 (uninitialized): PHY [mdio-bus:05] driver [Realtek RTL8218B (external)]
[    3.330169] rtl83xx-switch switch@bb000000 lan07 (uninitialized): PHY [mdio-bus:06] driver [Realtek RTL8218B (external)]
[    3.345812] rtl83xx-switch switch@bb000000 lan08 (uninitialized): PHY [mdio-bus:07] driver [Realtek RTL8218B (external)]
[    3.361000] rtl83xx-switch switch@bb000000 lan09 (uninitialized): PHY [mdio-bus:08] driver [Realtek RTL8218B (external)]
[    3.376643] rtl83xx-switch switch@bb000000 lan10 (uninitialized): PHY [mdio-bus:09] driver [Realtek RTL8218B (external)]
[    3.391832] rtl83xx-switch switch@bb000000 lan11 (uninitialized): PHY [mdio-bus:0a] driver [Realtek RTL8218B (external)]
[    3.407473] rtl83xx-switch switch@bb000000 lan12 (uninitialized): PHY [mdio-bus:0b] driver [Realtek RTL8218B (external)]
[    3.423116] rtl83xx-switch switch@bb000000 lan13 (uninitialized): PHY [mdio-bus:0c] driver [Realtek RTL8218B (external)]
[    3.438757] rtl83xx-switch switch@bb000000 lan14 (uninitialized): PHY [mdio-bus:0d] driver [Realtek RTL8218B (external)]
[    3.454400] rtl83xx-switch switch@bb000000 lan15 (uninitialized): PHY [mdio-bus:0e] driver [Realtek RTL8218B (external)]
[    3.470041] rtl83xx-switch switch@bb000000 lan16 (uninitialized): PHY [mdio-bus:0f] driver [Realtek RTL8218B (external)]
[    3.485685] rtl83xx-switch switch@bb000000 lan17 (uninitialized): PHY [mdio-bus:10] driver [Realtek RTL8218B (external)]
[    3.500873] rtl83xx-switch switch@bb000000 lan18 (uninitialized): PHY [mdio-bus:11] driver [Realtek RTL8218B (external)]
[    3.516517] rtl83xx-switch switch@bb000000 lan19 (uninitialized): PHY [mdio-bus:12] driver [Realtek RTL8218B (external)]
[    3.531705] rtl83xx-switch switch@bb000000 lan20 (uninitialized): PHY [mdio-bus:13] driver [Realtek RTL8218B (external)]
[    3.547346] rtl83xx-switch switch@bb000000 lan21 (uninitialized): PHY [mdio-bus:14] driver [Realtek RTL8218B (external)]
[    3.562988] rtl83xx-switch switch@bb000000 lan22 (uninitialized): PHY [mdio-bus:15] driver [Realtek RTL8218B (external)]
[    3.578630] rtl83xx-switch switch@bb000000 lan23 (uninitialized): PHY [mdio-bus:16] driver [Realtek RTL8218B (external)]
[    3.594272] rtl83xx-switch switch@bb000000 lan24 (uninitialized): PHY [mdio-bus:17] driver [Realtek RTL8218B (external)]
[    3.609914] rtl83xx-switch switch@bb000000 lan25 (uninitialized): PHY [mdio-bus:18] driver [Realtek RTL8218B (external)]
[    3.625558] rtl83xx-switch switch@bb000000 lan26 (uninitialized): PHY [mdio-bus:19] driver [Realtek RTL8218B (external)]
[    3.641200] rtl83xx-switch switch@bb000000 lan27 (uninitialized): PHY [mdio-bus:1a] driver [Realtek RTL8218B (external)]
[    3.656841] rtl83xx-switch switch@bb000000 lan28 (uninitialized): PHY [mdio-bus:1b] driver [Realtek RTL8218B (external)]
[    3.672482] rtl83xx-switch switch@bb000000 lan29 (uninitialized): PHY [mdio-bus:1c] driver [Realtek RTL8218B (external)]
[    3.688125] rtl83xx-switch switch@bb000000 lan30 (uninitialized): PHY [mdio-bus:1d] driver [Realtek RTL8218B (external)]
[    3.703766] rtl83xx-switch switch@bb000000 lan31 (uninitialized): PHY [mdio-bus:1e] driver [Realtek RTL8218B (external)]
[    3.719409] rtl83xx-switch switch@bb000000 lan32 (uninitialized): PHY [mdio-bus:1f] driver [Realtek RTL8218B (external)]
[    3.735050] rtl83xx-switch switch@bb000000 lan33 (uninitialized): PHY [mdio-bus:20] driver [Realtek RTL8218B (external)]
[    3.750693] rtl83xx-switch switch@bb000000 lan34 (uninitialized): PHY [mdio-bus:21] driver [Realtek RTL8218B (external)]
[    3.766337] rtl83xx-switch switch@bb000000 lan35 (uninitialized): PHY [mdio-bus:22] driver [Realtek RTL8218B (external)]
[    3.781525] rtl83xx-switch switch@bb000000 lan36 (uninitialized): PHY [mdio-bus:23] driver [Realtek RTL8218B (external)]
[    3.797166] rtl83xx-switch switch@bb000000 lan37 (uninitialized): PHY [mdio-bus:24] driver [Realtek RTL8218B (external)]
[    3.812807] rtl83xx-switch switch@bb000000 lan38 (uninitialized): PHY [mdio-bus:25] driver [Realtek RTL8218B (external)]
[    3.828450] rtl83xx-switch switch@bb000000 lan39 (uninitialized): PHY [mdio-bus:26] driver [Realtek RTL8218B (external)]
[    3.844092] rtl83xx-switch switch@bb000000 lan40 (uninitialized): PHY [mdio-bus:27] driver [Realtek RTL8218B (external)]
[    3.859734] rtl83xx-switch switch@bb000000 lan41 (uninitialized): PHY [mdio-bus:28] driver [Realtek RTL8218B (external)]
[    3.875377] rtl83xx-switch switch@bb000000 lan42 (uninitialized): PHY [mdio-bus:29] driver [Realtek RTL8218B (external)]
[    3.891019] rtl83xx-switch switch@bb000000 lan43 (uninitialized): PHY [mdio-bus:2a] driver [Realtek RTL8218B (external)]
[    3.906662] rtl83xx-switch switch@bb000000 lan44 (uninitialized): PHY [mdio-bus:2b] driver [Realtek RTL8218B (external)]
[    3.922302] rtl83xx-switch switch@bb000000 lan45 (uninitialized): PHY [mdio-bus:2c] driver [Realtek RTL8218B (external)]
[    3.937944] rtl83xx-switch switch@bb000000 lan46 (uninitialized): PHY [mdio-bus:2d] driver [Realtek RTL8218B (external)]
[    3.953586] rtl83xx-switch switch@bb000000 lan47 (uninitialized): PHY [mdio-bus:2e] driver [Realtek RTL8218B (external)]
[    3.969228] rtl83xx-switch switch@bb000000 lan48 (uninitialized): PHY [mdio-bus:2f] driver [Realtek RTL8218B (external)]
[    3.985404] rtl83xx-switch switch@bb000000: configuring for fixed/qsgmii link mode
[    3.994577] DSA: tree 0 setup
[    3.998199] LINK state irq: 20
[    4.001864] In rtl83xx_setup_qos
[    4.005738] Setting up RTL839X QoS
[    4.009791] RTL839X_PRI_SEL_TBL_CTRL(i): 01112111
[    4.015412] Current Intprio2queue setting: 00000000
[    4.021229] QM_PKT2CPU_INTPRI_MAP: 00fac688
[    4.026329] rtl838x_dbgfs_init called
[    4.058370] rtl83xx-switch switch@bb000000: Link is Up - 1Gbps/Full - flow control off
[    4.068226] /dev/root: Can't open blockdev
[    4.073125] VFS: Cannot open root device "(null)" or unknown-block(0,0): error -6
[    4.082097] Please append a correct "root=" boot option; here are the available partitions:
[    4.092089] 0100            4096 ram0 
[    4.092093]  (driver?)
[    4.099389] 0101            4096 ram1 
[    4.099392]  (driver?)
[    4.106683] 0102            4096 ram2 
[    4.106687]  (driver?)
[    4.113952] 0103            4096 ram3 
[    4.113955]  (driver?)
[    4.121244] 0104            4096 ram4 
[    4.121247]  (driver?)
[    4.128542] 0105            4096 ram5 
[    4.128545]  (driver?)
[    4.135835] 0106            4096 ram6 
[    4.135839]  (driver?)
[    4.143105] 0107            4096 ram7 
[    4.143108]  (driver?)
[    4.150397] 0108            4096 ram8 
[    4.150400]  (driver?)
[    4.157691] 0109            4096 ram9 
[    4.157695]  (driver?)
[    4.164961] 010a            4096 ram10 
[    4.164964]  (driver?)
[    4.172357] 010b            4096 ram11 
[    4.172360]  (driver?)
[    4.179758] 010c            4096 ram12 
[    4.179761]  (driver?)
[    4.187155] 010d            4096 ram13 
[    4.187159]  (driver?)
[    4.194529] 010e            4096 ram14 
[    4.194531]  (driver?)
[    4.201924] 010f            4096 ram15 
[    4.201927]  (driver?)
[    4.209326] 1f00             256 mtdblock0 
[    4.209329]  (driver?)
[    4.217138] 1f01              64 mtdblock1 
[    4.217141]  (driver?)
[    4.224927] 1f02              64 mtdblock2 
[    4.224930]  (driver?)
[    4.232737] 1f03            1024 mtdblock3 
[    4.232741]  (driver?)
[    4.240553] 1f04            1024 mtdblock4 
[    4.240556]  (driver?)
[    4.248399] 1f05            6976 mtdblock5 
[    4.248404]  (driver?)
[    4.256215] 1f06            6976 mtdblock6 
[    4.256218]  (driver?)
[    4.264008] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)
[    4.273871] Rebooting in 1 seconds..
[    5.273508] System restart.II: Copied Preloader data from 0x9fc00000(15804B) to 0x9f000000.

I'm still not sure whether we need "openwrt,uimage" in compatible. Is there any harm in keeping it?

733

Ouch, I had the 56 in mind. Need to spend more time with the 8393 target. Anyway, then I will generally limit the IO to smaller than PHY-address 52 in both the read and write routines.

1 Like
734

It must be synchronised with the magic you are using. So if you leave that at default in the image Makefile, then it must be left at default in the splitter config in the DTS too.

The U-Boot in the ZyXEL switches doesn't care, so either will work. But IMHO we should use the same magic the OEM firmware uses, to ensure maximu compatibility.

It's only needed if you use any of the openwrt specific properties. Having it there doesn't harm.

1 Like
735

@svanheule looks like the link is down, so I can't see it. Do you think we need to modify the reason value somewhere?

I tried reverting openwrt to revision daa5860 (this is before a bunch of multicast and other commits, see the history here). In this revision, it appears that VLAN 1 has no flooding issue, although other VLANs (2 and 100) do. This matches @akron's experience that switching the management VLAN from 100 to 1 fixes the flooding problem. Unfortunately, on openwrt master, I believe there is flooding on all VLANs including VLAN 1. So there may have been a problem introduced like @anon13997276 suggested. Maybe on reset, the switch has some default config that avoids flooding issue for VLAN 1.

736

@svanheule sorry for the ping, just wanted to inquire if there's been any progress on merging the patches required for supporting the port LEDs, either to OpenWrt, or mainline Linux. Are there any blockers as of now?

737

Who can I talk to about adding support for the RTL9301 series of switches?

738

That would be @anon13997276 I guess. See also his xgs1250 branch: https://github.com/bkobl/openwrt/tree/xgs1250

739

RTL9301 support is basically done, what is missing is the 10GBit SFP+ ports and IPv6 L3 offloading (most of IPv4 L3 offloading works). Two routers using the RTL9301 have support, the Zyxel XGS1210-12 and the XGS1250-12.
The RTL9301 support is in this PR:

The DTS for the XGS switches can be found here:

In the same tree is also 10GBit support for the 3 Aquantia AQR113c PHYs that provide the multi-gbit support, the PR does only 5GBit.

1 Like
740

This is great. I would need to use the 10G SPF+ ports, so will that feature eventually work or what's preventing those ports from working?

For PoE support with RTL9301, what PoE chipset's are supported? What about the PSE chip HS104PTI and HS104PBI? It is controlled by 12C register control, whatever that means.
http://www.poeplus.com/?s=S3024P-4SE

1 Like
741

The SFP+ ports are being intermittently worked on since months, but although there is complete GPL source code for this, they are very difficult to set up. While there is progress in understanding, there is no breakthrough yet. So I cannot give you any time estimate. Even if we get it working this week, it would still take months until it shows up in a stable release.

How did you find the reference to those PoE Chips? I assume 12C is i2c. So far there is no support for these kind of chips.The ones supported are Brodcom and are controlled via UART and an intermediary ARM SoC. I cannot give you an estimate whether and when there will be support. Also because none of the devs have one of these devices.

2 Likes
742

Website is online again. I haven't actually worked with the network hardware/driver, I've only been putting together the info we have on it (that I know of).

As far as I understand, the reason field is provided by the switch on received frames. You could modify it, but that would be meaningless. For a more complete/correct interpretation of all the fields and features, someone else will have to fill it out.

743

The RTL8231 driver is currently stranded upstream, due to some missing feature in the kernel's regmap interface. Part of that driver could also be used for an upstream LED driver, but also there I can't really provide a time frame.

744

Ah, makes sense. Thanks for the clarification. I did try to ascertain this conclusion from your previous comments and linked patches, but it wasn't completely clear.

Do you see any chance of these missing features being implemented in kernel 5.14?

745

I just asked the seller which PoE chipset was in this switch. I am open to purchasing / providing one of these to the devs, so let me know who would be responsible for implementing such a solution.

746

I guess @svanheule is the right person, he really dug into the protocol of the other PoE chips. He also knows how to analyze busses like the I2C.

BTW: currently there is a big effort together with brainslayer from DD-WRT to get support for RTL931x-based switches done. This will include their SFP+ ports which look pretty much similar to the ones on the 930x. So maybe going that route will finally crack this problem. Status at this point is: the switches boot, including SMP!

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