Support for RTL838x based managed switches

plappermaul · March 17, 2025, 7:43pm

This is only half of the truth.

The SERDES hardware mode can be set individually for each serdes by SDS_MODE_SEL_x registers. See rtsds_930x_set_hwmode() in my last try to get SerDes support upstream.

The code you are talking about is for configuring the clock managment unit of a SerDes pair. Similar code for RTL931x:

_dal_mango_construct_cmuType_set(uint32 unit, uint32 aSds, rtk_serdesMode_t mode)
{
    dal_mango_sds_cmutype_t cmuType = DAL_MANGO_SDS_CMU_END;
    uint32                  cmuPage = 0;
    uint32                  frc_cmu_spd;
    uint32                  evenSds;
    uint32                  lane, frc_lc_mode_bitnum, frc_lc_mode_val_bitnum;
    int32                   ret;

    switch (mode)
    {
        case RTK_MII_DISABLE:
        case RTK_MII_10GR:
        case RTK_MII_XSGMII:
        //case RTK_MII_USXGMII:
        case RTK_MII_USXGMII_10GSXGMII:
        case RTK_MII_USXGMII_10GDXGMII:
        case RTK_MII_USXGMII_10GQXGMII:
        case RTK_MII_USXGMII_5GSXGMII:
        case RTK_MII_USXGMII_5GDXGMII:
        case RTK_MII_USXGMII_2_5GSXGMII:
            return RT_ERR_OK;
        case RTK_MII_10GR1000BX_AUTO:
            if (IF_CHIP_TYPE_1(unit))
            {
                RT_ERR_CHK(SDS_FIELD_W(unit, aSds, 0x24, 0xd, 14, 14, 0), ret);
            }
            return RT_ERR_OK;
        case RTK_MII_QSGMII:
            cmuType = DAL_MANGO_SDS_CMU_RING;
            cmuPage = 0x2a;
            frc_cmu_spd = 0;
            break;
        case RTK_MII_HISGMII:
            cmuType = DAL_MANGO_SDS_CMU_RING;
            cmuPage = 0x28;
            frc_cmu_spd = 1;
            break;
        case RTK_MII_XSMII:
            cmuType = DAL_MANGO_SDS_CMU_RING;
            cmuPage = 0x26;
            frc_cmu_spd = 0;
            break;
        case RTK_MII_1000BX_FIBER:
            cmuType = DAL_MANGO_SDS_CMU_RING;
            cmuPage = 0x24;
            frc_cmu_spd = 0;
            break;
        case RTK_MII_100BX_FIBER:
            cmuType = DAL_MANGO_SDS_CMU_RING;
            cmuPage = 0x24;
            frc_cmu_spd = 0;
            break;
        case RTK_MII_1000BX100BX_AUTO:
            cmuType = DAL_MANGO_SDS_CMU_RING;
            cmuPage = 0x24;
            frc_cmu_spd = 0;
            break;
        case RTK_MII_SGMII:
            cmuType = DAL_MANGO_SDS_CMU_RING;
            cmuPage = 0x24;
            frc_cmu_spd = 0;
            break;
        case RTK_MII_2500Base_X:
            cmuType = DAL_MANGO_SDS_CMU_RING;
            cmuPage = 0x28;
            frc_cmu_spd = 1;
            break;
        default:
            osal_printf("SerDes %d mode is invalid\n", aSds);
            return RT_ERR_FAILED;
    }

    lane = aSds % 2;

    if (0 == lane)
    {
        frc_lc_mode_bitnum = 4;
        frc_lc_mode_val_bitnum = 5;
    }
    else
    {
        frc_lc_mode_bitnum = 6;
        frc_lc_mode_val_bitnum = 7;
    }

    evenSds = aSds - lane;
    if (DAL_MANGO_SDS_CMU_RING == cmuType)
    {
        RT_ERR_CHK(SDS_FIELD_W(unit, aSds, cmuPage, 0x7, 15, 15, 0), ret);
        if (IF_CHIP_TYPE_1(unit))
        {
            RT_ERR_CHK(SDS_FIELD_W(unit, aSds, cmuPage, 0xd, 14, 14, 0), ret);
        }

        RT_ERR_CHK(SDS_FIELD_W(unit, evenSds, 0x20, 0x12, 3, 2, 0x3), ret);
        RT_ERR_CHK(SDS_FIELD_W(unit, evenSds, 0x20, 0x12, frc_lc_mode_bitnum, frc_lc_mode_bitnum, 1), ret);
        RT_ERR_CHK(SDS_FIELD_W(unit, evenSds, 0x20, 0x12, frc_lc_mode_val_bitnum, frc_lc_mode_val_bitnum, 0), ret);
        RT_ERR_CHK(SDS_FIELD_W(unit, evenSds, 0x20, 0x12, 12, 12, 1), ret);
        RT_ERR_CHK(SDS_FIELD_W(unit, evenSds, 0x20, 0x12, 15, 13, frc_cmu_spd), ret);
    }
    else if (DAL_MANGO_SDS_CMU_LC == cmuType)
    {
        RT_ERR_CHK(SDS_FIELD_W(unit, aSds, cmuPage, 0x7, 15, 15, 1), ret);
        if (IF_CHIP_TYPE_1(unit))
        {
            RT_ERR_CHK(SDS_FIELD_W(unit, aSds, cmuPage, 0xd, 14, 14, 1), ret);
        }

        RT_ERR_CHK(SDS_FIELD_W(unit, evenSds, 0x20, 0x12, 1, 0, 0x3), ret);
        RT_ERR_CHK(SDS_FIELD_W(unit, evenSds, 0x20, 0x12, frc_lc_mode_bitnum, frc_lc_mode_bitnum, 1), ret);
        RT_ERR_CHK(SDS_FIELD_W(unit, evenSds, 0x20, 0x12, frc_lc_mode_val_bitnum, frc_lc_mode_val_bitnum, 1), ret);
        RT_ERR_CHK(SDS_FIELD_W(unit, evenSds, 0x20, 0x12, 8, 8, 1), ret);
        RT_ERR_CHK(SDS_FIELD_W(unit, evenSds, 0x20, 0x12, 11, 9, frc_cmu_spd), ret);
    }

    return RT_ERR_OK;
}
````Preformatted text`

howels · March 18, 2025, 7:47pm

Found another switch on AliExpress that looks identical to the Onti ONT-S508CL-8S but with a different name, very cheap currently due to a promotion.

Can't be sure but it certainly is a visual match.

RadxaNaoki · March 19, 2025, 3:26am

This is from the same seller, I asked if it was the same one and they said it was, so I guess the "OM" stands for OMAY.

I also asked them to send me the photos.

antanas · March 19, 2025, 7:12am

Hi,
I have ZyXEL XGS1250-12 Rev. B1.
Apparently revision B1 is a bit different compared to A1. I did put openwrt on it but only eight 1G ports work as generic phy. SFP+ is also recognized.

[    0.734564] mdio_bus mdio-bus: MDIO device at address 24 is missing.
[    0.748185] mdio_bus mdio-bus: MDIO device at address 25 is missing.
[    0.761702] mdio_bus mdio-bus: MDIO device at address 26 is missing.
[    0.772453] REALTEK RTL9300 SERDES mdio-bus:1b: Detected internal RTL9300 Serdes
[    0.790125] i2c_dev: i2c /dev entries driver
[    0.795062] rtl9300_i2c_probe probing I2C adapter
[    0.800404] i2c-rtl9300 1b00036c.i2c-rtl9300: SCL speed 100000, mode is 0
[    0.808000] rtl9300_i2c_probe scl_num 0
[    0.812269] rtl9300_i2c_probe sda_num 1
[    0.821094] NET: Registered PF_INET6 protocol family
[    0.843239] Segment Routing with IPv6
[    0.847517] In-situ OAM (IOAM) with IPv6
[    0.852119] NET: Registered PF_PACKET protocol family
[    0.858208] 8021q: 802.1Q VLAN Support v1.8
[    0.885399] sfp sfp-p12: Host maximum power 1.0W
[    0.955754] REALTEK RTL9300 SERDES rtl838x slave mii-0:1b: Detected internal RTL9300 Serdes
[    0.977181] REALTEK RTL9300 SERDES rtl838x slave mii-0:3f: Detected internal RTL9300 Serdes
[    0.996786] rtl93xx_setup called
[    1.000437] In rtl83xx_vlan_setup
[    1.004113] UNKNOWN_MC_PMASK: 000000001fffffff
[    2.095187] rtl83xx_enable_phy_polling:          f0000ff
[    2.101456] rtl930x_led_init led_set configuration invalid skipping over this set
[    2.110005] rtl83xx-switch switch@1b000000: configuring for fixed/internal link mode
[    2.120335] rtl83xx-switch switch@1b000000 lan1 (uninitialized): PHY [mdio-bus:00] driver [Generic PHY] (irq=POLL)
[    2.134752] rtl83xx-switch switch@1b000000 lan2 (uninitialized): PHY [mdio-bus:01] driver [Generic PHY] (irq=POLL)
[    2.149266] rtl83xx-switch switch@1b000000 lan3 (uninitialized): PHY [mdio-bus:02] driver [Generic PHY] (irq=POLL)
[    2.163771] rtl83xx-switch switch@1b000000 lan4 (uninitialized): PHY [mdio-bus:03] driver [Generic PHY] (irq=POLL)
[    2.178242] rtl83xx-switch switch@1b000000 lan5 (uninitialized): PHY [mdio-bus:04] driver [Generic PHY] (irq=POLL)
[    2.192712] rtl83xx-switch switch@1b000000 lan6 (uninitialized): PHY [mdio-bus:05] driver [Generic PHY] (irq=POLL)
[    2.207314] rtl83xx-switch switch@1b000000 lan7 (uninitialized): PHY [mdio-bus:06] driver [Generic PHY] (irq=POLL)
[    2.221757] rtl83xx-switch switch@1b000000 lan8 (uninitialized): PHY [mdio-bus:07] driver [Generic PHY] (irq=POLL)
[    2.234952] rtl83xx-switch switch@1b000000 lan9 (uninitialized): no phy at 24
[    2.242989] rtl83xx-switch switch@1b000000 lan9 (uninitialized): failed to connect to PHY: -ENODEV
[    2.253004] rtl83xx-switch switch@1b000000 lan9 (uninitialized): error -19 setting up PHY for tree 0, switch 0, port 24
[    2.265303] rtl83xx-switch switch@1b000000 lan10 (uninitialized): no phy at 25
[    2.273360] rtl83xx-switch switch@1b000000 lan10 (uninitialized): failed to connect to PHY: -ENODEV
[    2.283476] rtl83xx-switch switch@1b000000 lan10 (uninitialized): error -19 setting up PHY for tree 0, switch 0, port 25
[    2.295839] rtl83xx-switch switch@1b000000 lan11 (uninitialized): no phy at 26
[    2.303896] rtl83xx-switch switch@1b000000 lan11 (uninitialized): failed to connect to PHY: -ENODEV
[    2.314018] rtl83xx-switch switch@1b000000 lan11 (uninitialized): error -19 setting up PHY for tree 0, switch 0, port 26

The differences that I've noticed is the switch chip is RTL8218E compared to the previous RTL8218D
And the chips next to 3 multigig ports are RTL8261BE instead of marvell Aquantia AQR113C.
See the photos:

plappermaul · March 19, 2025, 8:17am

RTL8218E datasheet added to https://github.com/plappermaul/realtek-doc

antanas · March 19, 2025, 6:09pm

Thanks. Based on this I've created a pull request for RTL8218E - https://github.com/openwrt/openwrt/pull/18302

Do you by any chance know if it's possible to get a datasheet for RTL8261BE?

plappermaul · March 19, 2025, 6:32pm

This is closest I see https://github.com/plappermaul/realtek-doc/blob/main/RTL8261N.pdf

andrewjlamarche · March 19, 2025, 8:09pm

Do you have anything for RTL8264 too?

plappermaul · March 19, 2025, 8:36pm

OpenWRT already has an offical driver for both chips in main https://git.openwrt.org/?p=openwrt/openwrt.git;a=tree;f=target/linux/generic/files/drivers/net/phy/rtl8261n;h=f714ed37d5e73d48ea2decb3c535f6fb2b847bd5;hb=refs/heads/main

antanas · March 19, 2025, 8:47pm

Any idea of how to make use of it for ZyXEL XGS1250-12 Rev. B1?

luckylinux · March 21, 2025, 4:00pm

Does anybody know if the mixed 2.5G RJ45 and 10G SFP+ such as are supported ?

ONTI ONT-S207CW-62TS
ONTI ONT-S207CW-61TS
ONTI ONT-S207CW-91TS

janh · March 22, 2025, 1:48pm

The port combination and price range of the ONT-S207CW series smells like RTL837x. If that guess is correct, then OpenWrt support is impossible, because the CPU is just a 8051.

Only the ONT-S207CW-72TS is likely RTL930x: Hasivo switches - #174 by Whiterat

Borromini · March 23, 2025, 12:22pm

@janh I have pulled your rt930x patches to test on my XGS1210-12 v2 with RTL8221 2,5 GbE PHYs.

blunden · March 23, 2025, 1:09pm

The Broadcom based ones rated for 80 or 100 meters used to be very expensive, but can now be found on AliExpress for reasonable prices from a few brands.

Xicom (select the 80 m model):

ZYOPM (select the 80 m model):

I have personally tested the Xicom 80 m transceiver and can confirm that it reports temperature readings. It reports itself as as 10GBASE-SR fiber transceiver for compatibility reasons, and is something that seems to be standard practice. @bmork

Xicom claims that it uses the BCM84891LB in the 80 m model, and Aquantia 113C in the 30 m model.

howels · March 23, 2025, 1:21pm

The ZYOPM 80m one also supports temperature and power readings. Been running it without many problems although my SFP+ modules seem to have issues with a reboot and only work properly once re-seated or swapped between slots after a reboot. Probably some hangover of the bootloader initialisation routine interfering with the driver.

blunden · March 23, 2025, 1:51pm

Ok, good. When I wrote that reply, I had not read the latest posts of the thread yet so I missed that there had already been a lot of additional discussions about these different AliExpress modules.

You can try setting the link speed and duplex manually instead of relying on auto-negotiation. That solved the behaviour you describe on the stock firmware of my Hasivo RTL9301 based switch.

howels · March 23, 2025, 9:34pm

I can't locate where interface speed is set in UCI, so much advice is "don't disable auto negotiation" which is fine for 1G devices with integrated phy but less helpful for 10G SFP+ devices.
Assuming this doesn't require falling back to ethtool commands?

TimSmall · March 24, 2025, 5:19pm

I wouldn't use an adapter in that sort of all-in-one formfactor, because I think it is a questionable mechanical design (too much leverage on the jack). Instead use a small "pigtail" style one with a bit of cable between the USB socket / trigger module and the barrel jack. Before such things were available as pre-built adapters, I used PD trigger modules from WeAct Studio - https://www.aliexpress.com/item/1005003336833794.html and just cut+soldered on the original cable from whatever power supply I didn't trust (with a bit of large size heatshrink tube around the PCB).

Alternatively 12v with 5.5 x 2.1 is a pretty common standard AC->DC adapter size, so you might be able to find a good brand name one in your local e-waste bin ;-).

For general diagnosing of PD stuff (e.g. listing what voltages and currents a power supply reports) as well as a very accurate voltage and current meter (using a Texas Instruments measurement IC), and bluetooth+USB data logging of voltage/current/power etc., I recommend the Ruideng TC66C (TC66 is the non-bluetooth version) - https://www.aliexpress.com/item/32968303350.html beware knock-offs sold elsewhere, both WeAct and Ruideng are trustworthy manufacturers and sell directly. For the TC66C, the YT channel TheHWcave has a great tutorial as well as pointers to open source logging software.

luckylinux · March 24, 2025, 6:49pm

I already bought them (both the "questionable" Adapter as well as the Cables e.g. https://www.aliexpress.com/item/1005006018729093.html and https://www.aliexpress.com/item/1005006058252700.html).

Not sure what you mean exactly by "Leverage". Do you mean a "Loose Fit" or a Lack of Strain Relief rather ?

It was also not very clear if it was 5.5x2.5mm or 5.5x2.1mm so I bought both of them again ...

For the TC66C, did you give me the link to the Official Store ? RD = Ruideng ?

Should I also get the HD35 Electronic Load or no need for that ?

Borromini · March 24, 2025, 8:20pm

@janh I have no baseline here, since last OpenWrt build I tried was main with 5.15 and olliver's patches for the XGS1210-12, slightly adapted for my B1 revision. But that did boot. I assume your tree is still booting for you on your XGS1010-12? I have pulled these commits into my tree, on top of main:

064cd9c7d4 realtek: add support for 10GBase-LR
762c1c3580 realtek: enable 2500Base-X interface mode
d2a45732c7 realtek: consider auto-negotiation state in rtl8226_set_eee
e36adccd08 realtek: improve RTL8226 support
91852fd7c2 realtek: call rtl9300_serdes_setup for additional PHY interface modes
a4f4363618 realtek: fix HSGMII PHY mode
f6e2a1a5e6 realtek: refactor RTL930x MAC config to fix PHY ports

Then a basic patch on top for the XGS1210-12 support:

https://dpaste.com/292V9SNNK.txt

I'm addressing this question to anyone knowledgeable of course. The 5.15 log would show the device booting through all the way to a prompt, but the 6.6 boot hangs here:

[    0.773224] Probing RTL838X eth device pdev: 820a8400, dev: 820a8410
[    0.799573] Found SoC ID: 9302: RTL9302B, family 9300

I noticed the 5.15 log would show a different identifier (?) for the 'eth device pdev', not sure if that's relevant?

[    0.519562] Probing RTL838X eth device pdev: 82085a00, dev: 82085a10
[    0.546175] Found SoC ID: 9302: RTL9302B, family 9300

It looks like what could be a PCI ID, but I'm not sure it actually is something like that.

6.6 boot log

Summary

RTL9300# # bootm

Booting kernel from Legacy Image at 84f00000 ...

Image Name: MIPS OpenWrt Linux-6.6.83
Created: 2025-03-23 10:28:45 UTC
Image Type: MIPS Linux Kernel Image (gzip compressed)
Data Size: 8385817 Bytes = 8 MB
Load Address: 80100000
Entry Point: 80100000
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK

Starting kernel ...

[ 0.000000] Linux version 6.6.83 (5800X@crunchbot) (mips-openwrt-linux-musl-gcc (OpenWrt GCC 13.3.0 r29070+8-8d1fe32c2c) 13.3.0, GNU ld (GNU Binutils) 2.42) #0 Sun Mar 23 10:28:45 2025
[ 0.000000] RTL838X model is 0
[ 0.000000] RTL839X model is 0
[ 0.000000] RTL93XX model is 93021001
[ 0.000000] SoC Type: RTL9302B
[ 0.000000] printk: bootconsole [early0] enabled
[ 0.000000] CPU0 revision is: 00019555 (MIPS 34Kc)
[ 0.000000] MIPS: machine is Zyxel XGS1210-12 v2 Switch
[ 0.000000] earlycon: ns16550a0 at MMIO 0x18002000 (options '115200n8')
[ 0.000000] printk: bootconsole [ns16550a0] enabled
[ 0.000000] Initrd not found or empty - disabling initrd
[ 0.000000] Using appended Device Tree.
[ 0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[ 0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[ 0.000000] Zone ranges:
[ 0.000000] Normal [mem 0x0000000000000000-0x0000000007ffffff]
[ 0.000000] HighMem empty
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000000000000-0x0000000007ffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff]
[ 0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
[ 0.000000] pcpu-alloc: [0] 0
[ 0.000000] Kernel command line: earlycon
[ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes, linear)
[ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes, linear)
[ 0.000000] Writing ErrCtl register=000094e9
[ 0.000000] Readback ErrCtl register=000094e9
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 32480
[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[ 0.000000] Memory: 105672K/131072K available (6655K kernel code, 623K rwdata, 840K rodata, 15684K init, 245K bss, 25400K reserved, 0K cma-reserved, 0K highmem)
[ 0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[ 0.000000] NR_IRQS: 256
[ 0.000000] Failed to get CPU clock: -2
[ 0.000000] CPU frequency from device tree: 800MHz
[ 0.000000] clocksource: realtek_otto_timer: mask: 0xfffffff max_cycles: 0xfffffff, max_idle_ns: 38225208801 ns
[ 0.000002] sched_clock: 28 bits at 3125kHz, resolution 320ns, wraps every 42949672800ns
[ 0.009024] Calibrating delay loop... 531.66 BogoMIPS (lpj=2658304)
[ 0.065711] pid_max: default: 32768 minimum: 301
[ 0.080629] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
[ 0.088630] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
[ 0.106458] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1.
[ 0.121821] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[ 0.132614] futex hash table entries: 256 (order: -1, 3072 bytes, linear)
[ 0.142669] pinctrl core: initialized pinctrl subsystem
[ 0.151384] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[ 0.158498] thermal_sys: Registered thermal governor 'step_wise'
[ 0.174141] clocksource: Switched to clocksource realtek_otto_timer
[ 0.198656] NET: Registered PF_INET protocol family
[ 0.204348] IP idents hash table entries: 2048 (order: 2, 16384 bytes, linear)
[ 0.213165] tcp_listen_portaddr_hash hash table entries: 1024 (order: 0, 4096 bytes, linear)
[ 0.222478] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
[ 0.230974] TCP established hash table entries: 1024 (order: 0, 4096 bytes, linear)
[ 0.239381] TCP bind hash table entries: 1024 (order: 1, 8192 bytes, linear)
[ 0.247130] TCP: Hash tables configured (established 1024 bind 1024)
[ 0.254862] MPTCP token hash table entries: 512 (order: 0, 6144 bytes, linear)
[ 0.263031] UDP hash table entries: 256 (order: 0, 4096 bytes, linear)
[ 0.270248] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes, linear)
[ 0.278672] NET: Registered PF_UNIX/PF_LOCAL protocol family
[ 0.304485] workingset: timestamp_bits=14 max_order=15 bucket_order=1
[ 0.313063] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[ 0.319522] jffs2: version 2.2 (NAND) (SUMMARY) (ZLIB) (LZMA) (RTIME) (CMODE_PRIORITY) (c) 2001-2006 Red Hat, Inc.
[ 0.365201] pinctrl-single 1b00c600.pinmux: 32 pins, size 4
[ 0.371636] pinctrl-single 1b00cc00.pinmux: 32 pins, size 4
[ 0.379559] Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
[ 0.388237] printk: console [ttyS0] disabled
[ 0.393466] 18002000.uart: ttyS0 at MMIO 0x18002000 (irq = 30, base_baud = 10937500) is a 16550A
[ 0.403157] printk: console [ttyS0] enabled
[ 0.403157] printk: console [ttyS0] enabled
[ 0.412496] printk: bootconsole [early0] disabled
[ 0.412496] printk: bootconsole [early0] disabled
[ 0.444269] printk: bootconsole [ns16550a0] disabled
[ 0.444269] printk: bootconsole [ns16550a0] disabled
[ 0.505014] brd: module loaded
[ 0.524796] spi-nor spi0.0: mx25l12805d (16384 Kbytes)
[ 0.530639] 7 fixed-partitions partitions found on MTD device spi0.0
[ 0.537836] OF: Bad cell count for /soc/spi@1200/flash@0/partitions
[ 0.544886] OF: Bad cell count for /soc/spi@1200/flash@0/partitions
[ 0.552113] Creating 7 MTD partitions on "spi0.0":
[ 0.557512] 0x000000000000-0x0000000e0000 : "u-boot"
[ 0.594736] 0x0000000e0000-0x0000000f0000 : "u-boot-env"
[ 0.614529] 0x0000000f0000-0x000000100000 : "u-boot-env2"
[ 0.622006] 0x000000100000-0x000000200000 : "jffs"
[ 0.634582] 0x000000200000-0x000000300000 : "jffs2"
[ 0.654542] 0x000000300000-0x000000fe0000 : "firmware"
[ 0.661876] 2 uimage-fw partitions found on MTD device firmware
[ 0.668545] Creating 2 MTD partitions on "firmware":
[ 0.674078] 0x000000000000-0x000000200000 : "kernel"
[ 0.704739] 0x000000200000-0x000000ce0000 : "rootfs"
[ 0.711609] mtd: setting mtd7 (rootfs) as root device
[ 0.717390] 1 squashfs-split partitions found on MTD device rootfs
[ 0.724330] 0x000000590000-0x000000ce0000 : "rootfs_data"
[ 0.754737] 0x000000fe0000-0x000001000000 : "log"
[ 0.773224] Probing RTL838X eth device pdev: 820a8400, dev: 820a8410
[ 0.799573] Found SoC ID: 9302: RTL9302B, family 9300

5.15 boot log

Summary

RTL9300# # boota

Booting kernel from Legacy Image at 81000000 ...

Image Name: MIPS OpenWrt Linux-5.15.148
Created: 2024-02-07 9:01:10 UTC
Image Type: MIPS Linux Kernel Image (lzma compressed)
Data Size: 2050232 Bytes = 2 MB
Load Address: 80100000
Entry Point: 80100000
Verifying Checksum ... OK
Uncompressing Kernel Image ... OK

Starting kernel ...

[ 0.000000] Linux version 5.15.148 (5800X@crunchbot) (mips-openwrt-linux-musl-gcc (OpenWrt GCC 12.3.0 r24993+1-32b4498c15) 12.3.0, GNU ld (GNU Binutils) 2.40.0) #0 Wed Feb 7 09:01:10 2024
[ 0.000000] RTL838X model is 0
[ 0.000000] RTL839X model is 0
[ 0.000000] RTL93XX model is 93021001
[ 0.000000] SoC Type: RTL9302B
[ 0.000000] printk: bootconsole [early0] enabled
[ 0.000000] CPU0 revision is: 00019555 (MIPS 34Kc)
[ 0.000000] MIPS: machine is Zyxel XGS1210-12 v2 Switch
[ 0.000000] earlycon: ns16550a0 at MMIO 0x18002000 (options '115200n8')
[ 0.000000] printk: bootconsole [ns16550a0] enabled
[ 0.000000] Initrd not found or empty - disabling initrd
[ 0.000000] Using appended Device Tree.
[ 0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[ 0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[ 0.000000] Zone ranges:
[ 0.000000] Normal [mem 0x0000000000000000-0x0000000007ffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000000000000-0x0000000007ffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff]
[ 0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=132768
[ 0.000000] pcpu-alloc: [0] 0
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 32480
[ 0.000000] Kernel command line: earlycon
[ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes, linear)
[ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes, linear)
[ 0.000000] Writing ErrCtl register=000094e0
[ 0.000000] Readback ErrCtl register=000094e0
[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[ 0.000000] Memory: 121720K/131072K available (5477K kernel code, 605K rwdata, 540K rodata, 1176K init, 209K bss, 9352K reserved, 0K cma-reserved)
[ 0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[ 0.000000] NR_IRQS: 256
[ 0.000000] Failed to get CPU clock: -2
[ 0.000000] CPU frequency from device tree: 800MHz
[ 0.000000] clocksource: realtek_otto_timer: mask: 0xfffffff max_cycles: 0xfffffff, max_idle_ns: 38225208801 ns
[ 0.000001] sched_clock: 28 bits at 3125kHz, resolution 320ns, wraps every 42949672800ns
[ 0.008970] Calibrating delay loop... 531.66 BogoMIPS (lpj=2658304)
[ 0.065693] pid_max: default: 32768 minimum: 301
[ 0.071675] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
[ 0.079703] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
[ 0.095987] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[ 0.106771] futex hash table entries: 256 (order: -1, 3072 bytes, linear)
[ 0.114399] pinctrl core: initialized pinctrl subsystem
[ 0.121262] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[ 0.142145] clocksource: Switched to clocksource realtek_otto_timer
[ 0.150455] NET: Registered PF_INET protocol family
[ 0.156142] IP idents hash table entries: 2048 (order: 2, 16384 bytes, linear)
[ 0.164859] tcp_listen_portaddr_hash hash table entries: 1024 (order: 0, 4096 bytes, linear)
[ 0.174167] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
[ 0.182660] TCP established hash table entries: 1024 (order: 0, 4096 bytes, linear)
[ 0.191019] TCP bind hash table entries: 1024 (order: 0, 4096 bytes, linear)
[ 0.198739] TCP: Hash tables configured (established 1024 bind 1024)
[ 0.205860] UDP hash table entries: 256 (order: 0, 4096 bytes, linear)
[ 0.213082] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes, linear)
[ 0.221137] NET: Registered PF_UNIX/PF_LOCAL protocol family
[ 0.231489] workingset: timestamp_bits=14 max_order=15 bucket_order=1
[ 0.244408] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[ 0.250788] jffs2: version 2.2 (NAND) (SUMMARY) (ZLIB) (LZMA) (RTIME) (CMODE_PRIORITY) (c) 2001-2006 Red Hat, Inc.
[ 0.264848] pinctrl-single 1b00cc00.pinmux: 32 pins, size 4
[ 0.272572] Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
[ 0.280433] printk: console [ttyS0] disabled
[ 0.285243] 18002000.uart: ttyS0 at MMIO 0x18002000 (irq = 30, base_baud = 10937500) is a 16550A
[ 0.294908] printk: console [ttyS0] enabled
[ 0.294908] printk: console [ttyS0] enabled
[ 0.304245] printk: bootconsole [early0] disabled
[ 0.304245] printk: bootconsole [early0] disabled
[ 0.314730] printk: bootconsole [ns16550a0] disabled
[ 0.314730] printk: bootconsole [ns16550a0] disabled
[ 0.366710] brd: module loaded
[ 0.374418] spi-nor spi0.0: mx25l12805d (16384 Kbytes)
[ 0.380214] 7 fixed-partitions partitions found on MTD device spi0.0
[ 0.387395] OF: Bad cell count for /soc/spi@1200/flash@0/partitions
[ 0.394451] OF: Bad cell count for /soc/spi@1200/flash@0/partitions
[ 0.401686] Creating 7 MTD partitions on "spi0.0":
[ 0.407084] 0x000000000000-0x0000000e0000 : "u-boot"
[ 0.415555] 0x0000000e0000-0x0000000f0000 : "u-boot-env"
[ 0.422748] 0x0000000f0000-0x000000100000 : "u-boot-env2"
[ 0.431767] 0x000000100000-0x000000200000 : "jffs"
[ 0.438401] 0x000000200000-0x000000300000 : "jffs2"
[ 0.446908] 0x000000300000-0x000000fe0000 : "firmware"
[ 0.454193] 2 uimage-fw partitions found on MTD device firmware
[ 0.460805] Creating 2 MTD partitions on "firmware":
[ 0.466407] 0x000000000000-0x000000200000 : "kernel"
[ 0.475046] 0x000000200000-0x000000ce0000 : "rootfs"
[ 0.481610] mtd: setting mtd7 (rootfs) as root device
[ 0.488263] 1 squashfs-split partitions found on MTD device rootfs
[ 0.495252] 0x000000590000-0x000000ce0000 : "rootfs_data"
[ 0.503484] 0x000000fe0000-0x000001000000 : "log"
[ 0.519562] Probing RTL838X eth device pdev: 82085a00, dev: 82085a10
[ 0.546175] Found SoC ID: 9302: RTL9302B, family 9300
[ 0.551940] Using MAC 0000000000010000
[ 0.556217] set sds port 0 to 2
[ 0.559755] set sds port 24 to 6
[ 0.563377] set sds port 25 to 7
[ 0.566971] set sds port 26 to 8
[ 0.570552] set sds port 27 to 9
[ 0.574866] c45_mask: 00000000
[ 0.649093] REALTEK RTL9300 SERDES mdio-bus:1a: Detected internal RTL9300 Serdes
[ 0.663954] REALTEK RTL9300 SERDES mdio-bus:1b: Detected internal RTL9300 Serdes
[ 0.673398] i2c_dev: i2c /dev entries driver
[ 0.678303] rtl9300_i2c_probe probing I2C adapter
[ 0.683634] i2c-rtl9300 1b00036c.i2c-rtl9300: SCL speed 100000, mode is 0
[ 0.691191] rtl9300_i2c_probe scl_num 0
[ 0.695485] rtl9300_i2c_probe sda_num 0
[ 0.700269] rtl9300_i2c_mux_probe probing I2C adapter
[ 0.705984] rtl9300_i2c_mux_probe base memory bb00036c
[ 0.711709] rtl9300_i2c_mux_probe channel 9 scl_num 0
[ 0.717367] rtl9300_i2c_mux_probe channel 9 sda_num 0
[ 0.723331] i2c i2c-0: Added multiplexed i2c bus 1
[ 0.728684] rtl9300_i2c_mux_probe channel 10 scl_num 0
[ 0.734448] rtl9300_i2c_mux_probe channel 10 sda_num 1
[ 0.740401] i2c i2c-0: Added multiplexed i2c bus 2
[ 0.745802] i2c-mux-rtl9300 i2cmux: 2-port mux on 1b00036c.i2c-rtl9300 adapter
[ 0.756814] NET: Registered PF_INET6 protocol family
[ 0.777678] Segment Routing with IPv6
[ 0.781890] In-situ OAM (IOAM) with IPv6
[ 0.786488] NET: Registered PF_PACKET protocol family
[ 0.792626] 8021q: 802.1Q VLAN Support v1.8
[ 0.798481] sfp sfp-p11: Host maximum power 1.0W
[ 0.805756] sfp sfp-p12: Host maximum power 1.0W
[ 0.873248] REALTEK RTL9300 SERDES rtl838x slave mii-0:1a: Detected internal RTL9300 Serdes
[ 0.889004] REALTEK RTL9300 SERDES rtl838x slave mii-0:1b: Detected internal RTL9300 Serdes
[ 0.904282] REALTEK RTL9300 SERDES rtl838x slave mii-0:3f: Detected internal RTL9300 Serdes
[ 0.915763] rtl93xx_setup called
[ 0.919408] In rtl83xx_vlan_setup
[ 0.923139] In rtl930x_vlan_profile_setup
[ 0.927594] In rtl930x_vlan_profile_setup
[ 0.932045] UNKNOWN_MC_PMASK: 000000001fffffff
[ 0.937028] VLAN 0: L2 learn: 0; Unknown MC PMasks: L2 1fffffff, IPv4 1fffffff, IPv6: 1fffffff
[ 0.937052] Routing enabled: IPv4 UC y, IPv6 UC y, IPv4 MC y, IPv6 MC y
[ 0.954219] Bridge enabled: IPv4 MC n, IPv6 MC n,
[ 0.959648] VLAN profile 0: raw 00033000 00000000 1fffffff 1fffffff 1fffffff
[ 2.012151] rtl83xx_enable_phy_polling: f0000ff
[ 2.018078] rtl930x_pie_init
[ 2.021486] rtl930x_led_init called
[ 2.025494] rtl930x_led_init led_set configuration invalid skipping over this set
[ 2.033879] rtl930x_led_init bb00cc00: 01052659
[ 2.038920] rtl930x_led_init bb00cc04: aaaa5555
[ 2.043980] rtl930x_led_init bb00cc08: 005faaaa
[ 2.049023] rtl930x_led_init bb00cc0c: 00000000
[ 2.054080] rtl930x_led_init bb00cc10: 00000000
[ 2.059116] rtl930x_led_init bb00cc14: 00000000
[ 2.064173] rtl930x_led_init bb00cc18: 0a200a01
[ 2.069210] rtl930x_led_init bb00cc1c: 0a0b0a28
[ 2.074267] rtl930x_led_init bb00cc20: 0a820a0b
[ 2.079304] rtl930x_led_init bb00cc24: 00000000
[ 2.084360] rtl930x_led_init bb00cc28: 0a200b80
[ 2.089397] rtl930x_led_init bb00cc2c: 00000000
[ 2.094455] rtl930x_led_init bb00cc30: 00a50000
[ 2.099491] rtl930x_led_init bb00cc34: 00000000
[ 2.104548] rtl930x_led_init bb00cc38: 00a50000
[ 2.109584] rtl930x_led_init bb00cc3c: 0f0000ff
[ 2.114642] rtl930x_led_init bb00cc40: 0f0000ff
[ 2.119678] rtl930x_led_init bb00cc44: 0f0000ff
[ 2.124736] rtl930x_led_init bb00cc48: 00000000
[ 2.129771] rtl930x_led_init bb00cc4c: 00000000
[ 2.134829] rtl930x_led_init bb00cc50: 00000000
[ 2.139866] rtl930x_led_init bb00cc54: 00000000
[ 2.144926] rtl930x_led_init bb00cc58: 00000000
[ 2.149968] rtl930x_led_init bb00cc5c: 00000000
[ 2.155384] rtl83xx-switch switch@1b000000: configuring for fixed/internal link mode
[ 2.164074] rtl93xx_phylink_mac_config port 28, mode 1, phy-mode: internal, speed 10000, link 0
[ 2.174023] rtl83xx-switch switch@1b000000 lan1 (uninitialized): PHY [mdio-bus:00] driver [REALTEK RTL8218D] (irq=POLL)
[ 2.187444] rtl83xx-switch switch@1b000000 lan2 (uninitialized): PHY [mdio-bus:01] driver [REALTEK RTL8218D] (irq=POLL)
[ 2.200658] rtl83xx-switch switch@1b000000 lan3 (uninitialized): PHY [mdio-bus:02] driver [REALTEK RTL8218D] (irq=POLL)
[ 2.214079] rtl83xx-switch switch@1b000000 lan4 (uninitialized): PHY [mdio-bus:03] driver [REALTEK RTL8218D] (irq=POLL)
[ 2.227500] rtl83xx-switch switch@1b000000 lan5 (uninitialized): PHY [mdio-bus:04] driver [REALTEK RTL8218D] (irq=POLL)
[ 2.240818] rtl83xx-switch switch@1b000000 lan6 (uninitialized): PHY [mdio-bus:05] driver [REALTEK RTL8218D] (irq=POLL)
[ 2.254343] rtl83xx-switch switch@1b000000 lan7 (uninitialized): PHY [mdio-bus:06] driver [REALTEK RTL8218D] (irq=POLL)
[ 2.267661] rtl83xx-switch switch@1b000000 lan8 (uninitialized): PHY [mdio-bus:07] driver [REALTEK RTL8218D] (irq=POLL)
[ 2.281042] rtl9300_configure_rtl8226 configuring RTL8226 on port 24
[ 2.288197] rtl9300_configure_rtl8226: port 24, SerDes is 6
[ 2.300413] rtl9300_configure_rtl8226 CMU BAND is 16
[ 2.325936] rtl9300_force_sds_mode: SDS: 6, mode 0
[ 2.331270] rtl9300_force_sds_mode --------------------- serdes 6 forcing to 1f ...
[ 2.345815] rtl9300_configure_rtl8226 PATCHING SerDes 6
[ 2.423997] rtl9300_rtl8226_phy_setup, port 24 patch version ffff
[ 2.430786] rtl9300_rtl8226_phy_setup: MDI pins already swapped
[ 2.439385] rtl9300_serdes_mac_link_config: registers before 00000000 00001403
[ 2.451436] rtl9300_serdes_mac_link_config: registers after 00000000 00001403
[ 2.459401] start_1.1.1 initial value for sds 6
[ 2.521400] end_1.1.1 --
[ 2.524245] start_1.1.2 Load DFE init. value
[ 2.530987] end_1.1.2
[ 2.533532] start_1.1.3 disable LEQ training,enable DFE clock
[ 2.551917] end_1.1.3 --
[ 2.554764] start_1.1.4 offset cali setting
[ 2.561408] end_1.1.4
[ 2.563953] start_1.1.5 LEQ and DFE setting
[ 2.582616] end_1.1.5
[ 2.585149] rtl9300_force_sds_mode: SDS: 6, mode 18
[ 2.590563] rtl9300_force_sds_mode --------------------- serdes 6 forcing to 12 ...
[ 2.855688] rtl9300_force_sds_mode --------------------- serdes 6 forced to 12 DONE
[ 2.876251] rtl83xx-switch switch@1b000000 lan9 (uninitialized): PHY [mdio-bus:18] driver [REALTEK RTL8221B] (irq=POLL)
[ 2.889543] rtl9300_configure_rtl8226 configuring RTL8226 on port 25
[ 2.896698] rtl9300_configure_rtl8226: port 25, SerDes is 7
[ 2.908914] rtl9300_configure_rtl8226 CMU BAND is 16
[ 2.934450] rtl9300_force_sds_mode: SDS: 7, mode 0
[ 2.939789] rtl9300_force_sds_mode --------------------- serdes 7 forcing to 1f ...
[ 2.954325] rtl9300_configure_rtl8226 PATCHING SerDes 7
[ 3.024463] rtl9300_rtl8226_phy_setup, port 25 patch version ffff
[ 3.031248] rtl9300_rtl8226_phy_setup: MDI pins already swapped
[ 3.039850] rtl9300_serdes_mac_link_config: registers before 00000000 00001403
[ 3.051906] rtl9300_serdes_mac_link_config: registers after 00000000 00001403
[ 3.059872] start_1.1.1 initial value for sds 7
[ 3.121864] end_1.1.1 --
[ 3.124707] start_1.1.2 Load DFE init. value
[ 3.131449] end_1.1.2
[ 3.133999] start_1.1.3 disable LEQ training,enable DFE clock
[ 3.152405] end_1.1.3 --
[ 3.155224] start_1.1.4 offset cali setting
[ 3.161861] end_1.1.4
[ 3.164406] start_1.1.5 LEQ and DFE setting
[ 3.183063] end_1.1.5
[ 3.185592] rtl9300_force_sds_mode: SDS: 7, mode 18
[ 3.191008] rtl9300_force_sds_mode --------------------- serdes 7 forcing to 12 ...
[ 3.456128] rtl9300_force_sds_mode --------------------- serdes 7 forced to 12 DONE
[ 3.476701] rtl83xx-switch switch@1b000000 lan10 (uninitialized): PHY [mdio-bus:19] driver [REALTEK RTL8221B] (irq=POLL)
[ 3.492337] DSA: tree 0 setup
[ 3.495695] LINK state irq: 23
[ 3.499169] In rtl83xx_setup_qos
[ 3.502883] L3_IPUC_ROUTE_CTRL 00002000, IPMC_ROUTE 0000077e, IP6UC_ROUTE 00014400, IP6MC_ROUTE 0001db7e
[ 3.513470] L3_IPUC_ROUTE_CTRL 00002001, IPMC_ROUTE 00000501, IP6UC_ROUTE 00014581, IP6MC_ROUTE 00012881
[ 3.524050] L3_IP_ROUTE_CTRL 0000013f
[ 3.528225] rtl930x_dbgfs_init called
[ 3.535846] rtl93xx_phylink_mac_config port 28, mode 1, phy-mode: internal, speed 10000, link 1
[ 3.545615] rtl83xx-switch switch@1b000000: Link is Up - 10Gbps/Full - flow control off
[ 3.562068] rtl83xx_fib_event_work_do: FIB4 default rule failed
[ 3.568740] rtl83xx_fib_event_work_do: FIB4 default rule failed
[ 3.582252] VFS: Mounted root (squashfs filesystem) readonly on device 31:7.
[ 3.595097] Freeing unused kernel image (initmem) memory: 1176K
[ 3.601701] This architecture does not have kernel memory protection.
[ 3.608920] Run /sbin/init as init process
[ 3.613509] with arguments:
[ 3.616805] /sbin/init
[ 3.619806] with environment:
[ 3.623318] HOME=/
[ 3.625941] TERM=linux
[ 4.139464] init: Console is alive
[ 4.143879] init: - watchdog -
[ 4.517145] kmodloader: loading kernel modules from /etc/modules-boot.d/
[ 4.558297] kmodloader: done loading kernel modules from /etc/modules-boot.d/*
[ 4.576996] init: - preinit -
[ 5.543800] random: jshn: uninitialized urandom read (4 bytes read)
[ 5.667289] random: jshn: uninitialized urandom read (4 bytes read)
[ 6.283313] random: jshn: uninitialized urandom read (4 bytes read)
[ 7.095339] RESETTING 9300, CPU_PORT 28
[ 7.299981] rtl838x-eth 1b00a300.ethernet eth0: configuring for fixed/internal link mode
[ 7.308984] In rtl838x_mac_config, mode 1
[ 7.314259] rtl83xx-switch switch@1b000000 lan1: configuring for phy/xgmii link mode
[ 7.322960] rtl93xx_phylink_mac_config port 0, mode 0, phy-mode: xgmii, speed -1, link 0
[ 7.331967] rtl93xx_phylink_mac_config SDS is 2
[ 7.337255] 8021q: adding VLAN 0 to HW filter on device lan1
[ 7.343945] rtl838x-eth 1b00a300.ethernet eth0: Link is Up - 1Gbps/Full - flow control off
[ 7.355086] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
[ 7.362105] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
[ 7.369486] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
[ 7.386252] rtl83xx_fib_event_work_do: FIB4 failed
[ 7.391606] rtl83xx_fib_event_work_do: FIB4 failed
[ 7.406065] random: procd: uninitialized urandom read (4 bytes read)
[ 7.415684] rtl83xx_fib_event_work_do: FIB4 failed
Press the [f] key and hit [enter] to enter failsafe mode
Press the [1], [2], [3] or [4] key and hit [enter] to select the debug level
[ 8.652200] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
[ 9.666298] jffs2: notice: (632) jffs2_build_xattr_subsystem: complete building xattr subsystem, 11 of xdatum (0 unchecked, 6 orphan) and 12 of xref (6 dead, 0 orphan) found.
[ 9.685688] mount_root: switching to jffs2 overlay
[ 9.694809] overlayfs: upper fs does not support tmpfile.
[ 9.708933] urandom-seed: Seeding with /etc/urandom.seed
[ 9.816651] rtl83xx_fib4_del: no such gateway: 0.0.0.0
[ 9.832433] rtl83xx_fib4_del: no such gateway: 0.0.0.0
[ 9.838196] rtl83xx_fib4_del: no such gateway: 0.0.0.0
[ 9.860952] procd: - early -
[ 9.864615] procd: - watchdog -
[ 10.559602] procd: - watchdog -
[ 10.563941] procd: - ubus -
[ 10.627179] random: ubusd: uninitialized urandom read (4 bytes read)
[ 10.636341] random: ubusd: uninitialized urandom read (4 bytes read)
[ 10.643904] random: ubusd: uninitialized urandom read (4 bytes read)
[ 10.656116] procd: - init -
Please press Enter to activate this console.

Any pointers are appreciated.