RTL838x# mw.l 0xbb000144 1
RTL838x# md.l 0xbb000144
bb000144: 00000001 00000000 1fffffff 1fffffff ................
This is only valid for the current boot. The reset still happens.
Testers needed for:
Sorry for the inconvenience. This workaround was already discussed in https://github.com/openwrt/openwrt/pull/10573#discussion_r976950848
Did not have time until now to post a fix. @musashino 's fix is the right way to go.
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@lucize @piaddic7ed I think I have something that excitingly works now 
~The led colors still seem to be off for 2.5G (led_set1 = <0x0a0b 0x0a28 0x0a82 0x0a0b>; /* LED set 1: 100Mbit, 1000Mbit, 2.5Gbit */ is what birger put in the dt; its somewhat white/pinkish, maybe that's what his daughter preferred? Should be cyan (B of RGB + limegreen), @svanheule might be able to help?~ edit: Figured it out, me being stupid. Perfectly pretty in CYAN
I have all 12 ports working, well i can ping from the switch 
and I have cpufreq, cpuIDLE and MT_SMP working. I've pushed to my realtek-next branch; and I've uploaded the binaries here, just to see if its failing for you due to complication (.config issues) or something I keep overseeing. https://drive.google.com/drive/folders/1yf9mB0fH931P0UYmyYuQzyukJZ428KWV?usp=sharing I've only booted via initramfs so far; but will flash this one actually
one thing i'll have to figure out, why my 1m DAC cable is working, and my 3M is not; but birger also said that DAC cable where a hit/miss for him.
Ok flashing it to inramfs, looks ok so far, odd thing, is that the LEDs are not working for the SFP ports, but they seem to be detected just fine; so might still be some 'initialization' stuff that's not quite right; of course I don't run rtk network on when booting from flash ... thus; to load from flash; setenv bootcmd rtk network on; boota
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I wanted to say that the device boots, no improvements, meaning that no 2.5gb link for me (this image is the same, used your bin), also as I said in the PR comments the spamming of
[ 68.203135] rtl9300_read_status: Port 27, SerDes is 9
[ 68.208880] rtl9300_read_status got SDS mode 1f
[ 69.236282] rtl9300_read_status: Port 27, SerDes is 9
[ 69.241921] rtl9300_read_status got SDS mode 1f
it's just hidden in birger image, after I reconnect a SFP module it's not spamming anymore
@lucize but you have a XGS1250-12 right? That hardware is too different from mine to validate any of this. I have an XGS1010-12/XGS1210-12 and so I have different PHY's for 2.5. (you have 3 aquantia PHY's, I have 2 RTL8266 PHY's. The SFP port should be the same though iirc.
As for the spam, I also get it, I can 'silence' it but not sure if that's not hiding a bigger issue?
Any of the RTL930x users managed to use the switch as an actual 'switch'? So far, all testing I have done was via eth0 -> network on the various ports; not port <-> port config (on any firmware).
Right, so; my problem was that I was testing via a USB2.0 100Mbit USB dongle; which doesn't seem to work; The switch prints that it sees 100Mbit; but the led stays green (first hint, though led could be wrong) and doesn't work afterwards; so looks like 100Mbit currently is broken (works fine in u-boot and vendor firmware)
I have xgs1010-12 with 10Mbit DAC connected to Mellanox X-3 - is that configuration expected to work?
So birger initially said, DAC's are tricky, some work, some don't. I have 2 10Gbit DAC cables, 1m and 3m, only the 1m one works. Since I need the 3m one to work, I'll obviously have to look into that, as that matters to me personally
As for 10Mbit (typo?) and 100Mbit, I have not seen working on any ports, only 1000Mbit on 1bit ports, , 1000Mbit and 2500Mbit on the multi-g ports and 10000Mbit on the SFP ports. 100Mbit on any of the RJ45 ports doesn't work; I don't have 10Mbit dongles to try that, but setting advertisemode to 10mbit also doesn't work atm.
Sorry, I made a typo: I have 10Gbit DAC, it's 1.5M long (cheapest one I could find for $6)- I'll try it over the weekend.
Curious! I wish I could get one for 1.5m and mine where far more then that sadly 
€19 and €29 iirc. Lets hope they didn't sham you
For the record, would you mind running i2cdump 1 0x50 -y with one end in lan11? (or 2 in lan12) and paste that here in tripple backticks? I don't think it'll contain anything very interesting, but good to have and compare the data.
DAC works fine for me now between Zyxel and Mellanox on Debian/Proxmox.
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So I figured out the DAC situation, in that the SerDeS needs to be properly calibrated. For our 'fixed hardware' (serdes MII links between the chips) these calibration tables are static, which is logical, the hardware isn't changing. The question of course 'where to store them' big datablobs in the kernel, used based on compatible? In the devicetree?, as a 'firmware blob'? Many options for the future.
For DAC however (and probably also for optical SFP, but maybe less important), the SerDes needs to be calibrated depending on the length and signal quality. This a little complex, and alot of (black) magic (values) in the [[https://gitlab.com/olliver/openwrt/realtek_sdk/-/blob/openwrt-dev/loader/u-boot-2011.12/board/Realtek/switch/sdk/src/dal/longan/dal_longan_sds.c|SDK]]. But at least we have the data so this can be implemented, but it relies on a lot of 'trial and error', just copy/pasting the gist of the code will help, but we'll lack understanding for sure. Anyway, some homework/something to learn.
That doesn't look too bad, does it? They have different settings for fiber and DAC, but not for the different lengths.
Nah, doens't look to bad at all, they do have defines for the various lengths, but, they are all the same. I think some 'training' happens at some point. Right now, I'm cleaning some stuff up; to prepare for inclusion, but ran into the fact, that some values (pre_amp, main_amp) for 2.5G are in our code, seemingly working, but can't be found in the SDK. So where did they come from? ... who knows
The frustrating bit is, if you could measure it, you can tune it and validate it; but right now it's more of 'this works, this doesn't, this ... seems to work, but we'll learn later, that it actually doesn't And while I do have a 300Mhz scope, it's not even close to the 10G needed on that bus
Did we ever get the SDK for the 'cascaded' 9301 switch? Is it the same as the 1210-12/1250-12? I'm looking at the SDS configuration block, and notice not all serdes'es get configured (on the cascaded master only 2) so are the defaults fine for the other internal links? I would guess so; but then what about the other serdeses?
E.g. https://gitlab.com/olliver/openwrt/realtek_sdk/-/blob/openwrt-dev/loader/u-boot-2011.12/board/Realtek/switch/sdk/src/dal/longan/dal_longan_sds.c#L492 seems logical, 8 serdesen for the 8 10G SFP+ cages. What are ser0 and 1 though? unused? For internal purposes? For the CPU-MAC? but that's way to much capacity (though logically maybe easier? unless its a gbit serdes (do those exist?) Or is it 2 cascaded serdesen for 'external CPU mode' as RTL9301 calls it.
hello, i have D-Link DGS-1210-10 Rev. F1, and i've seen dgs-1210 toh and svan's wiki, while the board has already been documented, and status of openwrt already on "git", i have not seen the build for this typical board.
Should i build it by myself? or i simply can use DGS-1210-10P / MP (realtek based ofc)?
the only git comment that i've seen about DGS-1210-10 are from Oct 2021
maybe @svanheule or @RaylynnKnight can help me about this particular board?
Has anyone tried the ZyXEL GS1915 series of switches?
Did you take a look at its internals? No guarantee they're a supported platform.
switch is working fine 1/10gb, no sfp and no multigig, I'm curious how qnap router that has the same aquantia phy is working fine, also my DAC is 5m, I think
Yeah, DAC is something I'm working on; and it's a bit of a mess; we need to calibrate the DAC's at runtime. Once done, it that should work ...
As for the aquantia PHY's they are working for you on openwrt git master (they should I reccon).