Things like this...
I downloaded the GPL source myself, and briefly looked into it.
Their own solution for the Winbond support:
src/linux/patches/linux-3.10.70_080_2ndNandSource.patch
--- linux-3.10.70_WNC/drivers/mtd/nand/mvebu_nfc/hal/mvNfc.c 2016-01-11 17:31:05.000000000 +0800
+++ 20160111/drivers/mtd/nand/mvebu_nfc/hal/mvNfc.c 2017-05-26 13:59:50.000000000 +0800
@@ -320,6 +320,52 @@
.bb_page = 0, /* Manufacturer Bad block marking page in block */
.flags = NFC_CLOCK_UPSCALE_200M
},
+ { /* WNC_Gary Winbond 2Gb */
+ .tADL = 70, /* tADL, Address to write data delay */
+ .tCH = 5, /* tCH, Enable signal hold time */
+ .tCS = 15, /* tCS, Enable signal setup time */
+ .tWC = 25, /* tWC, ND_nWE cycle duration */
+ .tWH = 10, /* tWH, ND_nWE high duration */
+ .tWP = 12, /* tWP, ND_nWE pulse time */
+ .tRC = 25, /* tWC, ND_nRE cycle duration */
+ .tRH = 15, /* tRH, ND_nRE high duration */
+ .tRP = 12, /* tRP, ND_nRE pulse width */
+ .tR = 25000, /* tR = data transfer from cell to register, maximum 60,000ns */
+ .tWHR = 60, /* tWHR, ND_nWE high to ND_nRE low delay for status read */
+ .tAR = 10, /* tAR, ND_ALE low to ND_nRE low delay */
+ .tRHW = 100, /* tRHW, ND_nRE high to ND_nWE low delay 32 clocks */
+ .pgPrBlk = 64, /* Pages per block - detected */
+ .pgSz = 2048, /* Page size */
+ .oobSz = 64 , /* Spare size */
+ .blkNum = 2048, /* Number of blocks/sectors in the flash */
+ .id =0xDAEF, /* Device ID 0xDevice,Vendor */
+ .model = "Winbond 2Gb 8bit",
+ .bb_page = 0, /* Manufacturer Bad block marking page in block */
+ .flags = NFC_CLOCK_UPSCALE_200M
+ },
+ { /* WNC_Gary MXIC 2Gb 20150518*/
+ .tADL = 70, /* tADL, Address to write data delay */
+ .tCH = 5, /* tCH, Enable signal hold time */
+ .tCS = 15, /* tCS, Enable signal setup time */
+ .tWC = 20, /* tWC, ND_nWE cycle duration */
+ .tWH = 7, /* tWH, ND_nWE high duration */
+ .tWP = 10, /* tWP, ND_nWE pulse time */
+ .tRC = 20, /* tWC, ND_nRE cycle duration */
+ .tRH = 60, /* tRH, ND_nRE high duration */
+ .tRP = 10, /* tRP, ND_nRE pulse width */
+ .tR = 25000, /* tR = data transfer from cell to register, maximum 60,000ns */
+ .tWHR = 60, /* tWHR, ND_nWE high to ND_nRE low delay for status read */
+ .tAR = 10, /* tAR, ND_ALE low to ND_nRE low delay */
+ .tRHW = 60, /* tRHW, ND_nRE high to ND_nWE low delay 32 clocks */
+ .pgPrBlk = 64, /* Pages per block - detected */
+ .pgSz = 2048, /* Page size */
+ .oobSz = 64 , /* Spare size */
+ .blkNum = 2048, /* Number of blocks/sectors in the flash */
+ .id =0xDAC2, /* Device ID 0xDevice,Vendor */
+ .model = "MXIC 2Gb 8bit",
+ .bb_page = 0, /* Manufacturer Bad block marking page in block */
+ .flags = NFC_CLOCK_UPSCALE_200M
+ },
{ /* Micron 4Gb */
.tADL = 70, /* tADL, Address to write data delay */
.tCH = 5, /* tCH, Enable signal hold time */
(I didn't compare yet all all sources to the previous version, but just looked at the core patch directory src/linux/patches/ where most of the interesting stuff is.)
The solution proposed by Kaloz seems much shorter, as it onyl sets a few key parameters. This seems like a full chip database entry.