Sitecom WLR-4100 (MT7620A + QCA 8337) support

Well. It's clear that no rgmii interface synchronization in both directions.
Then rgmii is syncronized:

  • any increasing of P5 tx* statistics must increase M0 rx* statistics too (this means that syncho ok in P5 -> M0 directrion);
  • any increasing of M0 tx* statistics must increase P5 rx* statistics too (this means that syncho ok in M0 -> P5 directrion);
    Let's quick change synchro from switch0 side. Pls change value qca,ar8327-initvals in dts to:
			qca,ar8327-initvals = <
				0x04 0x87600000 /* PORT0 PAD MODE CTRL */
				0x0c 0x00000000 /* PORT6 PAD MODE CTRL */
				0x7c 0x0000007e /* PORT0_STATUS */
				0x94 0x00000000 /* PORT6_STATUS */
			>;

And show statistics again.

Changing from 0x87300000 to 0x87600000 did not bring so much luck:

root@OpenWrt:/# swconfig dev switch1 port 4 show
Port 4:
	mib: Port 4 MIB counters
TxGPC      : 0
TxBOC      : 0
TxGOC      : 0
TxEPC      : 0
RxGPC      : 0
RxBOC      : 0
RxGOC      : 0
RxEPC1     : 0
RxEPC2     : 0

	pvid: 0
	link: port:4 link:down
root@OpenWrt:/# 
root@OpenWrt:/# swconfig dev switch1 port 5 show
Port 5:
	mib: Port 5 MIB counters
TxGPC      : 323
TxBOC      : 0
TxGOC      : 100911
TxEPC      : 0
RxGPC      : 0
RxBOC      : 0
RxGOC      : 0
RxEPC1     : 0
RxEPC2     : 0

	pvid: 0
	link: port:5 link:up speed:1000baseT full-duplex 
root@OpenWrt:/# 
root@OpenWrt:/# swconfig dev switch0 port 0 show
Port 0:
	mib: MIB counters
RxBroad     : 0
RxPause     : 0
RxMulti     : 0
RxFcsErr    : 0
RxAlignErr  : 0
RxRunt      : 0
RxFragment  : 0
Rx64Byte    : 0
Rx128Byte   : 0
Rx256Byte   : 0
Rx512Byte   : 0
Rx1024Byte  : 0
Rx1518Byte  : 0
RxMaxByte   : 0
RxTooLong   : 0
RxGoodByte  : 0
RxBadByte   : 0
RxOverFlow  : 0
Filtered    : 0
TxBroad     : 1224
TxPause     : 0
TxMulti     : 1823
TxUnderRun  : 0
Tx64Byte    : 67
Tx128Byte   : 2733
Tx256Byte   : 177
Tx512Byte   : 0
Tx1024Byte  : 42
Tx1518Byte  : 28
TxMaxByte   : 0
TxOverSize  : 0
TxByte      : 325360 (317.7 KiB)
TxCollision : 0
TxAbortCol  : 0
TxMultiCol  : 0
TxSingleCol : 0
TxExcDefer  : 0
TxDefer     : 0
TxLateCol   : 0

	enable_eee: ???
	igmp_snooping: 0
	vlan_prio: 0
	pvid: 0
	link: port:0 link:up speed:1000baseT full-duplex txflow rxflow 
root@OpenWrt:/# 
root@OpenWrt:/# swconfig dev switch0 port 2 show
Port 2:
	mib: MIB counters
RxBroad     : 136
RxPause     : 0
RxMulti     : 619
RxFcsErr    : 0
RxAlignErr  : 0
RxRunt      : 0
RxFragment  : 0
Rx64Byte    : 53
Rx128Byte   : 620
Rx256Byte   : 60
Rx512Byte   : 0
Rx1024Byte  : 14
Rx1518Byte  : 8
RxMaxByte   : 0
RxTooLong   : 0
RxGoodByte  : 86697 (84.6 KiB)
RxBadByte   : 0
RxOverFlow  : 0
Filtered    : 0
TxBroad     : 0
TxPause     : 0
TxMulti     : 0
TxUnderRun  : 0
Tx64Byte    : 0
Tx128Byte   : 0
Tx256Byte   : 0
Tx512Byte   : 0
Tx1024Byte  : 0
Tx1518Byte  : 0
TxMaxByte   : 0
TxOverSize  : 0
TxByte      : 0
TxCollision : 0
TxAbortCol  : 0
TxMultiCol  : 0
TxSingleCol : 0
TxExcDefer  : 0
TxDefer     : 0
TxLateCol   : 0

	enable_eee: 0
	igmp_snooping: 0
	vlan_prio: 0
	pvid: 1
	link: port:2 link:up speed:100baseT full-duplex auto
root@OpenWrt:/# 

I am confident about P5 (Port5<->GigaSW). Instead I am not about M0 and/or bit 31 (MAC0 MAC6 exchange) of AR8337.
RGMII_0 on the right side of AR8337 looks connected to MT7620A:


The RGMII_1 on the upper part looks unconnected.

Yes, I agree that in this case there is no need MAC exchange. Check 0x07600000 value. If fail than try without tx/rx delay 0x05600000/0x06600000 or any delay 0x04000000

bingo!!!
0x07600000

root@OpenWrt:/# ping 192.168.1.8 -c 8 -w 10
PING 192.168.1.8 (192.168.1.8): 56 data bytes
64 bytes from 192.168.1.8: seq=0 ttl=128 time=2.600 ms
64 bytes from 192.168.1.8: seq=1 ttl=128 time=3.020 ms
64 bytes from 192.168.1.8: seq=2 ttl=128 time=3.080 ms
64 bytes from 192.168.1.8: seq=3 ttl=128 time=2.980 ms
64 bytes from 192.168.1.8: seq=4 ttl=128 time=3.000 ms
64 bytes from 192.168.1.8: seq=5 ttl=128 time=2.940 ms
64 bytes from 192.168.1.8: seq=6 ttl=128 time=3.000 ms
64 bytes from 192.168.1.8: seq=7 ttl=128 time=3.020 ms

--- 192.168.1.8 ping statistics ---
8 packets transmitted, 8 packets received, 0% packet loss
round-trip min/avg/max = 2.600/2.955/3.080 ms
root@OpenWrt:/# 

0x05600000

PING 192.168.1.8 (192.168.1.8): 56 data bytes
64 bytes from 192.168.1.8: seq=0 ttl=128 time=2.700 ms
64 bytes from 192.168.1.8: seq=1 ttl=128 time=2.620 ms
64 bytes from 192.168.1.8: seq=2 ttl=128 time=3.060 ms
64 bytes from 192.168.1.8: seq=3 ttl=128 time=2.900 ms

0x06600000

PING 192.168.1.8 (192.168.1.8): 56 data bytes
64 bytes from 192.168.1.8: seq=0 ttl=128 time=2.720 ms
64 bytes from 192.168.1.8: seq=1 ttl=128 time=2.900 ms
64 bytes from 192.168.1.8: seq=2 ttl=128 time=2.440 ms
64 bytes from 192.168.1.8: seq=3 ttl=128 time=3.100 ms

0x04000000

PING 192.168.1.8 (192.168.1.8): 56 data bytes
64 bytes from 192.168.1.8: seq=0 ttl=128 time=2.800 ms
64 bytes from 192.168.1.8: seq=1 ttl=128 time=2.880 ms
64 bytes from 192.168.1.8: seq=2 ttl=128 time=2.420 ms
64 bytes from 192.168.1.8: seq=3 ttl=128 time=2.960 ms

Not sure we need some fine tuning in the clock delay.

1 Like

Excellent!
Good luck!

Can we embed the above commands in the *.dts?

I don't think so. But you can add option ar8xxx_mib_poll_interval 100 and option ar8xxx_mib_type 1 into switch config section (where option reset 1 and option enable_vlan 1) of /etc/config/network file.

I flashed the image. Router boots like it did when I uploaded to RAM, but the commands for configuring ar8337 switch do not have effect:

swconfig dev switch0 set reset 1
swconfig dev switch0 set enable_vlan 1
swconfig dev switch0 vlan 1 set ports '0t 1 2 3 4'
swconfig dev switch0 vlan 2 set ports '0t 5'
swconfig dev switch0 set apply 1

What do you mean

?

Before yesterday, I was testing the OpenWRT snapshot by uploading it to RAM using *initramfs-kernel.bin without touching the flash.
It worked fine with any setting of the clocks of the switch0 <-> switch1 interface. I left no clock delay in both RX and TX clocks.
Yesterday I did the big step by burning *squashfs-sysupgrade.bin on flash.
I noticed the switches interface did not work like it did with equivalent initramfs-kernel.bin.
Finally I restored the clock delay on both switch0 directions and I found, after several attempts, the magic numbers: TXclk=0, RXclk=2.
I discover that the QCA8337 RGMII RX clock is actually a single output used for all ports: 0, 5 and 6. The delay of this output clock is enabled in the Port5 pad mode Ctrl register.

/dts-v1/;

#include "mt7620a.dtsi"

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	compatible = "sitecom,wlr-4100", "ralink,mt7620a-soc";
	model = "Sitecom WLR-4100 v1 002 sw21";

	aliases {
		led-boot = &led_status;
		led-failsafe = &led_status;
		led-running = &led_status;
		led-upgrade = &led_status;
	};

	chosen {
		bootargs = "console=ttyS0,115200";
	};

	keys {
		compatible = "gpio-keys-polled";
		poll-interval = <20>;
							//SENAO_GPIO_BUTTON_WPS	2
		wps {
			label = "wps";
			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_WPS_BUTTON>;
		};
							//SENAO_GPIO_HW_RESET		17
	/*	reset {
			label = "reset";
			gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RESTART>;
		};
	*/
	};

	leds {	
		compatible = "gpio-leds";
							//SENAO_GPIO_LED_POWER		9
		led_status: status {				
			label = "wlr-4100:green:status";
			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
		};
							//SENAO_GPIO_LED_24G		72
		wifi2g {
			label = "wlr-4100:green:wifi2g";
			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
		};
							//SENAO_GPIO_LED_WPS		39
	/*	led_wps: wps {
			label = "wlr-4100:blue:wps";
			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
		};
	*/	
		
	};
	
								//SENAO_GPIO_POWER_USB		38
								//SENAO_GPIO_SWITCH_RESET	45
	/*
	gpio_export {
		compatible = "gpio-export";
		#size-cells = <0>;

		usb-power {
			gpio-export,name = "usb-power";
			gpio-export,output = <1>;
			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
		};
	};
	*/

};

&gpio0 {
	status = "okay";
};

/*
&gpio1 {
	status = "okay";
};

&gpio2 {
	status = "okay";
};
*/

&gpio3 {
	status = "okay";
};

&spi0 {
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <10000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "uboot";
				reg = <0x0 0x30000>;
				read-only;
			};

			config: partition@30000 {
				label = "config";
				reg = <0x30000 0x10000>;
				read-only;
			};

			factory: partition@40000 {
				label = "factory";
				reg = <0x40000 0x10000>;
				read-only;
			};

			partition@50000 {
				compatible = "denx,uimage";
				label = "firmware";
				reg = <0x50000 0x790000>;
			};

			partition@7e0000 {
				label = "backup";
				reg = <0x7e0000 0x10000>;
				read-only;
			};

			partition@7f0000 {
				label = "storage";
				reg = <0x7f0000 0x10000>;
				read-only;
			};
		};
	};
};

&ethernet {
	status = "okay";
	mtd-mac-address = <&factory 0x4>;
	//	mediatek,portmap = "wllll";
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;

	port@5 {
		status = "okay";
		phy-mode = "rgmii";
		mediatek,fixed-link = <1000 1 1 1>;
		phy-handle = <&phy0>;

	};

	mdio-bus {
		status = "okay";
		mediatek,mdio-mode = <1>;

		phy0: ethernet-phy@0 {
			reg = <0>;
			phy-mode = "rgmii";
			qca,ar8327-initvals = <
				0x04 0x06200000 /* PORT0 PAD MODE CTRL */
				0x08 0x01000000 /* PORT5 PAD MODE CTRL  RX delay EN all ports 0, 5, 6 */
				0x7c 0x0000007e /* PORT0_STATUS */
			>;
		};

		phy1: ethernet-phy@1 {
			reg = <1>;
			phy-mode = "rgmii";
		};

		phy2: ethernet-phy@2 {
			reg = <2>;
			phy-mode = "rgmii";
		};

		phy3: ethernet-phy@3 {
			reg = <3>;
			phy-mode = "rgmii";
		};

		phy4: ethernet-phy@4 {
			reg = <4>;
			phy-mode = "rgmii";
		};
	};
};

/*
&gsw {
     mediatek,port4="gmac";
};
*/

&ehci {
	status = "okay";
};

&ohci {
	status = "okay";
};

&wmac {
	status = "okay";
	ralink,mtd-eeprom = <&factory 0>;
};

/*
&pcie {
	status = "okay";
};

&pcie0 {
	wifi@0,0 {
		reg = <0x0000 0 0 0 0>;
		mediatek,mtd-eeprom = <&factory 0x8000>;
		mediatek,2ghz = <0>;
	};
};
*/

&pinctrl {
	state_default: pinctrl0 {
		gpio {
			//ralink,group = "mdio", "rgmii1", "uartf", "i2c", "wled";
			ralink,group = "uartf", "i2c", "wled";
			ralink,function = "gpio";
		};
	};
};

Now it works but I have to keep the RS232 connected because I have to issue the commands:

swconfig dev switch0 set reset 1
swconfig dev switch0 set enable_vlan 1
swconfig dev switch0 vlan 1 set ports '0t 1 2 3 4'
swconfig dev switch0 vlan 2 set ports '0t 5'
swconfig dev switch0 set ar8xxx_mib_poll_interval 100
swconfig dev switch0 set ar8xxx_mib_type 1
swconfig dev switch0 set apply 1

For allowing the device access, after the burning on the flash.
How can I embed the VLAN setting in squashfs-sysupgrade.bin file?
This will allow me to access from the Ethrenet and to disconnect RS232.

Have a nice week-end

To create default switch config you can add something like:

	sitecom,wlr-4100)
		ucidef_add_switch "switch0" \
			"1:lan" "2:lan" "3:lan" "4:lan" "5:wan" "0t@eth0"
		ucidef_add_switch_attr "switch0" ar8xxx_mib_poll_interval 100
		ucidef_add_switch_attr "switch0" ar8xxx_mib_type 1
		;;

in file target/linux/ramips/base-files/etc/board.d/02_network function ramips_setup_interfaces() before building firmware image. In this case default switch config (in file /etc/config/network) will be created at first start of firmware after flashing.

1 Like

2 LAN ports work out of 4, like before.

I noticed:

  1. The majority of the boards use 6t@eth0
  2. The QCA8337 port 6 is still active despite it is unconnected: speed:10baseT
  3. It was enabled (active) despite 0x0C 0x00000000 /* PORT6 PAD MODE CTRL */
  4. It was enabled despite 0x94 0x00000000 /* PORT6 STATUS */

If you can't beat them, join them. Let's try to kill port0 since I am not able to beat port6

qca,ar8327-initvals = <
    0x04 0x80000000 /* PORT0 PAD MODE CTRL MAC 0-6 Exchange */
    0x08 0x01000000 /* PORT5 PAD MODE CTRL  RX delay EN all ports 0, 5, 6 */
    0x0c 0x06200000 /* PORT6 PAD MODE CTRL */
    0x94 0x0000007e /* PORT6_STATUS */

I will try this configuration this evening.

I suppose different behavior I experienced before between:

  1. SDRAM upload with *initramfs
  2. Flash boot after burning squashfs

was due to the PORT5 PAD MODE CTRL register: in case 1 it was written by boot loader in order to allow TFTP data transfer. In case 2, it has been left unwritten. it kept the HW reset default value.

Slowly and slowly I may have a fully working snapshot.

No luck, the ports 3 and 4 (labelled 1 and 2 on the board) are still down and now port 0 looks hard to die like it was port6.
In the meantime on the web I found:

which includes a couple of sections which are not present in OpenWRT:

	if (chip_is_ar8337(priv)) {
		/*
		 * Workaround: RGMII RX delay setting needs to be
		 * always specified for AR8337 to avoid port 5
		 * RX hang on high traffic / flood conditions
		 */
		t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
	}

It is about port 5 pad register we already discover, plus another 8337 specific section:

	if (chip_is_ar8337(priv)) {
		/* Update HOL registers with values suggested by QCA switch team */
		for (i = 0; i < AR8327_NUM_PORTS; i++) {
			if (i == AR8216_PORT_CPU || i == 5 || i == 6) {
				t = 0x3 << AR8327_PORT_HOL_CTRL0_EG_PRI0_BUF_S;
				t |= 0x4 << AR8327_PORT_HOL_CTRL0_EG_PRI1_BUF_S;
				t |= 0x4 << AR8327_PORT_HOL_CTRL0_EG_PRI2_BUF_S;
				t |= 0x4 << AR8327_PORT_HOL_CTRL0_EG_PRI3_BUF_S;
				t |= 0x6 << AR8327_PORT_HOL_CTRL0_EG_PRI4_BUF_S;
				t |= 0x8 << AR8327_PORT_HOL_CTRL0_EG_PRI5_BUF_S;
				t |= 0x1e << AR8327_PORT_HOL_CTRL0_EG_PORT_BUF_S;
			} else {
				t = 0x3 << AR8327_PORT_HOL_CTRL0_EG_PRI0_BUF_S;
				t |= 0x4 << AR8327_PORT_HOL_CTRL0_EG_PRI1_BUF_S;
				t |= 0x6 << AR8327_PORT_HOL_CTRL0_EG_PRI2_BUF_S;
				t |= 0x8 << AR8327_PORT_HOL_CTRL0_EG_PRI3_BUF_S;
				t |= 0x19 << AR8327_PORT_HOL_CTRL0_EG_PORT_BUF_S;
			}
			ar8xxx_write(priv, AR8327_REG_PORT_HOL_CTRL0(i), t);

			t = 0x6 << AR8327_PORT_HOL_CTRL1_ING_BUF_S;
			t |= AR8327_PORT_HOL_CTRL1_EG_PRI_BUF_EN;
			t |= AR8327_PORT_HOL_CTRL1_EG_PORT_BUF_EN;
			t |= AR8327_PORT_HOL_CTRL1_WRED_EN;
			ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(i),
				   AR8327_PORT_HOL_CTRL1_ING_BUF |
				   AR8327_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
				   AR8327_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
				   AR8327_PORT_HOL_CTRL1_WRED_EN,
				   t);
		}
	}

which tunes the internal FIFO with magic numbers:

    0x970 0x1E864443 /* PORT0_HOL_CTRL0 */
    0x974 0x000001C6 /* PORT0_HOL_CTRL1 */
    0x978 0x19008643 /* PORT1_HOL_CTRL0 */
    0x97C 0x000001C6 /* PORT1_HOL_CTRL1 */
    0x980 0x19008643 /* PORT2_HOL_CTRL0 */
    0x984 0x000001C6 /* PORT2_HOL_CTRL1 */
    0x988 0x19008643 /* PORT3_HOL_CTRL0 */
    0x98C 0x000001C6 /* PORT3_HOL_CTRL1 */
    0x990 0x19008643 /* PORT4_HOL_CTRL0 */
    0x994 0x000001C6 /* PORT4_HOL_CTRL1 */
    0x998 0x1E864443 /* PORT5_HOL_CTRL0 */
    0x99C 0x000001C6 /* PORT5_HOL_CTRL1 */
    0x9A0 0x1E864443 /* PORT6_HOL_CTRL0 */
    0x9A4 0x000001C6 /* PORT6_HOL_CTRL1 */

I do not expect it will fix port 3 and 4 issue.
On top of that I noticed the following kernel error:

[    0.489589] switch0: Atheros AR8337 rev. 2 switch registered on mdio-bus
[    0.723649] ar8327: qca,phy-rgmii-en is not specified
[    0.730275] ar8327: qca,phy-rgmii-en is not specified

WiFi works.
I tried to leave the WiFi LED driven by the HW since is connected to GPIO 72 WLAN_LED_N but it does not reflect the WiFi stutus.
Therefore I decleared in dts file, but it remains off. I can switch on manually:

echo "default-on" > /sys/class/leds/wlr-4100v1002:blue:wifi2g/trigger

The same for wps:

echo "default-on" > /sys/class/leds/wlr-4100v1002:white:wps/trigger

Even the wps button is configured on the right pin but it does not has effect.

I understood MDIO bus controls both internal (MT7620) and external (AR8337) PHY. The MT7620 software may corrupt the AR8337 configuration in the attempt to configure the its own internal (unused) Phy connected to the same MDIO bus.
Therefore I tried to implement the software management of MDIO in order to prevent such hypothetical corruption.
I try this *.dts inspired from another SoC but it does not compile:

dts virtual mdio
/dts-v1/;

#include "mt7620a.dtsi"

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	compatible = "sitecom,wlr-4100v1002", "ralink,mt7620a-soc";
	model = "Sitecom sw39 WLR-4100 v1 002";

	aliases {
		led-boot = &led_power;
		led-failsafe = &led_power;
		led-running = &led_power;
		led-upgrade = &led_power;
	};

	chosen {
		bootargs = "console=ttyS0,115200";
	};

	keys {
		compatible = "gpio-keys-polled";
		poll-interval = <20>;
							//SENAO_GPIO_BUTTON_WPS	2
		wps {
			label = "wps";
			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_WPS_BUTTON>;
		};
							//SENAO_GPIO_HW_RESET		17			watchdog reset
							//SENAO_GPIO_SWITCH_RESET	45		NAND	ND_CS_N
		reset {			
			label = "reset";
			gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RESTART>;
		};
	
	};

	leds {	
		compatible = "gpio-leds";
							//SENAO_GPIO_LED_POWER		9   UARTF  	CTS_N
		led_power: power {				
			label = "wlr-4100v1002:amber:power";
			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
		};
							//SENAO_GPIO_LED_24G		72	WLAN_LED_N  software driving
		wifi2g {
			label = "wlr-4100v1002:blue:wifi2g";					
			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
		};
							//SENAO_GPIO_LED_WPS		39		SPI 		SPI_WP
		led_wps: wps {
			label = "wlr-4100v1002:white:wps";
			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
		};		
	};

								//SENAO_GPIO_POWER_USB		38		SPI 		SPI_HOLD
	gpio_export {			
		compatible = "gpio-export";
		#size-cells = <0>;

		usb-power {
			gpio-export,name = "usb-power";
			gpio-export,output = <1>;
			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
		};
	};
	
	
	mdio0: mdio {
		compatible = "virtual,mdio-gpio";
		#address-cells = <1>;
		#size-cells = <0>;
		gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>,	//MDC
			<&gpio1 0 GPIO_ACTIVE_HIGH>;				//MDIO

		phy0: ethernet-phy@0 {
			reg = <0>;
			phy-mode = "rgmii";
			qca,ar8327-initvals = <
				0x04 0x06200000 /* PORT0 PAD MODE CTRL */
				0x08 0x01000000 /* PORT5 PAD MODE CTRL  RX delay EN all ports 0, 5, 6 */
				0x7C 0x0000004e /* PORT0_STATUS */
		};
	};

	

};

&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&gpio2 {
	status = "okay";
};

&gpio3 {
	status = "okay";
};

&spi0 {
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <10000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "uboot";
				reg = <0x0 0x30000>;
				read-only;
			};

			config: partition@30000 {
				label = "config";
				reg = <0x30000 0x10000>;
				read-only;
			};

			factory: partition@40000 {
				label = "factory";
				reg = <0x40000 0x10000>;
				read-only;
			};

			partition@50000 {
				compatible = "denx,uimage";
				label = "firmware";
				reg = <0x50000 0x790000>;
			};

			partition@7e0000 {
				label = "backup";
				reg = <0x7e0000 0x10000>;
				read-only;
			};

			partition@7f0000 {
				label = "storage";
				reg = <0x7f0000 0x10000>;
				read-only;
			};
		};
	};
};

&ethernet {
	status = "okay";
	mtd-mac-address = <&factory 0x4>;
	// mediatek,portmap = "wllll";   //it is used for MT7620 internal Phy
	pinctrl-names = "default";
	//pinctrl-0 = <&rgmii1_pins &mdio_pins>;
	pinctrl-0 = <&rgmii1_pins>;

	port@5 {
		status = "okay";
		phy-mode = "rgmii";
		mediatek,fixed-link = <1000 1 1 1>;
		phy-handle = <&phy0>;

	};


	/*
	mdio-bus {
		status = "okay";
		mediatek,mdio-mode = <1>;
		phy0: ethernet-phy@0 {
			reg = <0>;
			phy-mode = "rgmii";
			qca,ar8327-initvals = <
				0x04 0x06200000 		//	PORT0 PAD MODE CTRL 
				0x08 0x01000000 		//	PORT5 PAD MODE CTRL  RX delay EN all ports 0, 5, 6 
				0x0c 0x00000000 		//	PORT6 PAD MODE CTRL 
				0x7C 0x0000004e 		//	PORT0_STATUS 
				0x94 0x00000000 		//	PORT6_STATUS 
				0xE4 0x000AA545 	//	MAC_POWER_SEL
				
				 0x970 0x1E864443 	//	PORT0_HOL_CTRL0 
				0x974 0x000001C6  	//	PORT0_HOL_CTRL1 
				0x978 0x19008643   	//	PORT1_HOL_CTRL0 
				0x97C 0x000001C6 	//	PORT1_HOL_CTRL1 
				0x980 0x19008643 	//	PORT2_HOL_CTRL0 
				0x984 0x000001C6 	//	PORT2_HOL_CTRL1 
				0x988 0x19008643 	// 	PORT3_HOL_CTRL0 
				0x98C 0x000001C6	// 	PORT3_HOL_CTRL1 
				0x990 0x19008643 	// 	PORT4_HOL_CTRL0 
				0x994 0x000001C6 	// 	PORT4_HOL_CTRL1 
				0x998 0x1E864443 	// 	PORT5_HOL_CTRL0 
				0x99C 0x000001C6 	//	PORT5_HOL_CTRL1 
				0x9A0 0x1E864443 	// 	PORT6_HOL_CTRL0 
				0x9A4 0x000001C6 	// 	PORT6_HOL_CTRL1 
			>;
		};
	};

	
	*/

};

/*
&ehci {
	status = "okay";
};
*/

&ohci {
	status = "okay";
};

&wmac {
	status = "okay";
	ralink,mtd-eeprom = <&factory 0>;
};

&pinctrl {
	state_default: pinctrl0 {
		gpio {
			ralink,group = "uartf", "i2c", "rgmii2", "wled", "spi refclk", "jtag", "ephy",  "nd_sd"; 	// wled HW driving does not work
			//	ralink,group = "uartf", "i2c", "rgmii2", "spi refclk", "jtag", "ephy",  "nd_sd"; 		//wled is already driven  by WiFi on GPIO 72
			ralink,function = "gpio";
		};
	};
};

Finally I fixed the *.dts code to be compiled, but it did not instatiated the SW MDIO. So I invesitgated others ways and finally I can confirm what it was identified for other MT7620 QCA8337 router:

the extra MT7620 mdio setting in:
openwrt/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c
mess up the setting of QCA8337.
The MT7620 mdio extra setting have to be skipped in case of external switch usage, or at least in case of specific switch like QCA8337, AR8327...

Some other small issue about the WiFi LED. I added:

sitecom,wlr-4100v1002)
	set_wifi_led "$boardname::blue:wifi2g"
	ucidef_set_led_netdev "lan" "lan" "$boardname::white:wps" "eth0"
	;;

in 01_leds leading to the following section in /etc/config/system:

config led 'led_wifi_led'
	option name 'wifi'
	option sysfs 'wlr-4100v1002::blue:wifi2g'
	option trigger 'netdev'
	option mode 'link tx rx'
	option dev 'wlan0'

config led 'led_lan'
	option name 'lan'
	option sysfs 'wlr-4100v1002::white:wps'
	option trigger 'netdev'
	option mode 'link tx rx'
	option dev 'eth0'

which does not work.
after setting LEDs in LUCI I get:

config led 'led_wifi_led'
	option name 'wifi'
	option trigger 'netdev'
	option dev 'wlan0'
	option sysfs 'wlr-4100v1002:blue:wifi2g'
	option default '0'
	list mode 'link'
	list mode 'tx'
	list mode 'rx'

which works.
How can I modify 01_leds?

LED's names $boardname::blue:wifi2g and $boardname::white:wps must match to label properties of corresponding leds in dts-file.
So simply change:
$boardname::blue:wifi2g to $boardname:blue:wifi2g
$boardname::white:wps to $boardname:white:wps
in 01_leds

1 Like

fixes and cleanup of MT7620 ethernet driver now in master, ready to backport after testing

I successfully tested WLR-4100 on Master therefore I created PR4308 .
I am compiling the WLR-4100 for 21.02. I may test it tonight.

@mpratt14 @123serge123 Thank you very much for your effort on MT7620

1 Like

In 21.02 the MT7620A QCA8337 connection is broken because the fixing is needed in 21.02 as well: