Before yesterday, I was testing the OpenWRT snapshot by uploading it to RAM using *initramfs-kernel.bin without touching the flash.
It worked fine with any setting of the clocks of the switch0 <-> switch1 interface. I left no clock delay in both RX and TX clocks.
Yesterday I did the big step by burning *squashfs-sysupgrade.bin on flash.
I noticed the switches interface did not work like it did with equivalent initramfs-kernel.bin.
Finally I restored the clock delay on both switch0 directions and I found, after several attempts, the magic numbers: TXclk=0, RXclk=2.
I discover that the QCA8337 RGMII RX clock is actually a single output used for all ports: 0, 5 and 6. The delay of this output clock is enabled in the Port5 pad mode Ctrl register.
/dts-v1/;
#include "mt7620a.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
compatible = "sitecom,wlr-4100", "ralink,mt7620a-soc";
model = "Sitecom WLR-4100 v1 002 sw21";
aliases {
led-boot = &led_status;
led-failsafe = &led_status;
led-running = &led_status;
led-upgrade = &led_status;
};
chosen {
bootargs = "console=ttyS0,115200";
};
keys {
compatible = "gpio-keys-polled";
poll-interval = <20>;
//SENAO_GPIO_BUTTON_WPS 2
wps {
label = "wps";
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
//SENAO_GPIO_HW_RESET 17
/* reset {
label = "reset";
gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
*/
};
leds {
compatible = "gpio-leds";
//SENAO_GPIO_LED_POWER 9
led_status: status {
label = "wlr-4100:green:status";
gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
};
//SENAO_GPIO_LED_24G 72
wifi2g {
label = "wlr-4100:green:wifi2g";
gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
};
//SENAO_GPIO_LED_WPS 39
/* led_wps: wps {
label = "wlr-4100:blue:wps";
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
*/
};
//SENAO_GPIO_POWER_USB 38
//SENAO_GPIO_SWITCH_RESET 45
/*
gpio_export {
compatible = "gpio-export";
#size-cells = <0>;
usb-power {
gpio-export,name = "usb-power";
gpio-export,output = <1>;
gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
};
};
*/
};
&gpio0 {
status = "okay";
};
/*
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
*/
&gpio3 {
status = "okay";
};
&spi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "uboot";
reg = <0x0 0x30000>;
read-only;
};
config: partition@30000 {
label = "config";
reg = <0x30000 0x10000>;
read-only;
};
factory: partition@40000 {
label = "factory";
reg = <0x40000 0x10000>;
read-only;
};
partition@50000 {
compatible = "denx,uimage";
label = "firmware";
reg = <0x50000 0x790000>;
};
partition@7e0000 {
label = "backup";
reg = <0x7e0000 0x10000>;
read-only;
};
partition@7f0000 {
label = "storage";
reg = <0x7f0000 0x10000>;
read-only;
};
};
};
};
ðernet {
status = "okay";
mtd-mac-address = <&factory 0x4>;
// mediatek,portmap = "wllll";
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
port@5 {
status = "okay";
phy-mode = "rgmii";
mediatek,fixed-link = <1000 1 1 1>;
phy-handle = <&phy0>;
};
mdio-bus {
status = "okay";
mediatek,mdio-mode = <1>;
phy0: ethernet-phy@0 {
reg = <0>;
phy-mode = "rgmii";
qca,ar8327-initvals = <
0x04 0x06200000 /* PORT0 PAD MODE CTRL */
0x08 0x01000000 /* PORT5 PAD MODE CTRL RX delay EN all ports 0, 5, 6 */
0x7c 0x0000007e /* PORT0_STATUS */
>;
};
phy1: ethernet-phy@1 {
reg = <1>;
phy-mode = "rgmii";
};
phy2: ethernet-phy@2 {
reg = <2>;
phy-mode = "rgmii";
};
phy3: ethernet-phy@3 {
reg = <3>;
phy-mode = "rgmii";
};
phy4: ethernet-phy@4 {
reg = <4>;
phy-mode = "rgmii";
};
};
};
/*
&gsw {
mediatek,port4="gmac";
};
*/
&ehci {
status = "okay";
};
&ohci {
status = "okay";
};
&wmac {
status = "okay";
ralink,mtd-eeprom = <&factory 0>;
};
/*
&pcie {
status = "okay";
};
&pcie0 {
wifi@0,0 {
reg = <0x0000 0 0 0 0>;
mediatek,mtd-eeprom = <&factory 0x8000>;
mediatek,2ghz = <0>;
};
};
*/
&pinctrl {
state_default: pinctrl0 {
gpio {
//ralink,group = "mdio", "rgmii1", "uartf", "i2c", "wled";
ralink,group = "uartf", "i2c", "wled";
ralink,function = "gpio";
};
};
};
Now it works but I have to keep the RS232 connected because I have to issue the commands:
swconfig dev switch0 set reset 1
swconfig dev switch0 set enable_vlan 1
swconfig dev switch0 vlan 1 set ports '0t 1 2 3 4'
swconfig dev switch0 vlan 2 set ports '0t 5'
swconfig dev switch0 set ar8xxx_mib_poll_interval 100
swconfig dev switch0 set ar8xxx_mib_type 1
swconfig dev switch0 set apply 1
For allowing the device access, after the burning on the flash.
How can I embed the VLAN setting in squashfs-sysupgrade.bin file?
This will allow me to access from the Ethrenet and to disconnect RS232.
Have a nice week-end