SamKnows SK-WB8 MT7621 bricked

waldyrdias · December 20, 2022, 2:01pm

Help me please, I went to update my sk-wb8 , now it doesn't want to boot. Thank you very much.

===================================================================
                MT7621   stage1 code Mar 12 2015 14:43:30 (ASIC)
                CPU=500000000 HZ BUS=125000000 HZ
==================================================================
Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x31100000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-800Mhz ===
PLL3 FB_DL: 0x0, 1/0 = 753/271 01000000
PLL2 FB_DL: 0x13, 1/0 = 568/456 4D000000
PLL4 FB_DL: 0x16, 1/0 = 575/449 59000000
do DDR setting..[01F40000]
Apply DDR2 Setting...(use customer AC)
          0    8   16   24   32   40   48   56   64   72   80   88   96  104  112  120
      --------------------------------------------------------------------------------
0000:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0001:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0002:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0003:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0004:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0005:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0006:|    0    0    0    0    0    0    0    0    0    0    0    0    0    1    1    1
0007:|    0    0    0    0    0    0    1    1    1    1    1    1    1    1    1    1
0008:|    1    1    1    1    1    1    1    1    1    1    1    1    0    0    0    0
0009:|    1    1    1    1    1    0    0    0    0    0    0    0    0    0    0    0
000A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000E:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000F:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0010:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0011:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0012:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0013:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0014:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0015:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0016:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0017:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0018:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0019:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001E:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001F:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
DRAMC_DQSCTL1[0e0]=1A000000
DRAMC_DQSGCTL[124]=80000000
rank 0 coarse = 8
rank 0 fine = 48
B:|    0    0    0    0    0    1    1    1    0    0    0    0    0    0    0    0
opt_dle value:6
DRAMC_DDR2CTL[07c]=40001263
DRAMC_PADCTL4[0e4]=00000005
DRAMC_DQIDLY1[210]=0B0C090B
DRAMC_DQIDLY2[214]=060A060A
DRAMC_DQIDLY3[218]=0F090C08
DRAMC_DQIDLY4[21c]=0B070C08
DRAMC_R0DELDLY[018]=00002A2A
==================================================================
                RX      DQS perbit delay software calibration
==================================================================
1.0-15 bit dq delay value
==================================================================
bit|     0  1  2  3  4  5  6  7  8  9
--------------------------------------
0 |    10 8 9 10 10 6 9 5 7 11
10 |    8 15 8 11 7 11
--------------------------------------

==================================================================
2.dqs window
x=pass dqs delay value (min~max)center
y=0-7bit DQ of every group
input delay:DQS0 =42 DQS1 = 42
==================================================================
bit     DQS0     bit      DQS1
0  (1~82)41  8  (1~81)41
1  (0~82)41  9  (1~82)41
2  (1~78)39  10  (0~82)41
3  (1~82)41  11  (1~84)42
4  (1~84)42  12  (1~84)42
5  (2~82)42  13  (1~82)41
6  (1~81)41  14  (1~84)42
7  (1~82)41  15  (1~84)42
==================================================================
3.dq delay value last
==================================================================
bit|    0  1  2  3  4  5  6  7  8   9
--------------------------------------
0 |    11 9 12 11 10 6 10 6 8 12
10 |    9 15 8 12 7 11
==================================================================
==================================================================
     TX  perbyte calibration
==================================================================
DQS loop = 15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqsdly_pass[0]=15,  finish count=1
dqs_perbyte_dly.last_dqsdly_pass[1]=15,  finish count=2
DQ loop=15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqdly_pass[0]=15,  finish count=1
dqs_perbyte_dly.last_dqdly_pass[1]=15,  finish count=2
byte:0, (DQS,DQ)=(8,8)
byte:1, (DQS,DQ)=(8,8)
DRAMC_DQODLY1[200]=88888888
DRAMC_DQODLY2[204]=88888888
20,data:88
[EMI] DRAMC calibration passed

===================================================================
                MT7621   stage1 code done
                CPU=500000000 HZ BUS=125000000 HZ
===================================================================


U-Boot 1.1.3 (Jan 15 2016 - 09:47:18)

Board: Ralink APSoC DRAM:  128 MB
relocate_code Pointer at: 87fb8000

Config XHCI 40M PLL
flash manufacture id: ef, device id 40 18
find flash: W25Q128BV
============================================
Ralink UBoot Version: 4.3.0.0
--------------------------------------------
ASIC MT7621A DualCore (MAC to MT7530 Mode)
DRAM_CONF_FROM: Auto-Detection
DRAM_TYPE: DDR2
DRAM bus: 16 bit
Xtal Mode=3 OCP Ratio=1/4
Flash component: SPI Flash
Date:Jan 15 2016  Time:09:47:18
============================================
icache: sets:256, ways:4, linesz:32 ,total:32768
dcache: sets:256, ways:4, linesz:32 ,total:32768

 ##### The CPU freq = 880 MHZ ####
 estimate memory size =128 Mbytes
#Reset_MT7530

Please choose the operation:
   1: Load system code to SDRAM via TFTP.
   2: Load system code then write to Flash via TFTP.
   3: Boot system code via Flash (default).
   4: Entr boot command line interface.
   7: Load Boot Loader code then write to Flash via Serial.
   9: Load Boot Loader code then write to Flash via TFTP.

You choosed 3

 0
bootcount: 4

3: System Boot system code via Flash.
Erasing SPI Flash...
.
Writing to SPI Flash...
.
done
## Booting image at bce30000 ...
Bad Magic Number,85190320

frollic · December 20, 2022, 2:10pm

tried the debricking guide from the devices wiki page ?

lleachii · December 20, 2022, 2:45pm

What happened since it was working here?

mmstano · December 20, 2022, 3:56pm

As @frollic mentioned, you’ll need to follow the instructions in this debricking guide

The devs highly advise against updating core packages and include warnings about it here

If you want to update/upgrade core packages next time, you should backup your config and run a sysupgrade, instead of using CLI/Luci opkg

waldyrdias · December 20, 2022, 5:19pm

Yes, it doesn't want to go into TFTP mode.

frollic · December 20, 2022, 5:20pm

Define doesn't want to...

mk24 · December 20, 2022, 5:25pm

It is trying to boot the recovery partition. It should boot to bc050000 instead which is where OpenWrt is installed. Check the boot environment by hitting 4 at the menu to get the prompt and type printenv.

mmstano · December 20, 2022, 5:37pm

Make sure you know what your device is looking for. It should be listed in the device’s wiki. Not all devices run as a TFTP client. Some devices run as a TFTP server and you’ll need to run your console/PC as the client.

waldyrdias · December 21, 2022, 12:24am


===================================================================
                MT7621   stage1 code done
                CPU=500000000 HZ BUS=125000000 HZ
===================================================================


U-Boot 1.1.3 (Jan 15 2016 - 09:47:18)

Board: Ralink APSoC DRAM:  128 MB
relocate_code Pointer at: 87fb8000

Config XHCI 40M PLL
flash manufacture id: ef, device id 40 18
find flash: W25Q128BV
============================================
Ralink UBoot Version: 4.3.0.0
--------------------------------------------
ASIC MT7621A DualCore (MAC to MT7530 Mode)
DRAM_CONF_FROM: Auto-Detection
DRAM_TYPE: DDR2
DRAM bus: 16 bit
Xtal Mode=3 OCP Ratio=1/4
Flash component: SPI Flash
Date:Jan 15 2016  Time:09:47:18
============================================
icache: sets:256, ways:4, linesz:32 ,total:32768
dcache: sets:256, ways:4, linesz:32 ,total:32768

 ##### The CPU freq = 880 MHZ ####
 estimate memory size =128 Mbytes
#Reset_MT7530

Please choose the operation:
   1: Load system code to SDRAM via TFTP.
   2: Load system code then write to Flash via TFTP.
   3: Boot system code via Flash (default).
   4: Entr boot command line interface.
   7: Load Boot Loader code then write to Flash via Serial.
   9: Load Boot Loader code then write to Flash via TFTP.

You choosed 3

 0
bootcount: 4

3: System Boot system code via Flash.
Erasing SPI Flash...
.
Writing to SPI Flash...
.
done
## Booting image at bce30000 ...
Bad Magic Number,85190320

waldyrdias · December 21, 2022, 12:29am

I thought I could turn the sk-wb8 into a xiaomi r3g because it had the same hardware.

psherman · December 21, 2022, 12:35am

What value would you have gained from this 'conversion'?

Having the same hardware does not mean it is actually the same device. To use a silly example: a Mac with an Intel processor is using the "same hardware" (from a CPU perspective) as a generic PC, but it is most certainly not the same. On a router like this, there are rarely devices from different companies that are truly the same under the hood... everything from the configuration of the ethernet ports and radios (and the logical/physical mappings thereof) to the GPIOs used for LEDs and reset button to the boot loader and flash memory layout are frequently all bespoke.

waldyrdias · December 21, 2022, 1:04am

I think I lost my router. The command for tftp does not work.

psherman · December 21, 2022, 1:09am

Bummer... how familiar are you with in-system-programmers? You may need to use such a device to reprogram your flash chip.

waldyrdias · December 21, 2022, 1:15am

What do I have to buy? I already have access via usb serial.

psherman · December 21, 2022, 1:20am

Maybe something like this:

But it depends on the hardware details of your device. And then you have to learn to use it and you need the correct file to flash to the chip.... be aware that the flash chip may contain factory calibration data for the wifi (known as the "ART" partition) that will render your wifi radios inoperable if you overwrite or corrupt the data.

mk24 · December 21, 2022, 1:57am

Hit 4 to get the prompt then run the command bootm bc050000
If OpenWrt boots, read the footnote about bootcount at the bottom of the OpenWrt device wiki page.

frollic · December 21, 2022, 5:44am

You really don't read the replies you're getting, do you?

What doesn't work?

waldyrdias · December 21, 2022, 2:16pm

                MT7621   stage1 code done
                CPU=500000000 HZ BUS=125000000 HZ
===================================================================


U-Boot 1.1.3 (Jan 15 2016 - 09:47:18)

Board: Ralink APSoC DRAM:  128 MB
relocate_code Pointer at: 87fb8000

Config XHCI 40M PLL
******************************
Software System Reset Occurred
******************************
flash manufacture id: ef, device id 40 18
find flash: W25Q128BV
============================================
Ralink UBoot Version: 4.3.0.0
--------------------------------------------
ASIC MT7621A DualCore (MAC to MT7530 Mode)
DRAM_CONF_FROM: Auto-Detection
DRAM_TYPE: DDR2
DRAM bus: 16 bit
Xtal Mode=3 OCP Ratio=1/4
Flash component: SPI Flash
Date:Jan 15 2016  Time:09:47:18
============================================
icache: sets:256, ways:4, linesz:32 ,total:32768
dcache: sets:256, ways:4, linesz:32 ,total:32768

 ##### The CPU freq = 880 MHZ ####
 estimate memory size =128 Mbytes
#Reset_MT7530

Please choose the operation:
   1: Load system code to SDRAM via TFTP.
   2: Load system code then write to Flash via TFTP.
   3: Boot system code via Flash (default).
   4: Entr boot command line interface.
   7: Load Boot Loader code then write to Flash via Serial.
   9: Load Boot Loader code then write to Flash via TFTP.

You choosed 3
                                                                              0
bootcount: 2

3: System Boot system code via Flash.
Erasing SPI Flash...
.
Writing to SPI Flash...
.
done
## Booting image at bc050000 ...
   Image Name:   MIPS OpenWrt Linux-5.10.146
   Image Type:   MIPS Linux Kernel Image (uncompressed)
   Data Size:    2690657 Bytes =  2.6 MB
   Load Address: 80001000
   Entry Point:  80001000
   Verifying Checksum ... OK
OK
No initrd
## Transferring control to Linux (at address 80001000) ...
## Giving linux memsize in MB, 128

Starting kernel ...

waldyrdias · December 21, 2022, 2:17pm

infinite loop

waldyrdias · December 21, 2022, 2:18pm

Number 4 doesn't work.