SamKnows SK-WB8 MT7621 bricked with latest snapshot

Hello all! Help needed!
I installed https://downloads.openwrt.org/snapshots/targets/ramips/mt7621/openwrt-ramips-mt7621-samknows_whitebox-v8-squashfs-sysupgrade.bin 17Feb version. I flashed it on Luci running 19.07.6.
I chose not to keep settings and forced installed after warning.
The device now seems to be bricked witherror:

## Booting image at bce30000 ...
Bad Magic Number,85190320

I connect with serial console to try to debrick it with tftp method. i'm trying to flash openwrt-19.07.6-ramips-mt7621-sk-wb8-squashfs-sysupgrade and i receive:

TIMEOUT_COUNT=10,Load address: 0x80100000
Loading: checksum bad
checksum bad
checksum bad
checksum bad
checksum bad
checksum bad
checksum bad
checksum bad
checksum bad
Got ARP REPLY, set server/gtwy eth addr (3c:a8:2a:79:85:b0)
Got it
T T T T T T T T T T
Retry count exceeded; starting again
TFTP from server 10.10.10.3; our IP address is 10.98.11.62
Filename '1.bin'.

Somebody can help? Thanks!
Below is the code.


===================================================================
                MT7621   stage1 code Mar 12 2015 14:43:30 (ASIC)
                CPU=500000000 HZ BUS=125000000 HZ
==================================================================
Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x31100000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-800Mhz ===
PLL2 FB_DL: 0x0, 1/0 = 1002/22 01000000
PLL4 FB_DL: 0xe, 1/0 = 603/421 39000000
PLL3 FB_DL: 0x18, 1/0 = 584/440 61000000
do DDR setting..[01F40000]
Apply DDR2 Setting...(use customer AC)
          0    8   16   24   32   40   48   56   64   72   80   88   96  104  11  2  120
      --------------------------------------------------------------------------  ------
0000:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0001:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0002:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0003:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0004:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0005:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0006:|    0    0    0    0    0    0    0    0    0    0    0    0    0    1      1    1
0007:|    0    0    0    0    0    0    1    1    1    1    1    1    1    1      1    1
0008:|    1    1    1    1    1    1    1    1    1    1    1    1    1    0      0    0
0009:|    1    1    1    1    1    0    0    0    0    0    0    0    0    0      0    0
000A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
000B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
000C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
000D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
000E:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
000F:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0010:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0011:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0012:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0013:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0014:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0015:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0016:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0017:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0018:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0019:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
001A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
001B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
001C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
001D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
001E:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
001F:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
DRAMC_DQSCTL1[0e0]=1A000000
DRAMC_DQSGCTL[124]=80000000
rank 0 coarse = 8
rank 0 fine = 48
B:|    0    0    0    0    0    1    1    1    0    0    0    0    0    0    0      0
opt_dle value:6
DRAMC_DDR2CTL[07c]=40001263
DRAMC_PADCTL4[0e4]=00000005
DRAMC_DQIDLY1[210]=0B08080A
DRAMC_DQIDLY2[214]=060A070A
DRAMC_DQIDLY3[218]=09060805
DRAMC_DQIDLY4[21c]=08060806
DRAMC_R0DELDLY[018]=00003031
==================================================================
                RX      DQS perbit delay software calibration
==================================================================
1.0-15 bit dq delay value
==================================================================
bit|     0  1  2  3  4  5  6  7  8  9
--------------------------------------
0 |    9 7 7 10 8 7 9 5 4 6
10 |    5 7 6 7 5 6
--------------------------------------

==================================================================
2.dqs window
x=pass dqs delay value (min~max)center
y=0-7bit DQ of every group
input delay:DQS0 =49 DQS1 = 48
==================================================================
bit     DQS0     bit      DQS1
0  (1~95)48  8  (1~94)47
1  (1~95)48  9  (1~92)46
2  (1~95)48  10  (1~94)47
3  (1~96)48  11  (1~91)46
4  (1~94)47  12  (1~95)48
5  (2~97)49  13  (1~94)47
6  (2~95)48  14  (1~94)47
7  (1~95)48  15  (1~91)46
==================================================================
3.dq delay value last
==================================================================
bit|    0  1  2  3  4  5  6  7  8   9
--------------------------------------
0 |    10 8 8 11 10 7 10 6 5 8
10 |    6 9 6 8 6 8
==================================================================
==================================================================
     TX  perbyte calibration
==================================================================
DQS loop = 15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqsdly_pass[0]=15,  finish count=1
dqs_perbyte_dly.last_dqsdly_pass[1]=15,  finish count=2
DQ loop=15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqdly_pass[0]=15,  finish count=1
dqs_perbyte_dly.last_dqdly_pass[1]=15,  finish count=2
byte:0, (DQS,DQ)=(8,8)
byte:1, (DQS,DQ)=(8,8)
DRAMC_DQODLY1[200]=88888888
DRAMC_DQODLY2[204]=88888888
20,data:88
[EMI] DRAMC calibration passed

===================================================================
                MT7621   stage1 code done
                CPU=500000000 HZ BUS=125000000 HZ
===================================================================


U-Boot 1.1.3 (Jan 15 2016 - 09:47:18)

Board: Ralink APSoC DRAM:  128 MB
relocate_code Pointer at: 87fb8000

Config XHCI 40M PLL
flash manufacture id: 1, device id 20 18
find flash: S25FL128P
============================================
Ralink UBoot Version: 4.3.0.0
--------------------------------------------
ASIC MT7621A DualCore (MAC to MT7530 Mode)
DRAM_CONF_FROM: Auto-Detection
DRAM_TYPE: DDR2
DRAM bus: 16 bit
Xtal Mode=3 OCP Ratio=1/4
Flash component: SPI Flash
Date:Jan 15 2016  Time:09:47:18
============================================
icache: sets:256, ways:4, linesz:32 ,total:32768
dcache: sets:256, ways:4, linesz:32 ,total:32768

 ##### The CPU freq = 880 MHZ ####
 estimate memory size =128 Mbytes
#Reset_MT7530

Please choose the operation:
   1: Load system code to SDRAM via TFTP.
   2: Load system code then write to Flash via TFTP.
   3: Boot system code via Flash (default).
   4: Entr boot command line interface.
   7: Load Boot Loader code then write to Flash via Serial.
   9: Load Boot Loader code then write to Flash via TFTP.

You choosed 2
                                                                              0


2: System Load Linux Kernel then write to Flash via TFTP.
 Warning!! Erase Linux in Flash then burn new one. Are you sure?(Y/N)
 Operation terminated

===================================================================
                MT7621   stage1 code Mar 12 2015 14:43:30 (ASIC)
                CPU=500000000 HZ BUS=125000000 HZ
==================================================================
Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x31100000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-800Mhz ===
PLL2 FB_DL: 0x0, 1/0 = 998/26 01000000
PLL4 FB_DL: 0xe, 1/0 = 636/388 39000000
PLL3 FB_DL: 0x18, 1/0 = 598/426 61000000
do DDR setting..[01F40000]
Apply DDR2 Setting...(use customer AC)
          0    8   16   24   32   40   48   56   64   72   80   88   96  104  11  2  120
      --------------------------------------------------------------------------  ------
0000:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0001:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0002:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0003:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0004:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0005:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0006:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      1    1
0007:|    0    0    0    0    0    0    1    1    1    1    1    1    1    1      1    1
0008:|    1    1    1    1    1    1    1    1    1    1    1    1    1    0      0    0
0009:|    1    1    1    1    1    0    0    0    0    0    0    0    0    0      0    0
000A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
000B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
000C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
000D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
000E:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
000F:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0010:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0011:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0012:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0013:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0014:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0015:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0016:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0017:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0018:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0019:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
001A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
001B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
001C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
001D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
001E:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
001F:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
DRAMC_DQSCTL1[0e0]=1A000000
DRAMC_DQSGCTL[124]=80000000
rank 0 coarse = 8
rank 0 fine = 48
B:|    0    0    0    0    1    1    1    0    0    0    0    0    0    0    0      0
opt_dle value:5
DRAMC_DDR2CTL[07c]=40001253
DRAMC_PADCTL4[0e4]=00000005
DRAMC_DQIDLY1[210]=0B08080A
DRAMC_DQIDLY2[214]=060A0709
DRAMC_DQIDLY3[218]=09060804
DRAMC_DQIDLY4[21c]=08050806
DRAMC_R0DELDLY[018]=00003031
==================================================================
                RX      DQS perbit delay software calibration
==================================================================
1.0-15 bit dq delay value
==================================================================
bit|     0  1  2  3  4  5  6  7  8  9
--------------------------------------
0 |    9 7 7 10 8 7 9 5 3 6
10 |    5 7 6 7 5 6
--------------------------------------

==================================================================
2.dqs window
x=pass dqs delay value (min~max)center
y=0-7bit DQ of every group
input delay:DQS0 =49 DQS1 = 48
==================================================================
bit     DQS0     bit      DQS1
0  (1~96)48  8  (1~94)47
1  (1~96)48  9  (1~92)46
2  (1~95)48  10  (1~93)47
3  (1~96)48  11  (1~92)46
4  (1~95)48  12  (1~96)48
5  (1~97)49  13  (1~94)47
6  (2~95)48  14  (1~95)48
7  (1~95)48  15  (1~92)46
==================================================================
3.dq delay value last
==================================================================
bit|    0  1  2  3  4  5  6  7  8   9
--------------------------------------
0 |    10 8 8 11 9 7 10 6 4 8
10 |    6 9 6 8 5 8
==================================================================
==================================================================
     TX  perbyte calibration
==================================================================
DQS loop = 15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqsdly_pass[0]=15,  finish count=1
dqs_perbyte_dly.last_dqsdly_pass[1]=15,  finish count=2
DQ loop=15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqdly_pass[0]=15,  finish count=1
dqs_perbyte_dly.last_dqdly_pass[1]=15,  finish count=2
byte:0, (DQS,DQ)=(8,8)
byte:1, (DQS,DQ)=(8,8)
DRAMC_DQODLY1[200]=88888888
DRAMC_DQODLY2[204]=88888888
20,data:88
[EMI] DRAMC calibration passed

===================================================================
                MT7621   stage1 code done
                CPU=500000000 HZ BUS=125000000 HZ
===================================================================


U-Boot 1.1.3 (Jan 15 2016 - 09:47:18)

Board: Ralink APSoC DRAM:  128 MB
relocate_code Pointer at: 87fb8000

Config XHCI 40M PLL
******************************
Software System Reset Occurred
******************************
flash manufacture id: 1, device id 20 18
find flash: S25FL128P
============================================
Ralink UBoot Version: 4.3.0.0
--------------------------------------------
ASIC MT7621A DualCore (MAC to MT7530 Mode)
DRAM_CONF_FROM: Auto-Detection
DRAM_TYPE: DDR2
DRAM bus: 16 bit
Xtal Mode=3 OCP Ratio=1/4
Flash component: SPI Flash
Date:Jan 15 2016  Time:09:47:18
============================================
icache: sets:256, ways:4, linesz:32 ,total:32768
dcache: sets:256, ways:4, linesz:32 ,total:32768

 ##### The CPU freq = 880 MHZ ####
 estimate memory size =128 Mbytes
#Reset_MT7530

Please choose the operation:
   1: Load system code to SDRAM via TFTP.
   2: Load system code then write to Flash via TFTP.
   3: Boot system code via Flash (default).
   4: Entr boot command line interface.
   7: Load Boot Loader code then write to Flash via Serial.
   9: Load Boot Loader code then write to Flash via TFTP.                     2
You choosed 2
                                                                              0


2: System Load Linux Kernel then write to Flash via TFTP.
 Warning!! Erase Linux in Flash then burn new one. Are you sure?(Y/N)
 Please Input new ones /or Ctrl-C to discard
        Input device IP (10.98.11.62) ==:10.10.10.1
        Input server IP (10.10.10.3) ==:10.10.10.3
        Input Linux Kernel filename () ==:openwrt.bin

 netboot_common, argc= 3

 NetTxPacket = 0x87FE4B80

 KSEG1ADDR(NetTxPacket) = 0xA7FE4B80

 NetLoop,call eth_halt !

 NetLoop,call eth_init !
Trying Eth0 (10/100-M)

 Waitting for RX_DMA_BUSY status Start... done


 ETH_STATE_ACTIVE!!
TFTP from server 10.10.10.3; our IP address is 10.10.10.1
Filename 'openwrt.bin'.

 TIMEOUT_COUNT=10,Load address: 0x80100000
Loading: checksum bad
checksum bad
checksum bad
checksum bad
checksum bad
checksum bad
checksum bad
Got ARP REPLY, set server/gtwy eth addr (3c:a8:2a:79:85:b0)
Got it
T T T T T T T T T T
Retry count exceeded; starting again
TFTP from server 10.10.10.3; our IP address is 10.10.10.1
Filename 'openwrt.bin'.

 TIMEOUT_COUNT=10,Load address: 0x80100000
Loading: Got ARP REPLY, set server/gtwy eth addr (3c:a8:2a:79:85:b0)
Got it
T T T T T T T T T T
Retry count exceeded; starting again
TFTP from server 10.10.10.3; our IP address is 10.10.10.1
Filename 'openwrt.bin'.

 TIMEOUT_COUNT=10,Load address: 0x80100000
Loading: Got ARP REPLY, set server/gtwy eth addr (3c:a8:2a:79:85:b0)
Got it
T T T T T T T T T T
Retry count exceeded; starting again
TFTP from server 10.10.10.3; our IP address is 10.10.10.1
Filename 'openwrt.bin'.

 TIMEOUT_COUNT=10,Load address: 0x80100000
Loading: Got ARP REPLY, set server/gtwy eth addr (3c:a8:2a:79:85:b0)
Got it
T T T T T T T T T T
Retry count exceeded; starting again
TFTP from server 10.10.10.3; our IP address is 10.10.10.1
Filename 'openwrt.bin'.

 TIMEOUT_COUNT=10,Load address: 0x80100000
Loading: Got ARP REPLY, set server/gtwy eth addr (3c:a8:2a:79:85:b0)
Got it
T T T T T T T T T T
Retry count exceeded; starting again
TFTP from server 10.10.10.3; our IP address is 10.10.10.1
Filename 'openwrt.bin'.

 TIMEOUT_COUNT=10,Load address: 0x80100000
Loading: Got ARP REPLY, set server/gtwy eth addr (3c:a8:2a:79:85:b0)
Got it
T T T T T T T T T T
Retry count exceeded; starting again
TFTP from server 10.10.10.3; our IP address is 10.10.10.1
Filename 'openwrt.bin'.

 TIMEOUT_COUNT=10,Load address: 0x80100000
Loading: Got ARP REPLY, set server/gtwy eth addr (3c:a8:2a:79:85:b0)
Got it
T T T T T T T T T T
Retry count exceeded; starting again
TFTP from server 10.10.10.3; our IP address is 10.10.10.1
Filename 'openwrt.bin'.

 TIMEOUT_COUNT=10,Load address: 0x80100000
Loading: Got ARP REPLY, set server/gtwy eth addr (3c:a8:2a:79:85:b0)
Got it
T T T T T T T T T T
Retry count exceeded; starting again
TFTP from server 10.10.10.3; our IP address is 10.10.10.1
Filename 'openwrt.bin'.

 TIMEOUT_COUNT=10,Load address: 0x80100000
Loading: Got ARP REPLY, set server/gtwy eth addr (3c:a8:2a:79:85:b0)
Got it
T T T T T T T T T T
Retry count exceeded; starting again
TFTP from server 10.10.10.3; our IP address is 10.10.10.1
Filename 'openwrt.bin'.

 TIMEOUT_COUNT=10,Load address: 0x80100000
Loading: Got ARP REPLY, set server/gtwy eth addr (3c:a8:2a:79:85:b0)
Got it
T T T T T T T T T T
Retry count exceeded; starting again
TFTP from server 10.10.10.3; our IP address is 10.10.10.1
Filename 'openwrt.bin'.

 TIMEOUT_COUNT=10,Load address: 0x80100000
Loading: Got ARP REPLY, set server/gtwy eth addr (3c:a8:2a:79:85:b0)
Got it
T T T T T T T T T T
Retry count exceeded; starting again
TFTP from server 10.10.10.3; our IP address is 10.10.10.1
Filename 'openwrt.bin'.

 TIMEOUT_COUNT=10,Load address: 0x80100000
Loading: Got ARP REPLY, set server/gtwy eth addr (3c:a8:2a:79:85:b0)
Got it
T T T T T T T T T T
Retry count exceeded; starting again
TFTP from server 10.10.10.3; our IP address is 10.10.10.1
Filename 'openwrt.bin'.

 TIMEOUT_COUNT=10,Load address: 0x80100000
Loading: Got ARP REPLY, set server/gtwy eth addr (3c:a8:2a:79:85:b0)
Got it
T T T T T T T T T T
Retry count exceeded; starting again
TFTP from server 10.10.10.3; our IP address is 10.10.10.1
Filename 'openwrt.bin'.

 TIMEOUT_COUNT=10,Load address: 0x80100000
Loading: Got ARP REPLY, set server/gtwy eth addr (3c:a8:2a:79:85:b0)
Got it
T T T T T T T T T T
Retry count exceeded; starting again
TFTP from server 10.10.10.3; our IP address is 10.10.10.1
Filename 'openwrt.bin'.

 TIMEOUT_COUNT=10,Load address: 0x80100000
Loading: Got ARP REPLY, set server/gtwy eth addr (3c:a8:2a:79:85:b0)
Got it
T T T T T T T T T T
Retry count exceeded; starting again
TFTP from server 10.10.10.3; our IP address is 10.10.10.1
Filename 'openwrt.bin'.

 TIMEOUT_COUNT=10,Load address: 0x80100000
Loading: Got ARP REPLY, set server/gtwy eth addr (3c:a8:2a:79:85:b0)
Got it
T T T T T T T T T T
Retry count exceeded; starting again
TFTP from server 10.10.10.3; our IP address is 10.10.10.1
Filename 'openwrt.bin'.

 TIMEOUT_COUNT=10,Load address: 0x80100000
Loading: Got ARP REPLY, set server/gtwy eth addr (3c:a8:2a:79:85:b0)
Got it
T T T T T T T T T T
Retry count exceeded; starting again
TFTP from server 10.10.10.3; our IP address is 10.10.10.1
Filename 'openwrt.bin'.

 TIMEOUT_COUNT=10,Load address: 0x80100000
Loading: Got ARP REPLY, set server/gtwy eth addr (3c:a8:2a:79:85:b0)
Got it
T T T T T T T T T T
Retry count exceeded; starting again
TFTP from server 10.10.10.3; our IP address is 10.10.10.1
Filename 'openwrt.bin'.

 TIMEOUT_COUNT=10,Load address: 0x80100000
Loading: Got ARP REPLY, set server/gtwy eth addr (3c:a8:2a:79:85:b0)
Got it
T T T T T T T T T T
Retry count exceeded; starting again
TFTP from server 10.10.10.3; our IP address is 10.10.10.1
Filename 'openwrt.bin'.

 TIMEOUT_COUNT=10,Load address: 0x80100000
Loading: Got ARP REPLY, set server/gtwy eth addr (3c:a8:2a:79:85:b0)
Got it
T T T T T T T T T T
Retry count exceeded; starting again
TFTP from server 10.10.10.3; our IP address is 10.10.10.1
Filename 'openwrt.bin'.

 TIMEOUT_COUNT=10,Load address: 0x80100000
Loading: Got ARP REPLY, set server/gtwy eth addr (3c:a8:2a:79:85:b0)
Got it
T T
Abort
Done!
## Booting image at bc050000 ...
   Image Name:   MIPS OpenWrt Linux-5.4.98
   Image Type:   MIPS Linux Kernel Image (lzma compressed)
   Data Size:    2518581 Bytes =  2.4 MB
   Load Address: 80001000
   Entry Point:  80001000
   Verifying Checksum ... OK
   Uncompressing Kernel Image ... LZMA ERROR 1 - must RESET board to recover

===================================================================
                MT7621   stage1 code Mar 12 2015 14:43:30 (ASIC)
                CPU=500000000 HZ BUS=125000000 HZ
==================================================================
Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x31100000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-800Mhz ===
PLL2 FB_DL: 0x0, 1/0 = 1000/24 01000000
PLL4 FB_DL: 0xe, 1/0 = 644/380 39000000
PLL3 FB_DL: 0x18, 1/0 = 604/420 61000000
do DDR setting..[01F40000]
Apply DDR2 Setting...(use customer AC)
          0    8   16   24   32   40   48   56   64   72   80   88   96  104  11  2  120
      --------------------------------------------------------------------------  ------
0000:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0001:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0002:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0003:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0004:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0005:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0006:|    0    0    0    0    0    0    0    0    0    0    0    0    0    1      1    1
0007:|    0    0    0    0    0    0    1    1    1    1    1    1    1    1      1    1
0008:|    1    1    1    1    1    1    1    1    1    1    1    1    1    0      0    0
0009:|    1    1    1    1    1    0    0    0    0    0    0    0    0    0      0    0
000A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
000B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
000C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
000D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
000E:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
000F:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0010:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0011:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0012:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0013:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0014:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0015:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0016:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0017:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0018:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
0019:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
001A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
001B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
001C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
001D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
001E:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
001F:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0      0    0
DRAMC_DQSCTL1[0e0]=1A000000
DRAMC_DQSGCTL[124]=80000000
rank 0 coarse = 8
rank 0 fine = 48
B:|    0    0    0    0    0    1    1    1    0    0    0    0    0    0    0      0
opt_dle value:6
DRAMC_DDR2CTL[07c]=40001263
DRAMC_PADCTL4[0e4]=00000005
DRAMC_DQIDLY1[210]=0B08080A
DRAMC_DQIDLY2[214]=060A0709
DRAMC_DQIDLY3[218]=08060705
DRAMC_DQIDLY4[21c]=07050706
DRAMC_R0DELDLY[018]=00002F31
==================================================================
                RX      DQS perbit delay software calibration
==================================================================
1.0-15 bit dq delay value
==================================================================
bit|     0  1  2  3  4  5  6  7  8  9
--------------------------------------
0 |    9 7 7 10 8 7 9 5 4 6
10 |    5 7 6 7 5 6
--------------------------------------

==================================================================
2.dqs window
x=pass dqs delay value (min~max)center
y=0-7bit DQ of every group
input delay:DQS0 =49 DQS1 = 47
==================================================================
bit     DQS0     bit      DQS1
0  (1~95)48  8  (1~92)46
1  (1~95)48  9  (1~92)46
2  (1~95)48  10  (1~92)46
3  (1~96)48  11  (1~91)46
4  (1~95)48  12  (1~94)47
5  (1~97)49  13  (1~93)47
6  (2~95)48  14  (1~94)47
7  (1~95)48  15  (1~92)46
==================================================================
3.dq delay value last
==================================================================
bit|    0  1  2  3  4  5  6  7  8   9
--------------------------------------
0 |    10 8 8 11 9 7 10 6 5 7
10 |    6 8 6 7 5 7
==================================================================
==================================================================
     TX  perbyte calibration
==================================================================
DQS loop = 15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqsdly_pass[0]=15,  finish count=1
dqs_perbyte_dly.last_dqsdly_pass[1]=15,  finish count=2
DQ loop=15, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqdly_pass[0]=15,  finish count=1
dqs_perbyte_dly.last_dqdly_pass[1]=15,  finish count=2
byte:0, (DQS,DQ)=(8,8)
byte:1, (DQS,DQ)=(8,8)
DRAMC_DQODLY1[200]=88888888
DRAMC_DQODLY2[204]=88888888
20,data:88
[EMI] DRAMC calibration passed

===================================================================
                MT7621   stage1 code done
                CPU=500000000 HZ BUS=125000000 HZ
===================================================================


U-Boot 1.1.3 (Jan 15 2016 - 09:47:18)

Board: Ralink APSoC DRAM:  128 MB
relocate_code Pointer at: 87fb8000

Config XHCI 40M PLL
******************************
Software System Reset Occurred
******************************
flash manufacture id: 1, device id 20 18
find flash: S25FL128P
============================================
Ralink UBoot Version: 4.3.0.0
--------------------------------------------
ASIC MT7621A DualCore (MAC to MT7530 Mode)
DRAM_CONF_FROM: Auto-Detection
DRAM_TYPE: DDR2
DRAM bus: 16 bit
Xtal Mode=3 OCP Ratio=1/4
Flash component: SPI Flash
Date:Jan 15 2016  Time:09:47:18
============================================
icache: sets:256, ways:4, linesz:32 ,total:32768
dcache: sets:256, ways:4, linesz:32 ,total:32768

 ##### The CPU freq = 880 MHZ ####
 estimate memory size =128 Mbytes
#Reset_MT7530

Please choose the operation:
   1: Load system code to SDRAM via TFTP.
   2: Load system code then write to Flash via TFTP.
   3: Boot system code via Flash (default).
   4: Entr boot command line interface.
   7: Load Boot Loader code then write to Flash via Serial.
   9: Load Boot Loader code then write to Flash via TFTP.                     0
bootcount: 4

3: System Boot system code via Flash.
Erasing SPI Flash...
.
Writing to SPI Flash...
.
done
## Booting image at bce30000 ...
Bad Magic Number,85190320