Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1

Hi,
I have this device that i want to add support for it.
i managed to extract DTB from OEM firmware, and decompiled it to DTS.

i have the boot log level7 and printenv

what i do not understand, why when i use the dts file extracted from the device - which is huge 46KB - the boot hang @ Starting kernel ...

i compiled Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1 device and the boot log looks good except for few things did not work correctly as it is different for my device.

such as flash section.
Here are 2 flash memory. 1st is spi 2MiB and second is spi-nand 128MiB as shown on the boot log.

[    0.828018] sps:BAM 0x07884000 is registered.
[    0.831413] sps:BAM 0x07884000 (va:0xd0b00000) enabled: ver:0x19, number of pipes:12
[    0.839546] m25p80 spi0.0: found gd25q16, expected n25q128a11
[    0.844805] m25p80 spi0.0: gd25q16 (2048 Kbytes)
[    0.849427] 11 gww2-spi partitions found on MTD device spi0.0
[    0.855125] Creating 11 MTD partitions on "spi0.0":
[    0.860012] 0x000000000000-0x000000040000 : "0:SBL1"
[    0.866217] 0x000000040000-0x000000060000 : "0:MIBIB"
[    0.871427] 0x000000060000-0x0000000c0000 : "0:QSEE"
[    0.876397] 0x0000000c0000-0x0000000d0000 : "0:CDT"
[    0.881306] 0x0000000d0000-0x0000000e0000 : "0:DDRPARAMS"
[    0.886729] 0x0000000e0000-0x0000000f0000 : "0:APPSBLENV"
[    0.892205] 0x0000000f0000-0x000000170000 : "0:APPSBL"
[    0.897398] 0x000000170000-0x000000180000 : "0:ART"
[    0.902386] 0x000000180000-0x000000190000 : "0:nvram"
[    0.907508] 0x000000190000-0x0000001a0000 : "0:nvram2"
[    0.912782] 0x0000001a0000-0x000000200000 : "0:free"
[    0.929816] libphy: ipq40xx_mdio: probed
[    0.936523] ipq40xx-mdio 90000.mdio: ipq40xx-mdio driver was registered
[    0.948478] nand: device found, Manufacturer ID: 0xc2, Chip ID: 0x12
[    0.953829] nand: Macronix MX35LFxGE4AB 128MiB 3.3V
[    0.958662] nand: 128MiB, SLC, page size: 2048, OOB size: 64
[    0.964342] Scanning device for bad blocks
[    1.249570] random: nonblocking pool is initialized
[    1.364138] Bad eraseblock 522 at 0x000004140000
[    1.742097] 6 gww2-nand partitions found on MTD device spi0.1
[    1.746806] Creating 6 MTD partitions on "spi0.1":
[    1.751632] 0x000003000000-0x000005000000 : "rootfs"
[    1.757746] mtd: device 11 (rootfs) set to be root filesystem
[    1.762500] 0x000000000000-0x000002000000 : "rootfs2"
[    1.768624] 0x000006100000-0x000006200000 : "NVRAM"
[    1.773608] 0x000006200000-0x000006300000 : "NVRAM2"
[    1.778632] 0x000006300000-0x000006b00000 : "PRIV_FLASH"
[    1.784066] 0x000007d00000-0x000007e00000 : "dummy"

But spi and nand sections in dts file extracted are just this>

		spi@78b5000 {
			compatible = "qcom,spi-qup-v2";
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			reg-names = "spi_physical\0spi_bam_physical";
			reg = <0x78b5000 0x600 0x7884000 0x23000>;
			interrupt-names = "spi_irq\0spi_bam_irq";
			interrupts = <0x00 0x5f 0x00 0x00 0xee 0x00>;
			spi-max-frequency = <0x16e3600>;
			clocks = <0x02 0x17 0x02 0x15>;
			clock-names = "core_clk\0iface_clk";
			qcom,infinite-mode = <0x00>;
			qcom,use-bam;
			qcom,bam-consumer-pipe-index = <0x04>;
			qcom,bam-producer-pipe-index = <0x05>;
			qcom,master-id = <0x00>;
			status = "ok";
			pinctrl-0 = <0x49>;
			pinctrl-names = "default";

			m25p80@0 {
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				compatible = "n25q128a11";
				reg = <0x00>;
				linux,modalias = "m25p80\0n25q128a11";
				spi-max-frequency = <0x16e3600>;
				use-default-sizes;
			};
		};

		spi@78b6000 {
			compatible = "qcom,spi-qup-v2";
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			reg-names = "spi_physical\0spi_bam_physical";
			reg = <0x78b6000 0x600 0x7884000 0x23000>;
			interrupt-names = "spi_irq\0spi_bam_irq";
			interrupts = <0x00 0x60 0x00 0x00 0xee 0x00>;
			spi-max-frequency = <0x16e3600>;
			clocks = <0x02 0x19 0x02 0x15>;
			clock-names = "core_clk\0iface_clk";
			qcom,infinite-mode = <0x00>;
			qcom,use-bam;
			qcom,bam-consumer-pipe-index = <0x06>;
			qcom,bam-producer-pipe-index = <0x07>;
			qcom,master-id = <0x00>;
			status = "disabled";
		};

		qcom,nand@7980000 {
			compatible = "qcom,msm-nand";
			reg = <0x7980000 0x40000 0x7984000 0x1a000>;
			reg-names = "nand_phys\0bam_phys";
			interrupts = <0x00 0x65 0x00>;
			interrupt-names = "bam_irq";
			qcom,msm-bus,name = "qpic_nand";
			qcom,msm-bus,num-cases = <0x02>;
			qcom,msm-bus,num-paths = <0x01>;
			qcom,msm-bus,vectors-KBps = <0x5b 0x200 0x00 0x00 0x5b 0x200 0x61a80 0xc3500>;
			clock-names = "iface_clk\0core_clk";
			clocks = <0x02 0x2b 0x02 0x2c>;
			status = "disabled";
		};

spi@78b6000 and qcom,nand@7980000 status is disabled. so i will ignore.

there is only mentioned one flash only m25p80@0

i do not understand why. if someone can explain please.

The device's original downstream DTB is not compatible with a modern kernel.

Have a look at the upstream DTS here:

These devices were only recently removed from OpenWrt main branch, because the patches for them were making some wrong changes, and it did not look like there were any users: https://github.com/openwrt/openwrt/commit/46ed38adeb76b376e34056c755e0c8ffa5acf29f

The downstream kernel could be adding partitions based on kernel cmdline, modules, or userspace calls, or bootloader modifying the DTS before it gets passed to kernel.


To make this DTS more suitable to your device, you can modify the DTS in the build directory after it gets prepared; make target/linux/prepare, but before it gets compiled; make target/linux/install by OpenWrt, under build_dir/target-arm_cortex-a7+neon-vfpv4_musl_eabi/linux-ipq40xx_mikrotik/linux-*/arch/arm/boot/dts/*401*dk*. To make any changes persistent between rebuilds, you would need to make a quilt patch for the target kernel: https://openwrt.org/docs/guide-developer/toolchain/use-patches-with-buildsystem#adding_or_editing_kernel_patches

You also need to be very clear what device you actually have…

AP-DK01.1-C1 would be the naked Qualcomm reference board (open PCB, no case), sold somewhere in the 4-figure range (something similar to e.g. https://web.archive.org/web/20160717181324/http://www.compex.com.sg/qca-reference-design/).

Or an actual device with case and everything from a 'normal' router manufacturer (as in, plastic router or AP, sold somewhere in the mid- to high two-figure range), where the vendor roughly based their device on the aforementioned reference board and went on with their own hardware design from there. Most vendors keep the naming and don't use their own, which can be confusing. Devices like these typically have significant differences to the original reference board and need their own bespoke DTS (and image).

The images (previously-) provided by OpenWrt are (were) for the reference board only, not for consumer devices based on it.

when i used image-qcom-ipq4019-ap.dk01.1-c1.dts decompiled from dtb file for the target.

the code is compatible and kernel boots with flash and wifi and leds and buttons issues

recently i have managed to get the nand to read by adding a node under spi for it and also adding gpio for nand in cs-gpios and pinmux_cs pinconf_cs

Here is the extracted booting dts using a build of 22.03.5

/dts-v1/;

/ {
	#address-cells = <0x01>;
	#size-cells = <0x01>;
	model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
	compatible = "qcom,ap-dk01.1-c1\0qcom,ap-dk01.2-c1";
	interrupt-parent = <0x01>;

	reserved-memory {
		#address-cells = <0x01>;
		#size-cells = <0x01>;
		ranges;

		smem@87e00000 {
			reg = <0x87e00000 0x80000>;
			no-map;
		};

		tz@87e80000 {
			reg = <0x87e80000 0x180000>;
			no-map;
		};
	};

	aliases {
		spi0 = "/soc/spi@78b5000";
		spi1 = "/soc/spi@78b6000";
		i2c0 = "/soc/i2c@78b7000";
		i2c1 = "/soc/i2c@78b8000";
		ethernet0 = "/soc/edma@c080000/gmac0";
		ethernet1 = "/soc/edma@c080000/gmac1";
		serial0 = "/soc/serial@78af000";
	};

	cpus {
		#address-cells = <0x01>;
		#size-cells = <0x00>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <0x02>;
			qcom,acc = <0x03>;
			qcom,saw = <0x04>;
			reg = <0x00>;
			clocks = <0x05 0x09>;
			clock-frequency = <0x00>;
			clock-latency = <0x3e800>;
			operating-points-v2 = <0x06>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <0x02>;
			qcom,acc = <0x07>;
			qcom,saw = <0x08>;
			reg = <0x01>;
			clocks = <0x05 0x09>;
			clock-frequency = <0x00>;
			clock-latency = <0x3e800>;
			operating-points-v2 = <0x06>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <0x02>;
			qcom,acc = <0x09>;
			qcom,saw = <0x0a>;
			reg = <0x02>;
			clocks = <0x05 0x09>;
			clock-frequency = <0x00>;
			clock-latency = <0x3e800>;
			operating-points-v2 = <0x06>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <0x02>;
			qcom,acc = <0x0b>;
			qcom,saw = <0x0c>;
			reg = <0x03>;
			clocks = <0x05 0x09>;
			clock-frequency = <0x00>;
			clock-latency = <0x3e800>;
			operating-points-v2 = <0x06>;
		};

		l2-cache {
			compatible = "cache";
			cache-level = <0x02>;
			qcom,saw = <0x0d>;
			phandle = <0x02>;
		};
	};

	opp_table0 {
		compatible = "operating-points-v2";
		opp-shared;
		phandle = <0x06>;

		opp-48000000 {
			opp-hz = <0x00 0x2dc6c00>;
			clock-latency-ns = <0x3e800>;
		};

		opp-200000000 {
			opp-hz = <0x00 0xbebc200>;
			clock-latency-ns = <0x3e800>;
		};

		opp-500000000 {
			opp-hz = <0x00 0x1dcd6500>;
			clock-latency-ns = <0x3e800>;
		};

		opp-716000000 {
			opp-hz = <0x00 0x2aad4b00>;
			clock-latency-ns = <0x3e800>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x80000000 0x10000000>;
	};

	pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <0x01 0x07 0xf04>;
	};

	clocks {

		sleep_clk {
			compatible = "fixed-clock";
			clock-frequency = <0x7d00>;
			clock-output-names = "gcc_sleep_clk_src";
			#clock-cells = <0x00>;
			phandle = <0x13>;
		};

		xo {
			compatible = "fixed-clock";
			clock-frequency = <0x2dc6c00>;
			#clock-cells = <0x00>;
		};
	};

	firmware {

		scm {
			compatible = "qcom,scm-ipq4019";
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <0x01 0x02 0xf08 0x01 0x03 0xf08 0x01 0x04 0xf08 0x01 0x01 0xf08>;
		clock-frequency = <0x2dc6c00>;
		always-on;
	};

	soc {
		#address-cells = <0x01>;
		#size-cells = <0x01>;
		ranges;
		compatible = "simple-bus";

		interrupt-controller@b000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <0x03>;
			reg = <0xb000000 0x1000 0xb002000 0x1000>;
			phandle = <0x01>;
		};

		clock-controller@1800000 {
			compatible = "qcom,gcc-ipq4019";
			#clock-cells = <0x01>;
			#reset-cells = <0x01>;
			reg = <0x1800000 0x60000>;
			phandle = <0x05>;
		};

		rng@22000 {
			compatible = "qcom,prng";
			reg = <0x22000 0x140>;
			clocks = <0x05 0x2b>;
			clock-names = "core";
			status = "ok";
		};

		pinctrl@1000000 {
			compatible = "qcom,ipq4019-pinctrl";
			reg = <0x1000000 0x300000>;
			gpio-controller;
			gpio-ranges = <0x0e 0x00 0x00 0x64>;
			#gpio-cells = <0x02>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			interrupts = <0x00 0xd0 0x04>;
			phandle = <0x0e>;

			serial_pinmux {
				phandle = <0x12>;

				mux {
					pins = "gpio60\0gpio61";
					function = "blsp_uart0";
					bias-disable;
				};
			};

			spi_0_pinmux {
				phandle = <0x10>;

				pinmux {
					function = "blsp_spi0";
					pins = "gpio55\0gpio56\0gpio57";
				};

				pinmux_cs {
					function = "gpio";
					pins = "gpio54";
				};

				pinconf {
					pins = "gpio55\0gpio56\0gpio57";
					drive-strength = <0x0c>;
					bias-disable;
				};

				pinconf_cs {
					pins = "gpio54";
					drive-strength = <0x02>;
					bias-disable;
					output-high;
				};
			};
		};

		regulator@1948000 {
			compatible = "qcom,vqmmc-ipq4019-regulator";
			reg = <0x1948000 0x04>;
			regulator-name = "vqmmc";
			regulator-min-microvolt = <0x16e360>;
			regulator-max-microvolt = <0x2dc6c0>;
			regulator-always-on;
			status = "disabled";
		};

		sdhci@7824900 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0x7824900 0x11c 0x7824000 0x800>;
			interrupts = <0x00 0x7b 0x04 0x00 0x8a 0x04>;
			interrupt-names = "hc_irq\0pwr_irq";
			bus-width = <0x08>;
			clocks = <0x05 0x2f 0x05 0x2e 0x05 0x1c>;
			clock-names = "core\0iface\0xo";
			status = "disabled";
		};

		dma@7884000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x7884000 0x23000>;
			interrupts = <0x00 0xee 0x04>;
			clocks = <0x05 0x15>;
			clock-names = "bam_clk";
			#dma-cells = <0x01>;
			qcom,ee = <0x00>;
			status = "ok";
			phandle = <0x0f>;
		};

		spi@78b5000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x78b5000 0x600>;
			interrupts = <0x00 0x5f 0x04>;
			clocks = <0x05 0x17 0x05 0x15>;
			clock-names = "core\0iface";
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			dmas = <0x0f 0x05 0x0f 0x04>;
			dma-names = "rx\0tx";
			status = "ok";
			pinctrl-0 = <0x10>;
			pinctrl-names = "default";
			cs-gpios = <0x0e 0x36 0x00>;

			mx25l25635f@0 {
				compatible = "mx25l25635f\0jedec,spi-nor";
				#address-cells = <0x01>;
				#size-cells = <0x01>;
				reg = <0x00>;
				spi-max-frequency = <0x16e3600>;

				SBL1@0 {
					label = "SBL1";
					reg = <0x00 0x40000>;
					read-only;
				};

				MIBIB@40000 {
					label = "MIBIB";
					reg = <0x40000 0x20000>;
					read-only;
				};

				QSEE@60000 {
					label = "QSEE";
					reg = <0x60000 0x60000>;
					read-only;
				};

				CDT@c0000 {
					label = "CDT";
					reg = <0xc0000 0x10000>;
					read-only;
				};

				DDRPARAMS@d0000 {
					label = "DDRPARAMS";
					reg = <0xd0000 0x10000>;
					read-only;
				};

				APPSBLENV@e0000 {
					label = "APPSBLENV";
					reg = <0xe0000 0x10000>;
					read-only;
				};

				APPSBL@f0000 {
					label = "APPSBL";
					reg = <0xf0000 0x80000>;
					read-only;
				};

				ART@170000 {
					label = "ART";
					reg = <0x170000 0x10000>;
					read-only;
				};

				kernel@180000 {
					label = "kernel";
					reg = <0x180000 0x400000>;
				};

				rootfs@580000 {
					label = "rootfs";
					reg = <0x580000 0x1600000>;
				};

				firmware@180000 {
					label = "firmware";
					reg = <0x180000 0x1a00000>;
				};
			};
		};

		spi@78b6000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x78b6000 0x600>;
			interrupts = <0x00 0x60 0x04>;
			clocks = <0x05 0x19 0x05 0x15>;
			clock-names = "core\0iface";
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			dmas = <0x0f 0x07 0x0f 0x06>;
			dma-names = "rx\0tx";
			status = "disabled";
		};

		i2c@78b7000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x78b7000 0x600>;
			interrupts = <0x00 0x61 0x04>;
			clocks = <0x05 0x15 0x05 0x16>;
			clock-names = "iface\0core";
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			dmas = <0x0f 0x09 0x0f 0x08>;
			dma-names = "rx\0tx";
			status = "disabled";
		};

		i2c@78b8000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x78b8000 0x600>;
			interrupts = <0x00 0x62 0x04>;
			clocks = <0x05 0x15 0x05 0x18>;
			clock-names = "iface\0core";
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			dmas = <0x0f 0x0b 0x0f 0x0a>;
			dma-names = "rx\0tx";
			status = "disabled";
		};

		dma@8e04000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x8e04000 0x20000>;
			interrupts = <0x00 0xcf 0x04>;
			clocks = <0x05 0x21>;
			clock-names = "bam_clk";
			#dma-cells = <0x01>;
			qcom,ee = <0x01>;
			qcom,controlled-remotely;
			status = "ok";
			phandle = <0x11>;
		};

		crypto@8e3a000 {
			compatible = "qcom,crypto-v5.1";
			reg = <0x8e3a000 0x6000>;
			clocks = <0x05 0x21 0x05 0x22 0x05 0x23>;
			clock-names = "iface\0bus\0core";
			dmas = <0x11 0x02 0x11 0x03>;
			dma-names = "rx\0tx";
			status = "ok";
		};

		clock-controller@b088000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xb088000 0x1000 0xb008000 0x1000>;
			phandle = <0x03>;
		};

		clock-controller@b098000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xb098000 0x1000 0xb008000 0x1000>;
			phandle = <0x07>;
		};

		clock-controller@b0a8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xb0a8000 0x1000 0xb008000 0x1000>;
			phandle = <0x09>;
		};

		clock-controller@b0b8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xb0b8000 0x1000 0xb008000 0x1000>;
			phandle = <0x0b>;
		};

		regulator@b089000 {
			compatible = "qcom,saw2";
			reg = <0xb089000 0x1000 0xb009000 0x1000>;
			regulator;
			phandle = <0x04>;
		};

		regulator@b099000 {
			compatible = "qcom,saw2";
			reg = <0xb099000 0x1000 0xb009000 0x1000>;
			regulator;
			phandle = <0x08>;
		};

		regulator@b0a9000 {
			compatible = "qcom,saw2";
			reg = <0xb0a9000 0x1000 0xb009000 0x1000>;
			regulator;
			phandle = <0x0a>;
		};

		regulator@b0b9000 {
			compatible = "qcom,saw2";
			reg = <0xb0b9000 0x1000 0xb009000 0x1000>;
			regulator;
			phandle = <0x0c>;
		};

		regulator@b012000 {
			compatible = "qcom,saw2";
			reg = <0xb012000 0x1000>;
			regulator;
			phandle = <0x0d>;
		};

		serial@78af000 {
			compatible = "qcom,msm-uartdm-v1.4\0qcom,msm-uartdm";
			reg = <0x78af000 0x200>;
			interrupts = <0x00 0x6b 0x04>;
			status = "ok";
			clocks = <0x05 0x1a 0x05 0x15>;
			clock-names = "core\0iface";
			dmas = <0x0f 0x01 0x0f 0x00>;
			dma-names = "rx\0tx";
			pinctrl-0 = <0x12>;
			pinctrl-names = "default";
		};

		serial@78b0000 {
			compatible = "qcom,msm-uartdm-v1.4\0qcom,msm-uartdm";
			reg = <0x78b0000 0x200>;
			interrupts = <0x00 0x6c 0x04>;
			status = "disabled";
			clocks = <0x05 0x1b 0x05 0x15>;
			clock-names = "core\0iface";
			dmas = <0x0f 0x03 0x0f 0x02>;
			dma-names = "rx\0tx";
		};

		watchdog@b017000 {
			compatible = "qcom,kpss-wdt\0qcom,kpss-wdt-ipq4019";
			reg = <0xb017000 0x40>;
			clocks = <0x13>;
			timeout-sec = <0x0a>;
			status = "ok";
		};

		restart@4ab000 {
			compatible = "qcom,pshold";
			reg = <0x4ab000 0x04>;
		};

		pci@40000000 {
			compatible = "qcom,pcie-ipq4019\0snps,dw-pcie";
			reg = <0x40000000 0xf1d 0x40000f20 0xa8 0x80000 0x2000 0x40100000 0x1000>;
			reg-names = "dbi\0elbi\0parf\0config";
			device_type = "pci";
			linux,pci-domain = <0x00>;
			bus-range = <0x00 0xff>;
			num-lanes = <0x01>;
			#address-cells = <0x03>;
			#size-cells = <0x02>;
			ranges = <0x81000000 0x00 0x40200000 0x40200000 0x00 0x100000 0x82000000 0x00 0x40300000 0x40300000 0x00 0xd00000>;
			interrupts = <0x00 0x8d 0x04>;
			interrupt-names = "msi";
			#interrupt-cells = <0x01>;
			interrupt-map-mask = <0x00 0x00 0x00 0x07>;
			interrupt-map = <0x00 0x00 0x00 0x01 0x01 0x00 0x8e 0x04 0x00 0x00 0x00 0x02 0x01 0x00 0x8f 0x04 0x00 0x00 0x00 0x03 0x01 0x00 0x90 0x04 0x00 0x00 0x00 0x04 0x01 0x00 0x91 0x04>;
			clocks = <0x05 0x27 0x05 0x28 0x05 0x29>;
			clock-names = "aux\0master_bus\0slave_bus";
			resets = <0x05 0x1c 0x05 0x1b 0x05 0x1a 0x05 0x19 0x05 0x18 0x05 0x17 0x05 0x16 0x05 0x15 0x05 0x14 0x05 0x13 0x05 0x12 0x05 0x11>;
			reset-names = "axi_m\0axi_s\0pipe\0axi_m_vmid\0axi_s_xpu\0parf\0phy\0axi_m_sticky\0pipe_sticky\0pwr\0ahb\0phy_ahb";
			status = "disabled";
		};

		dma@7984000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x7984000 0x1a000>;
			interrupts = <0x00 0x65 0x04>;
			clocks = <0x05 0x2d>;
			clock-names = "bam_clk";
			#dma-cells = <0x01>;
			qcom,ee = <0x00>;
			status = "disabled";
			phandle = <0x14>;
		};

		qpic-nand@79b0000 {
			compatible = "qcom,ipq4019-nand";
			reg = <0x79b0000 0x1000>;
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			clocks = <0x05 0x2d 0x05 0x2c>;
			clock-names = "core\0aon";
			dmas = <0x14 0x00 0x14 0x01 0x14 0x02>;
			dma-names = "tx\0rx\0cmd";
			status = "disabled";

			nand@0 {
				reg = <0x00>;
				nand-ecc-strength = <0x04>;
				nand-ecc-step-size = <0x200>;
				nand-bus-width = <0x08>;
			};
		};

		wifi@a000000 {
			compatible = "qcom,ipq4019-wifi";
			reg = <0xa000000 0x200000>;
			resets = <0x05 0x00 0x05 0x01 0x05 0x02 0x05 0x03 0x05 0x04 0x05 0x05>;
			reset-names = "wifi_cpu_init\0wifi_radio_srif\0wifi_radio_warm\0wifi_radio_cold\0wifi_core_warm\0wifi_core_cold";
			clocks = <0x05 0x3b 0x05 0x3c 0x05 0x3d>;
			clock-names = "wifi_wcss_cmd\0wifi_wcss_ref\0wifi_wcss_rtc";
			interrupts = <0x00 0x20 0x01 0x00 0x21 0x01 0x00 0x22 0x01 0x00 0x23 0x01 0x00 0x24 0x01 0x00 0x25 0x01 0x00 0x26 0x01 0x00 0x27 0x01 0x00 0x28 0x01 0x00 0x29 0x01 0x00 0x2a 0x01 0x00 0x2b 0x01 0x00 0x2c 0x01 0x00 0x2d 0x01 0x00 0x2e 0x01 0x00 0x2f 0x01 0x00 0xa8 0x04>;
			interrupt-names = "msi0\0msi1\0msi2\0msi3\0msi4\0msi5\0msi6\0msi7\0msi8\0msi9\0msi10\0msi11\0msi12\0msi13\0msi14\0msi15\0legacy";
			status = "ok";
		};

		wifi@a800000 {
			compatible = "qcom,ipq4019-wifi";
			reg = <0xa800000 0x200000>;
			resets = <0x05 0x06 0x05 0x07 0x05 0x08 0x05 0x09 0x05 0x0a 0x05 0x0b>;
			reset-names = "wifi_cpu_init\0wifi_radio_srif\0wifi_radio_warm\0wifi_radio_cold\0wifi_core_warm\0wifi_core_cold";
			clocks = <0x05 0x3e 0x05 0x3f 0x05 0x40>;
			clock-names = "wifi_wcss_cmd\0wifi_wcss_ref\0wifi_wcss_rtc";
			interrupts = <0x00 0x30 0x01 0x00 0x31 0x01 0x00 0x32 0x01 0x00 0x33 0x01 0x00 0x34 0x01 0x00 0x35 0x01 0x00 0x36 0x01 0x00 0x37 0x01 0x00 0x38 0x01 0x00 0x39 0x01 0x00 0x3a 0x01 0x00 0x3b 0x01 0x00 0x3c 0x01 0x00 0x3d 0x01 0x00 0x3e 0x01 0x00 0x3f 0x01 0x00 0xa9 0x04>;
			interrupt-names = "msi0\0msi1\0msi2\0msi3\0msi4\0msi5\0msi6\0msi7\0msi8\0msi9\0msi10\0msi11\0msi12\0msi13\0msi14\0msi15\0legacy";
			status = "ok";
		};

		mdio@90000 {
			#address-cells = <0x01>;
			#size-cells = <0x00>;
			compatible = "qcom,ipq4019-mdio";
			reg = <0x90000 0x64>;
			status = "okay";

			ethernet-phy@0 {
				reg = <0x00>;
				qcom,control-dac = <0x05>;
			};

			ethernet-phy@1 {
				reg = <0x01>;
				qcom,control-dac = <0x05>;
			};

			ethernet-phy@2 {
				reg = <0x02>;
				qcom,control-dac = <0x05>;
			};

			ethernet-phy@3 {
				reg = <0x03>;
				qcom,control-dac = <0x05>;
			};

			ethernet-phy@4 {
				reg = <0x04>;
				qcom,control-dac = <0x05>;
			};

			psgmii-phy@5 {
				reg = <0x05>;
				qcom,tx-driver-strength = <0x08>;
				qcom,psgmii-az;
			};
		};

		ess-switch@c000000 {
			compatible = "qcom,ess-switch";
			reg = <0xc000000 0x80000>;
			switch_access_mode = "local bus";
			resets = <0x05 0x1d>;
			reset-names = "ess_rst";
			clocks = <0x05 0x24>;
			clock-names = "ess_clk";
			switch_cpu_bmp = <0x01>;
			switch_lan_bmp = <0x1e>;
			switch_wan_bmp = <0x20>;
			switch_mac_mode = <0x00>;
			switch_initvlas = <0x7c 0x54>;
			status = "okay";
		};

		ess-psgmii@98000 {
			compatible = "qcom,ess-psgmii";
			reg = <0x98000 0x800>;
			psgmii_access_mode = "local bus";
			status = "okay";
		};

		edma@c080000 {
			compatible = "qcom,ess-edma";
			reg = <0xc080000 0x8000>;
			qcom,page-mode = <0x00>;
			qcom,rx_head_buf_size = <0x604>;
			qcom,mdio_supported;
			qcom,poll_required = <0x01>;
			qcom,num_gmac = <0x02>;
			interrupts = <0x00 0x41 0x01 0x00 0x42 0x01 0x00 0x43 0x01 0x00 0x44 0x01 0x00 0x45 0x01 0x00 0x46 0x01 0x00 0x47 0x01 0x00 0x48 0x01 0x00 0x49 0x01 0x00 0x4a 0x01 0x00 0x4b 0x01 0x00 0x4c 0x01 0x00 0x4d 0x01 0x00 0x4e 0x01 0x00 0x4f 0x01 0x00 0x50 0x01 0x00 0xf0 0x01 0x00 0xf1 0x01 0x00 0xf2 0x01 0x00 0xf3 0x01 0x00 0xf4 0x01 0x00 0xf5 0x01 0x00 0xf6 0x01 0x00 0xf7 0x01 0x00 0xf8 0x01 0x00 0xf9 0x01 0x00 0xfa 0x01 0x00 0xfb 0x01 0x00 0xfc 0x01 0x00 0xfd 0x01 0x00 0xfe 0x01 0x00 0xff 0x01>;
			status = "okay";

			gmac0 {
				local-mac-address = [00 00 00 00 00 00];
				vlan_tag = <0x01 0x1f>;
			};

			gmac1 {
				local-mac-address = [00 00 00 00 00 00];
				qcom,phy_mdio_addr = <0x04>;
				qcom,poll_required = <0x01>;
				qcom,forced_speed = <0x3e8>;
				qcom,forced_duplex = <0x01>;
				vlan_tag = <0x02 0x20>;
			};
		};

		ssphy@9a000 {
			compatible = "qcom,usb-ss-ipq4019-phy";
			#phy-cells = <0x00>;
			reg = <0x9a000 0x800>;
			reg-names = "phy_base";
			resets = <0x05 0x0c>;
			reset-names = "por_rst";
			status = "okay";
			phandle = <0x16>;
		};

		hsphy@a6000 {
			compatible = "qcom,usb-hs-ipq4019-phy";
			#phy-cells = <0x00>;
			reg = <0xa6000 0x40>;
			reg-names = "phy_base";
			resets = <0x05 0x0d 0x05 0x0e>;
			reset-names = "por_rst\0srif_rst";
			status = "okay";
			phandle = <0x15>;
		};

		usb3@8af8800 {
			compatible = "qcom,dwc3";
			reg = <0x8af8800 0x100>;
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			clocks = <0x05 0x38 0x05 0x39 0x05 0x3a>;
			clock-names = "master\0sleep\0mock_utmi";
			ranges;
			status = "okay";

			dwc3@8a00000 {
				compatible = "snps,dwc3";
				reg = <0x8a00000 0xf8000>;
				interrupts = <0x00 0x84 0x04>;
				phys = <0x15 0x16>;
				phy-names = "usb2-phy\0usb3-phy";
				dr_mode = "host";
			};
		};

		hsphy@a8000 {
			compatible = "qcom,usb-hs-ipq4019-phy";
			#phy-cells = <0x00>;
			reg = <0xa8000 0x40>;
			reg-names = "phy_base";
			resets = <0x05 0x0f 0x05 0x10>;
			reset-names = "por_rst\0srif_rst";
			status = "okay";
			phandle = <0x17>;
		};

		usb2@60f8800 {
			compatible = "qcom,dwc3";
			reg = <0x60f8800 0x100>;
			#address-cells = <0x01>;
			#size-cells = <0x01>;
			clocks = <0x05 0x35 0x05 0x36 0x05 0x37>;
			clock-names = "master\0sleep\0mock_utmi";
			ranges;
			status = "okay";

			dwc3@6000000 {
				compatible = "snps,dwc3";
				reg = <0x6000000 0xf8000>;
				interrupts = <0x00 0x88 0x04>;
				phys = <0x17>;
				phy-names = "usb2-phy";
				dr_mode = "host";
			};
		};

		tcsr@194b000 {
			compatible = "qcom,tcsr";
			reg = <0x194b000 0x100>;
			qcom,usb-hsphy-mode-select = <0xe700e7>;
			status = "okay";
		};

		ess_tcsr@1953000 {
			compatible = "qcom,tcsr";
			reg = <0x1953000 0x1000>;
			qcom,ess-interface-select = <0x00>;
		};

		tcsr@1949000 {
			compatible = "qcom,tcsr";
			reg = <0x1949000 0x100>;
			qcom,wifi_glb_cfg = <0x41000000>;
		};

		tcsr@1957000 {
			compatible = "qcom,tcsr";
			reg = <0x1957000 0x100>;
			qcom,wifi_noc_memtype_m0_m2 = <0x2222222>;
		};
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

you mean this >

bootargs=bootpart=2 base_mac=01:07:89:7D:5E:01 boot_info=1 ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs rootwait loglevel=7

thanks

it is a device belongs to a Telecom Company runs Sealed firmware.
i am trying to add support for it so it could be reused after salvage.

so it has a model and every thing.

you are exactly right

that's what i am trying to do .

i managed to get initial read for nand

[    0.995802] spi-nand spi0.1: Macronix SPI NAND was found.
[    0.996448] spi-nand spi0.1: 128 MiB, block size: 128 KiB, page size: 2048, OOB size: 64

still much to go.

thanks