[QCA8072] cannot initialize ess-switch

[flipy]

Hello,
I'm working with a IPQ4019 Linksys WHW03 V2 device that has a QCA8072 switch chip.

I cannot get the ess-switch or the ethernet interfaces to work.

Relevant boot log message
ar40xx c000000.ess-switch: Probe failed - Missing PHYs!

As a note, PHY register addresses were different than the ones provided by patch 701-dts-ipq4019-add-mdio-node.patch and gmac1 attributes caused errors due to not being able to find PHY4 as defined in qcom,phy_mdio_addr = <4>.

From U-Boot, this are the PHYs available:

PHY 0x18: OUI = 0x1374, Model = 0x0B, Rev = 0x02,  10baseT, HDX
PHY 0x19: OUI = 0x1374, Model = 0x0B, Rev = 0x02,  10baseT, HDX
PHY 0x1A: OUI = 0x1374, Model = 0x0B, Rev = 0x02,  10baseT, HDX
PHY 0x1B: OUI = 0x1374, Model = 0x0B, Rev = 0x02,  10baseT, HDX
PHY 0x1C: OUI = 0x1374, Model = 0x0B, Rev = 0x02, 100baseT, FDX
PHY 0x1D: OUI = 0x1A082, Model = 0x00, Rev = 0x05,  10baseT, HDX

But the numbering shown when using PHYs directly from U-Boot is different:

eth0 PHY0 Down Speed :10 Half duplex
eth0 PHY1 Down Speed :10 Half duplex
eth0 PHY2 Down Speed :10 Half duplex
eth0 PHY3 up Speed :1000 Full duplex
eth0 PHY4 Down Speed :10 Half duplex

This is the initial U-Boot ethernet initialization:

Net:   MAC0 addr:30:23:3:33:18:70
PHY ID1: 0x4d
PHY ID2: 0xd0b2
ipq40xx_ess_sw_init done
eth0

Full boot log here -- also have the FDT from OEM if it helps.

DTS file

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

/*
 * Device Tree Source for Linksys WHW03 V2 (Velop)
 *
 * Copyright (C) 2020 Andreas Calvo <flipy.bcn@gmail.com>
 *
 */

/dts-v1/;

#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>

/ {
	model = "Linksys WHW03 V2 (Velop)";
	compatible = "linksys,whw03v2", "qcom,ipq4019";

	aliases {
		led-boot = &led_blue;
		led-failsafe = &led_red;
		led-running = &led_green;
		led-upgrade = &led_red;
	};


	keys {
		compatible = "gpio-keys";

		button@1 {
			label = "wps";
			linux,code = <KEY_WPS_BUTTON>;
			gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
		};
	};


	//
	// OEM U-Boot provides either
	// init=/sbin/init rootfstype=ubifs ubi.mtd=11,2048 \
	//                 root=ubi0:ubifs rootwait rw
	// or the same with ubi.mtd=13,2048
	//

	chosen {
		bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro earlyprintk";
	};


	soc {
		rng@22000 {
			status = "okay";
		};

		mdio@90000 {
			status = "okay";
		};

		ess-psgmii@98000 {
			status = "okay";
			resets = <&gcc ESS_PSGMII_ARES>;
        		reset-names = "psgmii_rst";
		};

		counter@4a1000 {
			compatible = "qcom,qca-gcnt";
			reg = <0x4a1000 0x4>;
		};


		tcsr@1949000 {
			compatible = "qcom,tcsr";
			reg = <0x1949000 0x100>;
			qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
		};

		tcsr@194b000 {
			compatible = "qcom,tcsr";
			reg = <0x194b000 0x100>;
			qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
		};

		ess_tcsr@1953000 {
			compatible = "qcom,tcsr";
			reg = <0x1953000 0x1000>;
			qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
		};

		tcsr@1957000 {
			compatible = "qcom,tcsr";
			reg = <0x1957000 0x100>;
			qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
		};

		usb2@60f8800 {
			status = "okay";
		};

		usb3@8af8800 {
			status = "okay";
		};

		crypto@8e3a000 {
			status = "okay";
		};

		watchdog@b017000 {
			status = "okay";
		};

		ess-switch@c000000 {
			status = "okay";
			resets = <&gcc ESS_RESET>, <&gcc ESS_MAC1_CLK_DIS>, \
                		<&gcc ESS_MAC2_CLK_DIS>, <&gcc ESS_MAC3_CLK_DIS>, \
                		<&gcc ESS_MAC4_CLK_DIS>, <&gcc ESS_MAC5_CLK_DIS>;
        		reset-names = "ess_rst","ess_mac1_clk_dis", \
                		"ess_mac2_clk_dis","ess_mac3_clk_dis", \
                		"ess_mac4_clk_dis", "ess_mac5_clk_dis";
		};

		edma@c080000 {
			status = "okay";
			/delete-property/ qcom,poll_required;
		};
	};
};

&tlmm {
	mdio_pins: mdio_pinmux {
		mux_1 {
			pins = "gpio6";
			function = "mdio";
			bias-pull-up;
		};
		mux_2 {
			pins = "gpio7";
			function = "mdc";
			bias-pull-up;
		};

		pin_rst {
			pins = "gpio19";
			function = "gpio";
			bias-disable;
			output-high;
		};
	};

	i2c_0_pins: i2c_0_pinmux {
		pinmux {
			function = "blsp_i2c0";
			pins = "gpio20", "gpio21";
			bias-disable;
		};
	};

	serial_0_pins: serial0_pinmux {
		pins = "gpio16", "gpio17";
		function = "blsp_uart0";
		bias-disable;
	};

	serial_1_pins: serial1_pinmux {
		pins = "gpio8", "gpio9";
		function = "blsp_uart1";
		bias-disable;
	};

	uart_1_pins: uart1_pinmux {
		mux {
			pins = "gpio8", "gpio9", "gpio10", "gpio11";
			function = "blsp_uart1";
			bias-disable;
		};
	};

	spi_0_pins: spi_0_pinmux {
		mux {
			pins = "gpio12", "gpio13", "gpio14", "gpio15";
			function = "blsp_spi0";
			bias-disable;
		};
	};
	
	spi_1_pins: spi_1_pinmux {
		mux {
			pins = "gpio44", "gpio46", "gpio47";
			function = "blsp_spi1";
			bias-disable;
		};
		host_int {
			pins = "gpio42";
			function = "gpio";
			input;
		};
		cs {
			pins = "gpio45";
			function = "gpio";
			bias-pull-up;
		};
		wake {
			pins = "gpio31";
			function = "gpio";
			output-high;
		};
	};
};

&gmac0 {
	qcom,poll_required_dynamic = <1>;
	qcom,phy_mdio_addr = <27>;
};

&gmac1 {
	qcom,poll_required_dynamic = <1>;
	qcom,phy_mdio_addr = <28>;
	///delete-property/ qcom,phy_mdio_addr;
	/delete-property/ qcom,poll_required;
	/delete-property/ qcom,forced_speed;
	/delete-property/ qcom,forced_duplex;
};

&mdio {
	status = "ok";
	pinctrl-0 = <&mdio_pins>;
	pinctrl-names = "default";
	reset-gpio = <&tlmm 19 GPIO_ACTIVE_LOW>;
};

&ethphy0 {
	#reg = <0>;
	reg = <24>;
};
&ethphy1 {
	#reg = <1>;
	reg = <25>;
};
&ethphy2 {
	#reg = <2>;
	reg = <26>;
};
&ethphy3 {
	#reg = <3>;
	reg = <27>;
};
&ethphy4 {
	#reg = <4>;
	reg = <28>;
};

&blsp_dma {
	status = "okay";
};

&blsp1_uart1 {
	status = "okay";
	pinctrl-0 = <&serial_0_pins>;
	pinctrl-names = "default";

};

&blsp1_uart2 {
	status = "okay";
	pinctrl-0 = <&serial_1_pins>;
	pinctrl-names = "default";

};

&cryptobam {
	status = "okay";
};

&nand {
	status = "okay";

	nand@0 {
		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "0:SBL1";
				reg = <0x0 0x100000>;
				read-only;
			};

			partition@100000 {
				label = "0:MIBIB";
				reg = <0x100000 0x100000>;
				read-only;
			};

			partition@200000 {
				label = "0:QSEE";
				reg = <0x200000 0x100000>;
				read-only;
			};

			partition@300000 {
				label = "0:CDT";
				reg = <0x300000 0x80000>;
				read-only;
			};

			partition@380000 {
				label = "0:APPSBL";
				reg = <0x380000 0x200000>;
				read-only;
			};

			partition@580000 {
				label = "0:ART";
				reg = <0x580000 0x80000>;
				read-only;
			};

			partition@600000 {
				label = "u_env";
				reg = <0x600000 0x80000>;
				// writable -- U-Boot environment
			};

			partition@680000 {
				label = "s_env";
				reg = <0x680000 0x40000>;
				// writable -- Boot counter records
			};

			partition@6c0000 {
				label = "devinfo";
				reg = <0x6c0000 0x40000>;
				read-only;
			};

			partition@700000 {
				label = "kernel";
				reg = <0x700000 0xa100000>;
			};

			partition@d00000 {
				label = "rootfs";
				reg = <0xd00000 0x9b00000>;
			};

			partition@a800000 {
				label = "alt_kernel";
				reg = <0xa800000 0xa100000>;
			};

			partition@ae00000 {
				label = "alt_rootfs";
				reg = <0xae00000 0x9b00000>;
			};

			partition@14900000 {
				label = "sysdiag";
				reg = <0x14900000 0x200000>;
				read-only;
			};

			partition@14b00000 {
				label = "syscfg";
				reg = <0x14b00000 0xb500000>;
				read-only;
			};
		};
	};
};

&pcie0 {
	status = "okay";

	perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
	wake-gpio = <&tlmm 40 GPIO_ACTIVE_LOW>;

	bridge@0,0 {
		reg = <0x00000000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		ranges;

		wifi2: wifi@1,0 {
			compatible = "qcom,ath10k";
			reg = <0x00010000 0 0 0 0>;
		};
	};
};

&qpic_bam {
	status = "okay";
};


&blsp1_i2c3 {
	pinctrl-0 = <&i2c_0_pins>;
	pinctrl-names = "default";

	status = "okay";

	pca9633 {
		compatible = "nxp,pca9633";
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		reg = <0x62>;
		nxp,hw-blink;
		led_red: red@0 {
			label = "whw03v2:red:power";
			reg = <0>;
		};
		led_green: green@1 {
			label = "whw03v2:green:power";
			reg = <1>;
		};
		led_blue: blue@2 {
			label = "whw03v2:blue:power";
			reg = <2>;
		};
		led_unusued: unused@3 {
			label = "whw03v2:unused:power";
			reg = <3>;
		};
	};
};

&usb2_hs_phy {
	status = "okay";
};

&usb3_hs_phy {
	status = "okay";
};

&usb3_ss_phy {
	status = "okay";
};

&wifi0 {
	status = "okay";
	qcom,ath10k-calibration-variant = "linksys-whw03v2-fcc";
};

&wifi1 {
	status = "okay";
	ieee80211-freq-limit = <5170000 5330000>;
	qcom,ath10k-calibration-variant = "linksys-whw03v2-fcc";
};

&wifi2 {
	status = "okay";
	ieee80211-freq-limit = <5490000 5835000>;
	qcom,ath10k-calibration-variant = "linksys-whw03v2-fcc";
};

I had followed a similar approach as Linksys EA8300 due to the MAC for both ethernet interfaces being the same upon boot.

UPDATE:
I think in this board access to the PHY interfaces is different.
On OEM DTS eth PHY are defined as follows:

ethernet-phy@0 {
		#reg = <0x0>;
		reg = <0x18>;
	};

Where reg points to the register address but #reg points to the chip ID.

[robimarko]

Hm, this reminds me of Mikrotiks RB450Gx4.
They use offsets to acces the PHYs instead of default addresses.

This patch may help you:

robimarko/openwrt/blob/RB450Gx4-PR-rebase/target/linux/ipq40xx/patches-5.4/715-ipq40xx-Add-MDIO-offset-support.patch

[flipy]

That fixed it.

Thanks!