Porting guide ar71xx to ath79?

Your PR has;

IMAGE/sysupgrade.bin := append-rootfs | pad-to 14528k | append-kernel | pad-to 16000k | check-size $$$$(IMAGE_SIZE)

What existing ported subtarget did you base it on?

Yuncore830 (Kuwfi 830) was ar71xx. Trying to move it to ath79

Please send me a PM when you've finished it. I'm currently adding support for Yunlink T740 which is very similar.

For the kernel after partition, is the line below the solution ?

IMAGE/sysupgrade.bin := append-rootfs | pad-to 14528k | append-kernel | pad-to 16000k | check-size $$(IMAGE_SIZE)

Where to find a proper documentation of generating the DTS file ?
Also, why such need ? The kernel shall detect the proper module to activate at boot time

fgrep qca9533 ./target/linux/ath79/dts/* | cut -d':' -f1
cat ./target/linux/ath79/image/* | grep -A10 qca9533
cat ./target/linux/ath79/image/generic.mk | grep -A5 yuncore

@anon50098793 and ?

I believe he’s saying “look at the source” as there are plenty of running examples there at this time.

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as mentioned in anotehr thread, these are not working on my device and obviously, the DTS is device specific. Just copy paste leads to non booting device

Look for differences in the mach-.c in target/linux/ar71xx/files/arch/mips/ath79/ and the mach file for a device that is supported in both ar71xx and ath79 - that will give you an idea of what DTS changes are needed.

As to "why such need" - Do some searching on Linux kernel history and why (at one point) I believe Linus stopped accepting patches for arch/arm until the transition to devicetree was implemented - because arch/arm was becoming a gigantic mess of hacked up C code

Or the TL;DR - "why such need" is because Linus Torvalds said so, you should probably trust his judgement.

I ported a device: https://github.com/neheb/source/commit/bab59e56a2940519c8437d27abe4f4d88152ad9c

Also happens to be QCA9531.

edit: Mind the GPIO numbers. Also mind the ethernet section. It probably does not match this device.

I do have the "mach-xxx.c" for that device. However, the translation in DTS does not boot

#define CF_WR650AC_KEYS_POLL_INTERVAL	20	/* msecs */



#define CF_WR650AC_GPIO_LED_24G		13
#define CF_WR650AC_GPIO_LED_58G		2
#define CF_WR650AC_GPIO_LED_WPS		20

#define CF_WR650AC_WMAC_CALDATA_OFFSET		0x1000
#define CF_WR650AC_PCIE_CALDATA_OFFSET		0x5000

#define CF_WR650AC_LAN_PHYMASK              BIT(0)
#define CF_WR650AC_WAN_PHYMASK              BIT(5)
#define CF_WR650AC_MDIO_MASK                (~(CF_WR650AC_LAN_PHYMASK | CF_WR650AC_WAN_PHYMASK))

static struct gpio_led cf_wr650ac_leds_gpio[] __initdata = {
		.name		= "comfast:blue:network",
		.active_low	= 1,
		.name		= "comfast:blue:24g",
		.gpio		= CF_WR650AC_GPIO_LED_24G,
		.active_low	= 1,
		.name		= "comfast:blue:58g",
		.gpio		= CF_WR650AC_GPIO_LED_58G,
		.active_low	= 1,
		.name		= "comfast:blue:wps",
		.gpio		= CF_WR650AC_GPIO_LED_WPS,
		.active_low	= 1,

static struct gpio_keys_button cf_wr650ac_gpio_keys[] __initdata = {
		.desc		= "Reset button/WPS button",
		.type		= EV_KEY,
		.code		= KEY_RESTART,
		.debounce_interval = CF_WR650AC_KEYS_DEBOUNCE_INTERVAL,
		.active_low	= 1,

static struct ar8327_pad_cfg cf_wr650ac_ar8327_pad0_cfg = {
	/* GMAC0 of the AR8337 switch is connected to GMAC0 via RGMII */
	.mode = AR8327_PAD_MAC_RGMII,
	.txclk_delay_en = true,
	.rxclk_delay_en = true,
	.txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
	.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,

static struct ar8327_pad_cfg cf_wr650ac_ar8327_pad6_cfg = {
	/* GMAC6 of the AR8337 switch is connected to GMAC1 via SGMII */
	.mode = AR8327_PAD_MAC_SGMII,
	.rxclk_delay_en = true,
	.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0,

static struct ar8327_platform_data cf_wr650ac_ar8327_data = {
	.pad0_cfg = &cf_wr650ac_ar8327_pad0_cfg,
	.pad6_cfg = &cf_wr650ac_ar8327_pad6_cfg,
	.port0_cfg = {
		.force_link = 1,
		.speed = AR8327_PORT_SPEED_1000,
		.duplex = 1,
		.txpause = 1,
		.rxpause = 1,
	.port6_cfg = {
		.force_link = 1,
		.speed = AR8327_PORT_SPEED_1000,
		.duplex = 1,
		.txpause = 1,
		.rxpause = 1,

static struct mdio_board_info cf_wr650ac_mdio0_info[] = {
		.bus_id = "ag71xx-mdio.0",
		.phy_addr = 0,
		.platform_data = &cf_wr650ac_ar8327_data,

static void __init cf_wr650ac_setup(void)
	u8 *art = (u8 *) KSEG1ADDR(0x1f020000);
	u8 wlan0_mac[ETH_ALEN];
	u8 wlan1_mac[ETH_ALEN];

	ath79_init_local_mac(ath79_eth0_data.mac_addr, art);
	ath79_init_mac(wlan0_mac, art, 1);
	ath79_init_mac(wlan1_mac, art, 3);
	/* Disable JTAG, enabling GPIOs 0-3 */
	/* Configure OBS4 line, for GPIO 4*/	
	ath79_gpio_function_setup(AR934X_GPIO_FUNC_JTAG_DISABLE, 0);		

	ath79_gpio_output_select(CF_WR650AC_GPIO_XWDT_TRIGGER, 0);	
	ath79_gpio_output_select(CF_WR650AC_GPIO_LED_NETWORK, 0);
	ath79_gpio_output_select(CF_WR650AC_GPIO_LED_24G, 0);
	ath79_gpio_output_select(CF_WR650AC_GPIO_LED_58G, 0);	
	ath79_gpio_output_select(CF_WR650AC_GPIO_LED_WPS, 0);

	ath79_register_leds_gpio(-1, ARRAY_SIZE(cf_wr650ac_leds_gpio),
	ath79_register_gpio_keys_polled(-1, CF_WR650AC_KEYS_POLL_INTERVAL,


	ath79_register_wmac(art + CF_WR650AC_WMAC_CALDATA_OFFSET, wlan0_mac);


	ath79_register_mdio(0, 0x0);


	/* GMAC0 is connected to the RMGII interface */
	ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
	ath79_eth0_data.phy_mask = CF_WR650AC_LAN_PHYMASK;
	ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
	ath79_eth0_pll_data.pll_1000 = 0xa6000000;

	/* GMAC1 is connected to the SGMII interface */
	ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
	ath79_eth1_data.speed = SPEED_1000;
	ath79_eth1_data.duplex = DUPLEX_FULL;
	ath79_eth1_pll_data.pll_1000 = 0x03000101;

	ap91_pci_init(art + CF_WR650AC_PCIE_CALDATA_OFFSET, wlan1_mac);


DTS file : https://github.com/openwrt/openwrt/pull/1957/files

Begging someone to port wndr4300 (nand driver? ) and dir505 (too old?) to ath79....

I can help test



v1 or v2?

If v2, should be a lot easier if/when the following is adopted. Do you know which NAND chip is in your device? It might be in the boot log.

Edit: Possibly a GigaDevice GD5F1G04UAYIG


From https://fccid.io/PY314200276/Internal-Photos/Internal-Photos-pdf-2459817.pdf

|Model|NETGEAR WNDR4300|
|Architecture|Atheros AR9344 rev 2|

[    0.629353] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xf1
[    0.635850] nand: Micron NAND 128MiB 3,3V 8-bit
[    0.640447] nand: 128 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64

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Not seeing that specific chip in the upstream driver, but with a datasheet in hand and some patience with the Linux-MTD group, it should be straightforward to support (define supported command set and their timings, page and OOB layouts, ECC return-value decoding).

OK so I'd keep waiting

Any idea about dir505?

AR9331 with 8/64 and 100 Mbps Ethernet -- Probably a matter of interest more than technical limitations.

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If I would make a bounty for devs making the porting, considering the difficulties how much would it be? Thx

That doesn't work this way. Someone who has the device will probably port it sometime.