OpenWrt support for Linksys MX8500

robimarko · 2024-03-10T16:08:40.580Z

Can you post the whole WIP DTS?

lytr · 2024-03-10T16:40:43.048Z

DTS:

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

/dts-v1/;

#include "ipq8074.dtsi"
#include "ipq8074-hk-cpu.dtsi"
#include "ipq8074-ess.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>

/ {
	model = "Linksys MX8500";
	compatible = "linksys,mx8500", "qcom,ipq8074";

	aliases {
		serial0 = &blsp1_uart5;
		serial1 = &blsp1_uart6;
		led-boot = &led_system_blue;
		led-running = &led_system_blue;
		led-failsafe = &led_system_red;
		led-upgrade = &led_system_green;
	};

	chosen {
		stdout-path = "serial0:115200n8";
		bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro";
	};

	keys {
		compatible = "gpio-keys";
		pinctrl-0 = <&button_pins>;
		pinctrl-names = "default";

		reset-button {
			label = "reset";
			gpios = <&tlmm 67 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RESTART>;
		};

		wps-button {
			label = "wps";
			gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_WPS_BUTTON>;
		};
	};

	gpio_export {
		compatible = "gpio-export";
		#size-cells = <0>;

		bt_pwr {
			gpio-export,name = "bt_pwr";
			gpio-export,output = <1>;
			gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
		};
	};
};

&tlmm {
	button_pins: button-state {
		pins = "gpio64", "gpio67";
		function = "gpio";
		drive-strength = <8>;
		bias-pull-up;
	};

	mdio_pins: mdio-state {
		mdc-pins {
			pins = "gpio68";
			function = "mdc";
			drive-strength = <8>;
			bias-pull-up;
		};

		mdio-pins {
			pins = "gpio69";
			function = "mdio";
			drive-strength = <8>;
			bias-pull-up;
		};
	};

	qpic_pins_new: qpic-pins {
		pins = "gpio1", "gpio3", "gpio4",
			"gpio5", "gpio6", "gpio7",
			"gpio8", "gpio10", "gpio11",
			"gpio12", "gpio13", "gpio14",
			"gpio15", "gpio17";
		function = "qpic";
		drive-strength = <8>;
		bias-disable;
	};
};

&blsp1_uart5 {
	status = "okay";
};

&blsp1_uart6 {
	status = "okay";
};

&prng {
	status = "okay";
};

&cryptobam {
	status = "okay";
};

&crypto {
	status = "okay";
};

&qpic_bam {
	status = "okay";
};

&qpic_nand {
	status = "okay";

	pinctrl-0 = <&qpic_pins_new>;

	nand@0 {
		reg = <0>;

		nand-ecc-strength = <4>;
		nand-ecc-step-size = <512>;
		nand-bus-width = <8>;

		partitions {
			compatible = "qcom,smem-part";

			partition-0-ethphyfw {
				compatible = "fixed-partitions";
				label = "0:ethphyfw";
				read-only;
				#address-cells = <1>;
				#size-cells = <1>;

				nvmem-layout {
					compatible = "fixed-layout";
					#address-cells = <1>;
					#size-cells = <1>;

					aqr_fw: firmware@0 {
						/* Skip the QCOM MBN Header of 40 bytes */
						reg = <0x28 0x5f82a>;
					};
				};
			};
		};
	};
};

&blsp1_i2c2 {
	status = "okay";

	led-controller@62 {
		compatible = "nxp,pca9633";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x62>;
		nxp,hw-blink;

		led_system_red: led@0 {
			reg = <0>;
			color = <LED_COLOR_ID_RED>;
			function = LED_FUNCTION_STATUS;
		};

		led_system_green: led@1 {
			reg = <1>;
			color = <LED_COLOR_ID_GREEN>;
			function = LED_FUNCTION_STATUS;
		};

		led_system_blue: led@2 {
			reg = <2>;
			color = <LED_COLOR_ID_BLUE>;
			function = LED_FUNCTION_STATUS;
		};
	};
};

&mdio {
	status = "okay";

	pinctrl-0 = <&mdio_pins>;
	pinctrl-names = "default";
	reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;

	ethernet-phy-package@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "qcom,qca8075-package";
		reg = <0>;

		qcom,package-mode = "qsgmii";

		qca8075_0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
		};

		qca8075_1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
		};

		qca8075_2: ethernet-phy@2 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <2>;
		};

		qca8075_3: ethernet-phy@3 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <3>;
		};
	};

	aqr114c: ethernet-phy@8 {
		compatible ="ethernet-phy-ieee802.3-c45";
		reg = <8>;
		reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
		firmware-name = "marvell/AQR-G4_v5.6.5-AQR_WNC_SAQA-L2_GT_ID45287_VER24005.cld";
		nvmem-cells = <&aqr_fw>;
		nvmem-cell-names = "firmware";
	};
};

&switch {
	status = "okay";

	switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>; /* lan port bitmap */
	switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
	switch_mac_mode = <MAC_MODE_QSGMII>; /* mac mode for uniphy instance0*/
	switch_mac_mode2 = <MAC_MODE_USXGMII>; /* mac mode for uniphy instance2*/

	qcom,port_phyinfo {
		port@1 {
			port_id = <1>;
			phy_address = <0>;
		};
		port@2 {
			port_id = <2>;
			phy_address = <1>;
		};
		port@3 {
			port_id = <3>;
			phy_address = <2>;
		};
		port@4 {
			port_id = <4>;
			phy_address = <3>;
		};
		port@6 {
			port_id = <6>;
			phy_address = <8>;
			compatible = "ethernet-phy-ieee802.3-c45";
			ethernet-phy-ieee802.3-c45;
		};
	};
};

&edma {
	status = "okay";
};

&dp1 {
	status = "okay";
	phy-mode = "qsgmii";
	phy-handle = <&qca8075_0>;
	label = "lan1";
};

&dp2 {
	status = "okay";
	phy-mode = "qsgmii";
	phy-handle = <&qca8075_1>;
	label = "lan2";
};

&dp3 {
	status = "okay";
	phy-mode = "qsgmii";
	phy-handle = <&qca8075_2>;
	label = "lan3";
};

&dp4 {
	status = "okay";
	phy-mode = "qsgmii";
	phy-handle = <&qca8075_3>;
	label = "lan4";
};

&dp6_syn {
	status = "okay";
	qcom,mactype = <1>;
	phy-mode = "usxgmii";
	phy-handle = <&aqr114c>;
	label = "wan";
};

&ssphy_0 {
	status = "okay";
};

&qusb_phy_0 {
	status = "okay";
};

&usb_0 {
	status = "okay";
};

&pcie_qmp0 {
	status = "okay";
};

&pcie0 {
	status = "okay";

	perst-gpio = <&tlmm 61 GPIO_ACTIVE_LOW>;

	bridge@0,0 {
		reg = <0x00000000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		ranges;

		wifi@1,0 {
			status = "okay";

			/* ath11k has no DT compatible for PCI cards */
			compatible = "pci17cb,1104";
			reg = <0x00010000 0 0 0 0>;

			qcom,ath11k-calibration-variant = "Linksys-MX8500";
		};
	};
};

&wifi {
	status = "okay";

	qcom,ath11k-calibration-variant = "Linksys-MX8500";
};

There is also this message at the beginning:

[    0.022111] OF: /soc/mdio@90000/ethernet-phy@8: could not find phandle 13

lytr · 2024-03-10T18:10:13.224Z

For now I was only able to set gpio44 high using pinctrl:

[    0.022200] OF: /soc/mdio@90000/ethernet-phy@8: could not find phandle 14
[    2.483378] OF: /soc/mdio@90000/ethernet-phy@8: could not find phandle 14
[    2.488659] Aquantia AQR114C 90000.mdio-1:08: loading firmware version 'v9.9.5 WNC SAQA-L2 082721 12:00:46' from 'FS'
[   13.930017] ssdk_phy_driver_init[371]:INFO:dev_id = 0, phy_adress = 8, phy_id = 0x31c31c22 phytype doesn't match

[  190.808205] nss-dp 3a007000.dp6-syn wan: PHY Link up speed: 1000
[  190.808285] IPv6: ADDRCONF(NETDEV_CHANGE): wan: link becomes ready
[  191.708447] uniphy autoneg time out!
[  201.207880] nss-dp 3a007000.dp6-syn wan: PHY Link is down

How to add new phy_id to the SSDK?

lytr · 2024-03-10T18:17:26.554Z

Could the problem with QCN9074 be that the regdb size inside the BDF is 7KB (like IPQ8074) and not 10KB like other BDFs for QCN9074?

robimarko · 2024-03-10T19:27:15.618Z

For SSDK, its simple like this:

GitLab

[qca-ssdk]: support AQR112C. (fef59290) · Commits · CodeLinaro / qsdk / oss /...

Change-Id: Ibebbcd2a797048e51293500aab8acee4485816b2 Signed-off-by: zhongjia

Just change the model and ID.

Also, I can reproduce the AQR reset, I think its the good old issue where you need to add a PHY ID via compatible as otherwise it cannot probe the PHY and just skips it without invoking the reset-gpios.

lytr · 2024-03-10T22:48:58.027Z

robimarko:

Also, I can reproduce the AQR reset, I think its the good old issue where you need to add a PHY ID via compatible as otherwise it cannot probe the PHY and just skips it without invoking the reset-gpios.

I tried:

	aqr114c: ethernet-phy@8 {
		compatible = "ethernet-phy-id31c3.1c22",
				"ethernet-phy-ieee802.3-c45";
		reg = <8>;
		reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
		firmware-name = "marvell/AQR-G4_v5.6.5-AQR_WNC_SAQA-L2_GT_ID45287_VER24005.cld";
		nvmem-cells = <&aqr_fw>;
		nvmem-cell-names = "firmware";
	};

and

	aqr114c: ethernet-phy@8 {
		compatible = "ethernet-phy-id0000.0000",
				"ethernet-phy-ieee802.3-c45";
		reg = <8>;
		reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
		firmware-name = "marvell/AQR-G4_v5.6.5-AQR_WNC_SAQA-L2_GT_ID45287_VER24005.cld";
		nvmem-cells = <&aqr_fw>;
		nvmem-cell-names = "firmware";
	};

but no luck.

Do you remember what caused the error for QCN9074 in the case of AX9000: OpenWrt support for Xiaomi AX9000 - #262 by robimarko ?

lytr · 2024-03-10T23:12:04.562Z

robimarko:

For SSDK, its simple like this:

https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-ssdk/-/commit/fef59290ba2b837d4f17063bdab55b22a783cb59

Just change the model and ID.

Finally port is working (using pinctrl):

[    2.498226] Aquantia AQR114C 90000.mdio-1:08: loading firmware version 'v9.9.5 WNC SAQA-L2 082721 12:00:46' from 'FS'
[   13.969704] aquantia_phy_api_ops_init[2241]:INFO:qca probe aquantia phy driver succeeded!

[  158.327799] nss-dp 3a007000.dp6-syn wan: PHY Link up speed: 1000
[  158.327879] IPv6: ADDRCONF(NETDEV_CHANGE): wan: link becomes ready

root@OpenWrt:/# ping 8.8.8.8
PING 8.8.8.8 (8.8.8.8): 56 data bytes
64 bytes from 8.8.8.8: seq=0 ttl=112 time=32.687 ms
64 bytes from 8.8.8.8: seq=1 ttl=112 time=38.285 ms

But there is no communication on QCA8075 ports...
Only link is detected.

robimarko · 2024-03-11T08:21:12.015Z

That QCN error was due to lack of regulatory DB in the BDF

lytr · 2024-03-11T08:24:46.591Z

The BDF file can be found here: https://github.com/testuser7/firmware_qca-wireless/blob/mx8500/board-linksys_mx8500.qcn9074

Is the regdb size for QCN9074 hardcoded in the code?

robimarko · 2024-03-11T12:16:09.551Z

It probably completely lacks any regulator info, that is the usual issue as size varies depending on the version that was used to generate it

lytr · 2024-03-11T13:12:08.557Z

There is regdb (starting at address 0x12df0 with size 0x1c00). This is default for the firmware WLAN.HK.2.4.0.1.
BDFs for newer firmware use regdb with size 0x2800 (starting at the same address).

georgem83 · 2024-03-11T13:23:13.517Z

I’ve encountered the same issue. Managed to get the radio to initialize after embedding the regdb from upstream in the specific BDF for the device.

IPQ5018: Potential future support for Linksys MX2000 Atlas 6 & MX5500 Atlas 6 Pro For Developers

that worked, had to extract the regdb from the upstream board-2.bin file and embed it in the stock board file using ath11k-bdencoder AND setting .supports_regdb to true. I also see the frequencies match the stock FW. Awesome and thanks for your help! Now back to troubleshooting ipq5018 wifi.

Still needs a lot of testing, but at least ath11k ‘accepts’ the regdb

lytr · 2024-03-11T18:53:52.516Z

Thanks for the tip. After preparing board data with external regdb and enabled supports_regdb radio is correctly detected.

Do I need anything special to operate the 6GHz radio:

Thu Jan  1 00:07:24 1970 daemon.err hostapd: Management frame protection is required in 6 GHz

I have wrong encryption. Radio is up now but not transmitting:

phy2-ap0  ESSID: "6g"
          Access Point: **:**:**:**:**:**
          Mode: Master  Channel: 33 (6.115 GHz)  HT Mode: HE160
          Center Channel 1: 47 2: unknown
          Tx-Power: 10 dBm  Link Quality: unknown/70
          Signal: unknown  Noise: -106 dBm
          Bit Rate: unknown
          Encryption: WPA3 SAE (CCMP)
          Type: nl80211  HW Mode(s): 802.11ax
          Hardware: 17CB:1104 17CB:1104 [Qualcomm Atheros QCN6024/9024/9074]
          TX power offset: none
          Frequency offset: none
          Supports VAPs: yes  PHY name: phy2

I have also enabled supports_regdb for IPQ8074 and prepared board data with external regdb. Radio is working. Does this mean we can use an external regdb in binary format?

robimarko · 2024-03-11T19:28:22.777Z

Yes, external regdb has been working for a while now, the issue was that QCA did not publish it publicly at all, but now we can extract it from up to date upstream BDF-s

lytr · 2024-03-11T19:30:30.573Z

Do we need to add variant to the regdb file name:

[
    {
        "board": [
            {
                "names": [
                    "bus=ahb,qmi-chip-id=0,qmi-board-id=255,variant=Linksys-MX8500"
                ],
                "data": "bus=ahb,qmi-chip-id=0,qmi-board-id=255,variant=Linksys-MX8500.bin"
            }
        ],
        "regdb": [
            {
                "names": [
                    "bus=ahb,qmi-chip-id=0,qmi-board-id=255,variant=Linksys-MX8500"
                ],
                "data": "bus=ahb,qmi-chip-id=0,qmi-board-id=255,variant=Linksys-MX8500.regdb"
            }
        ]
    }
]

?

robimarko · 2024-03-11T19:31:42.236Z

You sure it even needs to be packaged at all, simply putting the regd.bin next to board-2.bin in rootfs should work as driver is for sure attempting to load that

lytr · 2024-03-11T19:33:20.269Z

Is there a failback implemented in ath11k to the BDF internal regdb if the external regdb is not found?

robimarko · 2024-03-11T19:35:21.460Z

I think it first looks in the board-2.bin, and then if no regdb is found there tries the regd.bin binary

lytr · 2024-03-11T19:38:23.009Z

In this order:

board-2.bin: bus=ahb,qmi-chip-id=0,qmi-board-id=255,variant=Linksys-MX8500.bin (internal regdb)
board-2.bin: bus=ahb,qmi-chip-id=0,qmi-board-id=255,variant=Linksys-MX8500.regdb
regdb.bin

?

robimarko · 2024-03-11T20:21:14.776Z

Yes, from what I understand that is the priority ordering.

There are some bits in regdb.bin that supposedly allow for the internal BDF regulatory to be overriden by the external one but I have not seen that actually work