OpenWrt for Zyxel WSM20 (Multy M1) development discussion

For Developers
169

but this device have a different configuration are you sure this device is an MT7915 DBDC?

&pcie {
	status = "okay";
};

&pcie0 {
	wifi@0,0 {
		compatible = "mediatek,mt76";
		reg = <0x0000 0 0 0 0>;
		mediatek,mtd-eeprom = <&factory 0x0000>;
		mtd-mac-address = <&factory 0x4>;
	};
};

&pcie1 {
	wifi@0,0 {
		compatible = "mediatek,mt76";
		reg = <0x0000 0 0 0 0>;
		mediatek,mtd-eeprom = <&factory 0x0000>;
		mtd-mac-address = <&factory 0x4>;
	};
};

edit DTS like this

 &pcie {
          status = "okay";
   };
   
 &pcie1 {
         wifi@0,0 {
                compatible = "mediatek,mt76";
                 reg = <0x0000 0 0 0 0>;
                 mediatek,mtd-eeprom = <&factory 0x0>;
         };
 };
170

in boot i have sure this:

45] pci 0000:00:01.0: enabling device (0004 -> 0007)
[   14.319171] mt7915e 0000:02:00.0: enabling device (0000 -> 0002)
[   14.446320] mt7915e 0000:02:00.0: HW/SW Version: 0x8a108a10, Build Time: 20201105222230a
[   14.446320]
[   14.777120] mt7915e 0000:02:00.0: WM Firmware Version: ____000000, Build Time: 20201105222304
[   14.815304] mt7915e 0000:02:00.0: WA Firmware Version: DEV_000000, Build Time: 20201105222323
[   14.931892] mt7915e 0000:02:00.0: eeprom load fail, use default bin
[   14.938352] mt7915e 0000:02:00.0: Direct firmware load for mediatek/mt7915_eeprom_dbdc.bin failed with error -2
[   14.948413] mt7915e 0000:02:00.0: Falling back to sysfs fallback for: mediatek/mt7915_eeprom_dbdc.bin
[   14.976652] mt7915e: probe of 0000:02:00.0 failed with error -12
171 
14.931892] mt7915e 0000:02:00.0: eeprom load fail, use default bin
[   14.938352] mt7915e 0000:02:00.0: Direct firmware load for mediatek/mt7915_eeprom_dbdc.bin failed with error -2
[   14.948413] mt7915e 0000:02:00.0: Falling back to sysfs fallback for: mediatek/mt7915_eeprom_dbdc.bin
172

i'll try build an image tomorrow, but please flash back stock firmware first. we don't know if factory partition is ok now.

174

yes but the data is saved in factory, so if it is fu....k, than i do not think the radio will work.just try. hope it will work.

176

You might try dump factory partition to bin
cat /dev/mtd3 > /lib/firmware/mediatek/mt7915_eeprom_dbdc.bin .
I assumed mtd3 as factory firmware but might be stored elseware.

178

WIth

**great the wifi works with le dts modified **
it will remain to be seen but that is not very important
leds and buttons
for network ports
the wan does not work
lan port numbers are in wrong order

179

my dts? or ... what

this? change this as you need
<&macaddr_factory_incognita>

&switch0 {
	ports {
		port@0 {
			status = "okay";
			label = "wan";
			nvmem-cells = <&macaddr_factory_incognita>;
			nvmem-cell-names = "mac-address";
		};

		port@3 {
			status = "okay";
			label = "lan1";
		};

		port@2 {
			status = "okay";
			label = "lan2";
		};

		port@1 {
			status = "okay";
			label = "lan3";
         };
     };
};
180

for dts modified , only for the wifi running at this time

for find others infos exist sure in firmware saved ( mega.nz link )

181

@Annick we tested and working replace that i have posted

ok if that does not work, the problem for sure is not in DTS

post a sistem log or kernel log and try to connect the cable

183

LOL i wrote that because i do not have the device, replace that whit right info.
incognita= unknown

you made my night, LOL

185

I can't stop laughing, we'll see tomorrow

188

in 02_network make sure you have this under the device

ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" "wan"

DFS

189

At some point I though you got the device.

190

no, i do not have .did you get yours?

191

in fine i have found a solution with dtc ( 17.01 )

copy dtc.ipk version 17.01 to /tmp/tmp

a little hard for extract

/tmp/tmp# tar zxpvf dtc.ipk
/tmp/tmp# tar zxpvf control.tar.gz
/tmp/tmp# tar zxpvf data.tar.gz
/tmp/tmp# ./usr/bin/dtc -I fs /proc/device-tree > /tmp/tmp/dtc.txt

WSM20-OEM.dts

/dts-v1/;

/ {
	model = "MediaTek MT7621 RFB (802.11ax,NAND)";
	compatible = "mediatek,mt7621-rfb-ax-nand", "mediatek,mt7621-soc";
	#address-cells = <0x1>;
	#size-cells = <0x1>;

	gsw {
		mediatek,mdio = <0xc>;
		interrupts = <0x0 0x17 0x4>;
		mediatek,mcm;
		compatible = "mediatek,mt753x";
		mt7530,direct-phy-access;
		reset-names = "mcm";
		mediatek,portmap = "wllll";
		resets = <0x2 0x2>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		interrupt-parent = <0x5>;

		port@5 {
			reg = <0x5>;
			compatible = "mediatek,mt753x-port";
			phy-mode = "rgmii";

			fixed-link {
				full-duplex;
				speed = <0x3e8>;
			};
		};

		port@6 {
			reg = <0x6>;
			compatible = "mediatek,mt753x-port";
			phy-mode = "trgmii";

			fixed-link {
				full-duplex;
				speed = <0x3e8>;
			};
		};

		mdio-bus {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
		};
	};

	pcie@1e140000 {
		reg = <0x1e140000 0x40000>;
		interrupts = <0x0 0x4 0x4 0x0 0x18 0x4 0x0 0x19 0x4>;
		pinctrl-0 = <0xd>;
		compatible = "mediatek,mt7621-pci";
		clock-names = "pcie0", "pcie1", "pcie2";
		reset-gpios = <0xf 0x13 0x1>;
		reset-names = "pcie0", "pcie1", "pcie2";
		bus-range = <0x0 0xff>;
		device_type = "pci";
		clocks = <0xe 0x18 0xe 0x19 0xe 0x1a>;
		reset-gpio-names = "pcie0", "pcie1", "pcie2";
		ranges = <0x2000000 0x0 0x0 0x60000000 0x0 0x10000000 0x1000000 0x0 0x0 0x1e160000 0x0 0x10000>;
		resets = <0x2 0x18 0x2 0x19 0x2 0x1a>;
		status = "okay";
		#address-cells = <0x3>;
		#size-cells = <0x2>;
		pinctrl-names = "default";
		interrupt-parent = <0x5>;

		pcie0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			device_type = "pci";
			#address-cells = <0x3>;
			#size-cells = <0x2>;
		};

		pcie1 {
			reg = <0x800 0x0 0x0 0x0 0x0>;
			device_type = "pci";
			#address-cells = <0x3>;
			#size-cells = <0x2>;
		};

		pcie2 {
			reg = <0x1000 0x0 0x0 0x0 0x0>;
			device_type = "pci";
			#address-cells = <0x3>;
			#size-cells = <0x2>;
		};
	};

	cpus {

		cpu@0 {
			compatible = "mips,mips1004Kc";
		};

		cpu@1 {
			compatible = "mips,mips1004Kc";
		};
	};

	sdhci@1e130000 {
		reg = <0x1e130000 0x4000>;
		interrupts = <0x0 0x14 0x4>;
		compatible = "mediatek,mt7621-sdhci";
		status = "disabled";
		interrupt-parent = <0x5>;
	};

	usb-phy@1e1d0000 {
		reg = <0x1e1d0000 0x300>;
		compatible = "mediatek,mt7621-u3phy", "mediatek,mt2701-u3phy";
		ranges;
		status = "okay";
		#address-cells = <0x1>;
		#size-cells = <0x1>;

		usb-phy@0x1e1d0800 {
			reg = <0x1e1d0800 0x100>;
			clock-names = "ref";
			#phy-cells = <0x1>;
			clocks = <0x10>;
			phandle = <0x11>;
			linux,phandle = <0x11>;
		};

		usb-phy@0x1e1d0900 {
			reg = <0x1e1d0900 0x700>;
			clock-names = "ref";
			#phy-cells = <0x1>;
			clocks = <0x10>;
			phandle = <0x12>;
			linux,phandle = <0x12>;
		};

		usb-phy@0x1e1d1000 {
			reg = <0x1e1d1000 0x100>;
			clock-names = "ref";
			#phy-cells = <0x1>;
			clocks = <0x10>;
			phandle = <0x13>;
			linux,phandle = <0x13>;
		};
	};

	hnat@1e100000 {
		reg = <0x1e100000 0x3000>;
		mtketh-ppd = "eth0";
		mtketh-wan = "eth1";
		compatible = "mediatek,mtk-hnat_v1";
		reset-names = "mtketh";
		resets = <0xb 0x0>;
		status = "okay";
		ext-devices = "rai0", "ra0", "rai1", "ra1", "rai2", "ra2", "rai3", "ra3", "apclii0", "apcli0";
		mtketh-max-gmac = <0x2>;
	};

	rstctrl {
		#reset-cells = <0x1>;
		compatible = "ralink,rt2880-reset";
		phandle = <0x2>;
		linux,phandle = <0x2>;
	};

	sysclock50M@0 {
		#clock-cells = <0x0>;
		compatible = "fixed-clock";
		clock-frequency = <0x2faf080>;
		phandle = <0x1>;
		linux,phandle = <0x1>;
	};

	apll@0 {
		#clock-cells = <0x0>;
		compatible = "fixed-clock";
		clock-frequency = <0x1017df80>;
		phandle = <0x4>;
		linux,phandle = <0x4>;
	};

	chosen {
		bootargs = "console=ttyS0,115200n1 BootImage=1 root=/dev/mtdblock6 rootfstype=squashfs";
	};

	raeth@1e100000 {
		reg = <0x1e100000 0xe000>;
		interrupts = <0x0 0x3 0x4>;
		compatible = "mediatek,mt7621-eth";
		status = "disabled";
		mediatek,ethsys = <0xb>;
		interrupt-parent = <0x5>;
	};

	gpio-keys-polled {
		compatible = "gpio-keys-polled";
		poll-interval = <0x14>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;

		fn1 {
			gpios = <0xf 0x10 0x1>;
			label = "fn1";
			linux,code = <0x1d2>;
		};

		wps {
			gpios = <0xf 0x12 0x1>;
			label = "wps";
			linux,code = <0x211>;
		};

		reset {
			gpios = <0xf 0x6 0x1>;
			label = "reset";
			linux,code = <0x198>;
		};
	};

	gpio-leds {
		compatible = "gpio-leds";

		D1 {
			gpios = <0xf 0x3 0x1>;
			label = "D1";
			linux,default-trigger = "timer";
		};

		D2 {
			gpios = <0xf 0x4 0x1>;
			label = "D2";
		};

		D3 {
			gpios = <0xf 0x8 0x1>;
			label = "D3";
			linux,default-trigger = "timer";
		};

		D4 {
			gpios = <0xf 0x0 0x1>;
			label = "D4";
			linux,default-trigger = "timer";
		};

		D5 {
			gpios = <0xf 0xd 0x1>;
			label = "D5";
			linux,default-trigger = "timer";
		};

		D6 {
			gpios = <0xf 0x11 0x0>;
			label = "D6";
		};

		D7 {
			gpios = <0xf 0x5 0x0>;
			label = "D7";
			linux,default-trigger = "timer";
		};
	};

	palmbus@1e000000 {
		reg = <0x1e000000 0x100000>;
		compatible = "palmbus";
		ranges = <0x0 0x1e000000 0xfffff>;
		#address-cells = <0x1>;
		#size-cells = <0x1>;

		nand@3000 {
			reg = <0x3000 0x800>;
			pinctrl-0 = <0xa>;
			ecc-engine = <0x9>;
			compatible = "mediatek,mt7621-nfc";
			status = "okay";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			pinctrl-names = "default";

			flash@0 {
				reg = <0x0>;
				nand-ecc-mode = "hw";

				partitions {
					compatible = "fixed-partitions";
					#address-cells = <0x1>;
					#size-cells = <0x1>;

					All@0 {
						reg = <0x0 0x7f80000>;
						label = "All";
						read-only;
					};

					partition@7E80000 {
						reg = <0x7e80000 0x100000>;
						label = "crt";
					};

					partition@100000 {
						reg = <0x100000 0x100000>;
						label = "Ubootenv";
					};

					partition@200000 {
						reg = <0x200000 0x1c0000>;
						label = "Factory";
					};

					partition@400000 {
						reg = <0x3c0000 0x2800000>;
						label = "firmware_now";
					};

					partition@3C0000 {
						reg = <0x3c0000 0x2800000>;
						label = "RAS1";
					};

					partition@2C00000 {
						reg = <0x2bc0000 0x2800000>;
						label = "firmware";
					};

					partition@2BC0000 {
						reg = <0x2bc0000 0x2800000>;
						label = "RAS2";
					};

					partition@53C0000 {
						reg = <0x53c0000 0x100000>;
						label = "persist";
					};

					partition@0 {
						reg = <0x0 0x100000>;
						label = "Bootloader";
					};

					partition@54C0000 {
						reg = <0x54c0000 0x400000>;
						label = "rootfs_data";
					};

					partition@58C0000 {
						reg = <0x58c0000 0x25c0000>;
						label = "app";
					};
				};
			};
		};

		i2c@900 {
			reg = <0x900 0x100>;
			pinctrl-0 = <0x3>;
			compatible = "mediatek,mt7621-i2c";
			reset-names = "i2c";
			clocks = <0x1>;
			resets = <0x2 0x10>;
			status = "disabled";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			pinctrl-names = "default";
		};

		i2s@a00 {
			reg = <0xa00 0x100>;
			dmas = <0x6 0x4 0x6 0x6>;
			interrupts = <0x0 0x10 0x4>;
			txdma-req = <0x2>;
			compatible = "mediatek,mt7621-i2s";
			reset-names = "i2s";
			clocks = <0x4>;
			resets = <0x2 0x11>;
			status = "disabled";
			rxdma-req = <0x3>;
			dma-names = "tx", "rx";
			interrupt-parent = <0x5>;
		};

		spi@b00 {
			reg = <0xb00 0x100>;
			pinctrl-0 = <0x8>;
			compatible = "mediatek,mt7621-spi";
			reset-names = "spi";
			clocks = <0x7>;
			resets = <0x2 0x12>;
			status = "disabled";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			pinctrl-names = "default";
		};

		uartlite@c00 {
			reg = <0xc00 0x100>;
			interrupts = <0x0 0x1a 0x4>;
			reg-shift = <0x2>;
			no-loopback-test;
			compatible = "mediatek,mt6577-uart", "ns16550a";
			clock-frequency = <0x2faf080>;
			clocks = <0x1>;
			reg-io-width = <0x4>;
			interrupt-parent = <0x5>;
		};

		gdma@2800 {
			reg = <0x2800 0x800>;
			interrupts = <0x0 0xd 0x4>;
			compatible = "mtk,rt3883-gdma";
			reset-names = "dma";
			#dma-requests = <0x10>;
			resets = <0x2 0xe>;
			status = "disabled";
			#dma-channels = <0x10>;
			#dma-cells = <0x1>;
			phandle = <0x6>;
			linux,phandle = <0x6>;
			interrupt-parent = <0x5>;
		};

		sysc@0 {
			reg = <0x0 0x100>;
			compatible = "mtk,mt7621-sysc";
		};

		memc@5000 {
			reg = <0x5000 0x1000>;
			compatible = "mtk,mt7621-memc";
		};

		uartfull@d00 {
			reg = <0xd00 0x100>;
			interrupts = <0x0 0x1b 0x4>;
			reg-shift = <0x2>;
			no-loopback-test;
			compatible = "mediatek,mt6577-uart", "ns16550a";
			clock-frequency = <0x2faf080>;
			clocks = <0x1>;
			status = "okay";
			reg-io-width = <0x4>;
			interrupt-parent = <0x5>;
		};

		uartfull@e00 {
			reg = <0xe00 0x100>;
			interrupts = <0x0 0x1c 0x4>;
			reg-shift = <0x2>;
			no-loopback-test;
			compatible = "mediatek,mt6577-uart", "ns16550a";
			clock-frequency = <0x2faf080>;
			clocks = <0x1>;
			status = "disabled";
			reg-io-width = <0x4>;
			interrupt-parent = <0x5>;
		};

		ecc@3800 {
			reg = <0x3800 0x800>;
			compatible = "mediatek,mt7621-ecc";
			status = "okay";
			phandle = <0x9>;
			linux,phandle = <0x9>;
		};

		wdt@100 {
			reg = <0x100 0x100>;
			compatible = "mtk,mt7621-wdt";
		};

		hsdma@7000 {
			reg = <0x7000 0x1000>;
			interrupts = <0x0 0xb 0x4>;
			compatible = "mediatek,mt7621-hsdma";
			reset-names = "hsdma";
			#dma-requests = <0x1>;
			resets = <0x2 0x5>;
			status = "disabled";
			#dma-channels = <0x1>;
			#dma-cells = <0x1>;
			interrupt-parent = <0x5>;
		};

		gpio@600 {
			reg = <0x600 0x100>;
			compatible = "mtk,mt7621-gpio";
			#address-cells = <0x1>;
			#size-cells = <0x0>;

			bank@0 {
				reg = <0x0>;
				#gpio-cells = <0x2>;
				compatible = "mtk,mt7621-gpio-bank";
				phandle = <0xf>;
				gpio-controller;
				linux,phandle = <0xf>;
			};

			bank@1 {
				reg = <0x1>;
				#gpio-cells = <0x2>;
				compatible = "mtk,mt7621-gpio-bank";
				gpio-controller;
			};

			bank@2 {
				reg = <0x2>;
				#gpio-cells = <0x2>;
				compatible = "mtk,mt7621-gpio-bank";
				gpio-controller;
			};
		};
	};

	ethernet@1e100000 {
		reg = <0x1e100000 0xe000>;
		interrupts = <0x0 0x3 0x4>;
		compatible = "mediatek,mt7621-eth", "syscon";
		status = "okay";
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		mediatek,ethsys = <0xb>;
		interrupt-parent = <0x5>;

		mac@0 {
			reg = <0x0>;
			compatible = "mediatek,eth-mac";
			phy-mode = "trgmii";

			fixed-link {
				full-duplex;
				pause;
				speed = <0x3e8>;
			};
		};

		mac@1 {
			reg = <0x1>;
			compatible = "mediatek,eth-mac";
			phy-mode = "rgmii";

			fixed-link {
				full-duplex;
				pause;
				speed = <0x3e8>;
			};
		};

		mdio-bus {
			#address-cells = <0x1>;
			phandle = <0xc>;
			#size-cells = <0x0>;
			linux,phandle = <0xc>;

			ethernet-phy@1f {
				reg = <0x1f>;
				phy-mode = "rgmii";
			};
		};
	};

	sysclock125M@0 {
		#clock-cells = <0x0>;
		compatible = "fixed-clock";
		clock-frequency = <0x7735940>;
		phandle = <0x10>;
		linux,phandle = <0x10>;
	};

	aliases {
		serial0 = "/palmbus@1e000000/uartlite@c00";
	};

	interrupt-controller@1fbc0000 {
		reg = <0x1fbc0000 0x2000>;
		compatible = "mti,gic";
		mti,reserved-cpu-vectors = <0x7>;
		#interrupt-cells = <0x3>;
		phandle = <0x5>;
		interrupt-controller;
		linux,phandle = <0x5>;

		timer {
			interrupts = <0x1 0x1 0x0>;
			compatible = "mti,gic-timer";
			clocks = <0x14>;
		};
	};

	pinctrl {
		pinctrl-0 = <0x15>;
		compatible = "mtk,mtkmips-pinmux";
		pinctrl-names = "default";

		i2c {
			phandle = <0x3>;
			linux,phandle = <0x3>;

			i2c {
				mtk,function = "i2c";
				mtk,group = "i2c";
			};
		};

		spi {
			phandle = <0x8>;
			linux,phandle = <0x8>;

			spi {
				mtk,function = "spi";
				mtk,group = "spi";
			};
		};

		mdio {

			mdio {
				mtk,function = "mdio";
				mtk,group = "mdio";
			};
		};

		nand {
			phandle = <0xa>;
			linux,phandle = <0xa>;

			sdhci-nand {
				mtk,function = "nand2";
				mtk,group = "sdhci";
			};

			spi-nand {
				mtk,function = "nand1";
				mtk,group = "spi";
			};
		};

		pcie {
			phandle = <0xd>;
			linux,phandle = <0xd>;

			pcie {
				mtk,function = "gpio";
				mtk,group = "pcie";
			};
		};

		sdhci {

			sdhci {
				mtk,function = "sdhci";
				mtk,group = "sdhci";
			};
		};

		uart1 {

			uart1 {
				mtk,function = "uart1";
				mtk,group = "uart1";
			};
		};

		uart2 {

			uart2 {
				mtk,function = "uart2";
				mtk,group = "uart2";
			};
		};

		uart3 {

			uart3 {
				mtk,function = "uart3";
				mtk,group = "uart3";
			};
		};

		pinctrl0 {
			phandle = <0x15>;
			linux,phandle = <0x15>;

			gpio {
				mtk,function = "gpio";
				mtk,group = "i2c", "uart3", "jtag";
			};

			uart2 {
				mtk,function = "uart2";
				mtk,group = "uart2";
			};
		};

		rgmii1 {

			rgmii1 {
				mtk,function = "rgmii1";
				mtk,group = "rgmii1";
			};
		};

		rgmii2 {

			rgmii2 {
				mtk,function = "rgmii2";
				mtk,group = "rgmii2";
			};
		};
	};

	ethsys@1e000000 {
		reg = <0x1e000000 0x8000>;
		compatible = "mediatek,mt7621-ethsys", "syscon";
		phandle = <0xb>;
		linux,phandle = <0xb>;
	};

	usb@1e1c0000 {
		reg = <0x1e1c0000 0x1000 0x1e1d0700 0x100>;
		phys = <0x11 0x3 0x12 0x4 0x13 0x3>;
		interrupts = <0x0 0x16 0x4>;
		reg-names = "mac", "ippc";
		compatible = "mediatek,mt7621-xhci", "mediatek,mt2701-xhci";
		clock-names = "sys_ck", "free_ck", "ahb_ck", "dma_ck";
		clocks = <0x10 0x10 0x10 0x10>;
		status = "okay";
		interrupt-parent = <0x5>;
	};

	sysbusclock@0 {
		#clock-cells = <0x0>;
		compatible = "mtk,mt7621-sys-bus-clock";
		phandle = <0x7>;
		linux,phandle = <0x7>;
	};

	cpuclock@0 {
		#clock-cells = <0x0>;
		compatible = "mtk,mt7621-cpu-clock";
		phandle = <0x14>;
		linux,phandle = <0x14>;
	};

	cpuintc@0 {
		compatible = "mti,cpu-interrupt-controller";
		#interrupt-cells = <0x1>;
		#address-cells = <0x0>;
		interrupt-controller;
	};

	clkctrl {
		#clock-cells = <0x1>;
		compatible = "ralink,rt2880-clock";
		phandle = <0xe>;
		linux,phandle = <0xe>;
	};
};
1 Like
192

Finally the ZyXEL WSM20 is in da house

Now I have to step fast to see where @Annick currently is to help him out and update the Wiki for further help, because I feel everything is a little bit messed up. I've had difficulties keeping up with Annick ideas.

I currently have 6 units in the basement.

Here is some photos, now I need to see how to open this. Since @Annick is a ZyXEL engineer he knows everything straight away, but since I'm a noob on electronics I always have even a hard time to spot where the no-screw devices break apart.

image
image781×1197 46.6 KB

image
image707×1109 26.7 KB

Comparing to the photo that Annick sent

image

It feels he has ripped of the case to open it :rofl: WTF is that Blue thing? And the tape?

193

a plectrum ?

Internal photos at https://fccid.io/I88WSM20 might help with the opening,
but it looks like the lid's only using plastic latches, you need to pry it open.

194

@SirLouen the tape is there to hold the plectrum for the photo.

@Annick suggests that the weakest point is over the power button.

195

near power supply connector , a little hard to introduce the mediator

for OpenWrt i have not found other solution than to replace the bootloader.
it is a little dangerous because you must not be mistaken otherwise the box will be bricked

If someone knows how to do without changing it that would be miraculous