I was thinking the same.
In fact, I used NR7101 as a reference to build the WSM20 wiki page.
Not 100% confident but I would say that NR7101 looks like a WSM20 with a cell modem
You got running an OpenWRT build in your device, why would you be interested on creating a new build from scratch with the DTS?
Simply adapting those not working drivers would be enough I believe. Moreover knowing that this is probably just another copied device like some of the ones already supported.
well, i need help with mtd partition and the device can be added. sysupgrade is not working now.
Not sure I can help much. The similarities with the NR7101 are plenty of course, since they're both based on the MT7621. And most likely some version of the same Mediatek SDK. But based on the provided fw_printenv and /proc/mtd there isn't any evidence that the ZyXEL specific changes are similar. The NR7101 has none of those bootmenu entries, but it does have a couple of camel cased variables which are not present on the WSM20. And it has a completely different flash layout with other partition names.
And it doesn't look like the ZyXEL WAP6805 either, although that's another ZyXEL branded MT7621 device.
So I think you should look at this as a fresh new MT7621 device. Which means that it should be pretty easy to support if you only can find a way in.
As for the DTS - I don't think there are any shortcuts here. You'll have to write it yourself describing the hardware parts you see. The good news is that it's pretty simple. Just look at the examples, and make sure you get the partitions right from the start. LEDs and buttons will require some testing, but can come later. You'll probably be able to pick those up from the running OEM firmware. But if you don't it's pretty simple to just try all GPIOs. Describing the wifi interfaces is the hardest part. But it is most likely be identical to some of the existing MT7621 routers. Find one with the same wifi chips and re-use the device tree nodes.
There's really not much point in restricting the search for similarities to ZyXEL devices. Look at routers with the same wifi hardware instead.
well that should be really easy, all the same for this kind of devices.
&pcie1 {
wifi@0,0 {
compatible = "mediatek,mt76";
reg = <0x0000 0 0 0 0>;
mediatek,mtd-eeprom = <&factory 0x0>;
and the switch
&switch0 {
ports {
port@0 {
status = "okay";
label = "wan";
nvmem-cells = <&macaddr_factory_incognita>;
nvmem-cell-names = "mac-address";
};
port@3 {
status = "okay";
label = "lan1";
};
port@2 {
status = "okay";
label = "lan2";
};
port@1 {
status = "okay";
label = "lan3";
I will try to change the uboot it will be easier with that of a HUASIFEI box supported by x-wrt
with this box openwrt is also 17.01. there is an opkg
so i was able to install dtc and get the original dts
I have access to the directories with WinSCP with the console in safe mode without opkg ...
if someone could tell me how to install dtc without having opkg ...
now, that's an accident waiting to happen, hope you have a flash writer available.
ipks are just gzip:ed tar archives (picked some random package, as example)
[frollic@atlantis a]$ mv arptables-nft_1.8.7-7_mipsel_24kc.ipk arptables-nft_1.8.7-7_mipsel_24kc.gz
[frollic@atlantis a]$ tar -xvf arptables-nft_1.8.7-7_mipsel_24kc.gz
./debian-binary
./data.tar.gz
./control.tar.gz
[frollic@atlantis a]$ ls -ltr
total 12
-rw-r--r-- 1 frollic frollic 4 Aug 28 2022 debian-binary
-rw-r--r-- 1 frollic frollic 2309 Aug 28 2022 data.tar.gz
-rw-r--r-- 1 frollic frollic 604 Aug 28 2022 control.tar.gz
[frollic@atlantis a]$
This gentleman must an engineer from ZyXEL, he knows what he is doing. He has been throwing things out of the blue for the last couple of days. I have full trust on his HUASIFEI router with X-WRT 
@Annick i'm l not sure this mtd.txt inside the info you posted,where does it come from.
cat /proc/mtd
dev: size erasesize name
mtd0: 00080000 00020000 "Bootloader"
mtd1: 00040000 00020000 "Nvram"
mtd2: 00040000 00020000 "Bdata"
mtd3: 00080000 00020000 "Factory"
mtd4: 00040000 00020000 "crash"
mtd5: 00040000 00020000 "crash_log"
mtd6: 00400000 00020000 "kernel"
mtd7: 07980000 00020000 "ubi"
root@OpenWrt:/tmp#
Dude, you really need to learn how to quote properly 
Dude, you really need to learn how to quote properly
I know i suck
Lol...
Select the text in my post, wait for the quote button to appear, hovering the selected text.
Or use [quote] text [/quote] in your post.
no it's in surprice for developer folder
at my age 77 it's too late for it to improve
a with a little help I succeeded
but too many things in my brain and it gets'mixed up
You're doing just fine.
At 77, I'll probably won't even be able to wipe my own ass...
that's why I have to apologize for a lot of bullshit
you don't need to apologize if there is no disrespect.
I've never met a perfect man, that's the meaning of life
start with openwrt at this time
1 - flash with HUASIFEI bootloader
2 - flash HUASIFEI WR1800K-AX-NAND factory firmware
NO WIFI , I don't know why because I have the mt7615 mt7915e drivers
with also x-wrt firmware no wifi
let me understand you flash this firmware? can i see the DTS of this device?
if all work but not the wireless the error shoud be in factory partition, check that.
yes
1 - run with my personnal firmare WR1800K-AX-NAND
Architecture MediaTek MT7621 ver:1 eco:3
Target Platform ramips/mt7621
Firmware Version OpenWrt SNAPSHOT r18589-e821849c4f9 / LuCI Master git-22.014.56608-55dff3b
2 - run with x-wrt firmware
dts at this time
/dts-v1/;
/ {
compatible = "huasifei,wr1800k-ax-nand\0mediatek,mt7621-soc";
model = "WR1800K-AX-NAND";
#address-cells = <0x01>;
#size-cells = <0x01>;
nand@1e003000 {
compatible = "mediatek,mt7621-nfc";
clocks = <0x0c>;
reg-names = "nfi\0ecc";
clock-names = "nfi_clk";
status = "okay";
reg = <0x1e003000 0x800 0x1e003800 0x800>;
partitions {
compatible = "fixed-partitions";
#address-cells = <0x01>;
#size-cells = <0x01>;
partition@a00000 {
label = "ubi";
reg = <0x580000 0x7180000>;
};
partition@0 {
label = "Bootloader";
reg = <0x00 0x80000>;
};
partition@80000 {
label = "Config";
reg = <0x80000 0x80000>;
};
partition@100000 {
compatible = "nvmem-cells";
read-only;
#address-cells = <0x01>;
label = "factory";
#size-cells = <0x01>;
phandle = <0x19>;
reg = <0x100000 0x80000>;
macaddr@4 {
phandle = <0x1a>;
reg = <0x04 0x06>;
};
macaddr@28 {
phandle = <0x11>;
reg = <0x28 0x06>;
};
};
partition@600000 {
label = "kernel";
reg = <0x180000 0x400000>;
};
};
};
xhci@1e1c0000 {
compatible = "mediatek,mt8173-xhci";
clocks = <0x02>;
reg-names = "mac\0ippc";
clock-names = "sys_ck";
interrupt-parent = <0x01>;
#address-cells = <0x01>;
interrupts = <0x00 0x16 0x04>;
#size-cells = <0x00>;
reg = <0x1e1c0000 0x1000 0x1e1d0700 0x100>;
port@1 {
#trigger-source-cells = <0x00>;
reg = <0x01>;
};
port@2 {
#trigger-source-cells = <0x00>;
reg = <0x02>;
};
};
ethernet@1e100000 {
compatible = "mediatek,mt7621-eth";
clocks = <0x02>;
resets = <0x03 0x06 0x03 0x17>;
clock-names = "ethif";
mediatek,ethsys = <0x0d>;
interrupt-parent = <0x01>;
#address-cells = <0x01>;
interrupts = <0x00 0x03 0x04>;
#size-cells = <0x00>;
reg = <0x1e100000 0x10000>;
pinctrl-0 = <0x0e 0x0f 0x10>;
reset-names = "fe\0eth";
pinctrl-names = "default";
mdio-bus {
#address-cells = <0x01>;
#size-cells = <0x00>;
ethernet-phy@4 {
phandle = <0x12>;
reg = <0x04>;
};
switch@1f {
compatible = "mediatek,mt7621";
resets = <0x03 0x02>;
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x1f>;
reset-names = "mcm";
mediatek,mcm;
ports {
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x00>;
port@3 {
status = "okay";
label = "lan3";
reg = <0x03>;
};
port@1 {
status = "okay";
label = "lan1";
reg = <0x01>;
};
port@6 {
ethernet = <0x13>;
label = "cpu";
reg = <0x06>;
phy-mode = "rgmii";
fixed-link {
speed = <0x3e8>;
full-duplex;
};
};
port@4 {
status = "disabled";
label = "lan4";
reg = <0x04>;
};
port@2 {
status = "okay";
label = "lan2";
reg = <0x02>;
};
port@0 {
status = "disabled";
label = "lan0";
reg = <0x00>;
};
};
};
};
mac@0 {
compatible = "mediatek,eth-mac";
nvmem-cells = <0x11>;
phandle = <0x13>;
reg = <0x00>;
phy-mode = "rgmii";
nvmem-cell-names = "mac-address";
fixed-link {
speed = <0x3e8>;
pause;
full-duplex;
};
};
mac@1 {
phy-handle = <0x12>;
compatible = "mediatek,eth-mac";
mac-address-increment = <0x02>;
nvmem-cells = <0x11>;
status = "okay";
label = "wan";
reg = <0x01>;
phy-mode = "rgmii-txid";
nvmem-cell-names = "mac-address";
};
};
palmbus@1e000000 {
compatible = "palmbus";
ranges = <0x00 0x1e000000 0xfffff>;
#address-cells = <0x01>;
#size-cells = <0x01>;
reg = <0x1e000000 0x100000>;
syscon@5000 {
compatible = "mtk,mt7621-memc\0syscon";
reg = <0x5000 0x1000>;
};
wdt@100 {
compatible = "mediatek,mt7621-wdt";
reg = <0x100 0x100>;
};
systick@500 {
compatible = "ralink,mt7621-systick\0ralink,cevt-systick";
resets = <0x03 0x1c>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x05 0x04>;
reg = <0x500 0x10>;
reset-names = "intc";
};
i2c@900 {
compatible = "mediatek,mt7621-i2c";
clocks = <0x02>;
resets = <0x03 0x10>;
status = "disabled";
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0x900 0x100>;
pinctrl-0 = <0x04>;
reset-names = "i2c";
pinctrl-names = "default";
};
uartlite3@e00 {
reg-io-width = <0x04>;
compatible = "ns16550a";
status = "disabled";
interrupt-parent = <0x01>;
interrupts = <0x00 0x1c 0x04>;
reg = <0xe00 0x100>;
clock-frequency = <0x2faf080>;
pinctrl-0 = <0x07>;
reg-shift = <0x02>;
pinctrl-names = "default";
};
uartlite2@d00 {
reg-io-width = <0x04>;
compatible = "ns16550a";
status = "disabled";
interrupt-parent = <0x01>;
interrupts = <0x00 0x1b 0x04>;
reg = <0xd00 0x100>;
clock-frequency = <0x2faf080>;
pinctrl-0 = <0x06>;
reg-shift = <0x02>;
pinctrl-names = "default";
};
gpio@600 {
compatible = "mediatek,mt7621-gpio";
gpio-controller;
#interrupt-cells = <0x02>;
interrupt-parent = <0x01>;
interrupts = <0x00 0x0c 0x04>;
phandle = <0x18>;
reg = <0x600 0x100>;
#gpio-cells = <0x02>;
interrupt-controller;
};
hsdma@7000 {
#dma-cells = <0x01>;
compatible = "mediatek,mt7621-hsdma";
resets = <0x03 0x05>;
#dma-requests = <0x01>;
status = "disabled";
interrupt-parent = <0x01>;
interrupts = <0x00 0x0b 0x04>;
reg = <0x7000 0x1000>;
reset-names = "hsdma";
#dma-channels = <0x01>;
};
uartlite@c00 {
reg-io-width = <0x04>;
compatible = "ns16550a";
interrupt-parent = <0x01>;
interrupts = <0x00 0x1a 0x04>;
reg = <0xc00 0x100>;
clock-frequency = <0x2faf080>;
reg-shift = <0x02>;
no-loopback-test;
};
spi@b00 {
compatible = "ralink,mt7621-spi";
clocks = <0x08 0x01>;
resets = <0x03 0x12>;
status = "disabled";
#address-cells = <0x01>;
#size-cells = <0x00>;
reg = <0xb00 0x100>;
pinctrl-0 = <0x09>;
reset-names = "spi";
pinctrl-names = "default";
};
syscon@0 {
compatible = "mtk,mt7621-sysc\0syscon";
phandle = <0x0d>;
reg = <0x00 0x100>;
};
i2s@a00 {
compatible = "mediatek,mt7621-i2s";
clocks = <0x02>;
resets = <0x03 0x11>;
txdma-req = <0x02>;
status = "disabled";
interrupt-parent = <0x01>;
interrupts = <0x00 0x10 0x04>;
dma-names = "tx\0rx";
rxdma-req = <0x03>;
reg = <0xa00 0x100>;
dmas = <0x05 0x04 0x05 0x06>;
reset-names = "i2s";
};
gdma@2800 {
#dma-cells = <0x01>;
compatible = "ralink,rt3883-gdma";
resets = <0x03 0x0e>;
#dma-requests = <0x10>;
status = "disabled";
interrupt-parent = <0x01>;
interrupts = <0x00 0x0d 0x04>;
phandle = <0x05>;
reg = <0x2800 0x800>;
reset-names = "dma";
#dma-channels = <0x10>;
};
};
nficlock {
compatible = "fixed-clock";
#clock-cells = <0x00>;
phandle = <0x0c>;
clock-frequency = <0x7735940>;
};
sdhci@1e130000 {
compatible = "ralink,mt7620-sdhci";
status = "disabled";
interrupt-parent = <0x01>;
interrupts = <0x00 0x14 0x04>;
reg = <0x1e130000 0x4000>;
pinctrl-0 = <0x0b>;
pinctrl-names = "default";
};
sysclock {
compatible = "fixed-clock";
#clock-cells = <0x00>;
phandle = <0x02>;
clock-frequency = <0x2faf080>;
};
clkctrl {
compatible = "ralink,rt2880-clock";
#clock-cells = <0x01>;
phandle = <0x15>;
};
mc@1fbf8000 {
compatible = "mti,mips-cdmm";
reg = <0x1fbf8000 0x8000>;
};
cpuintc {
compatible = "mti,cpu-interrupt-controller";
#interrupt-cells = <0x01>;
#address-cells = <0x00>;
interrupt-controller;
};
pcie-phy@1e149000 {
compatible = "mediatek,mt7621-pci-phy";
phandle = <0x16>;
reg = <0x1e149000 0x700>;
#phy-cells = <0x01>;
};
pcie@1e140000 {
compatible = "mediatek,mt7621-pci";
clocks = <0x15 0x18 0x15 0x19 0x15 0x1a>;
resets = <0x03 0x18 0x03 0x19 0x03 0x1a>;
device_type = "pci";
clock-names = "pcie0\0pcie1\0pcie2";
phy-names = "pcie-phy0\0pcie-phy2";
ranges = <0x2000000 0x00 0x00 0x60000000 0x00 0x10000000 0x1000000 0x00 0x00 0x1e160000 0x00 0x10000>;
status = "okay";
interrupt-parent = <0x01>;
#address-cells = <0x03>;
interrupts = <0x00 0x04 0x04 0x00 0x18 0x04 0x00 0x19 0x04>;
reset-gpios = <0x18 0x13 0x01>;
#size-cells = <0x02>;
phys = <0x16 0x01 0x17 0x00>;
reg = <0x1e140000 0x100 0x1e142000 0x100 0x1e143000 0x100 0x1e144000 0x100>;
pinctrl-0 = <0x14>;
reset-names = "pcie0\0pcie1\0pcie2";
pinctrl-names = "default";
pcie@0,0 {
device_type = "pci";
ranges;
#address-cells = <0x03>;
#size-cells = <0x02>;
reg = <0x00 0x00 0x00 0x00 0x00>;
};
pcie@2,0 {
device_type = "pci";
ranges;
#address-cells = <0x03>;
#size-cells = <0x02>;
reg = <0x1000 0x00 0x00 0x00 0x00>;
};
pcie@1,0 {
device_type = "pci";
ranges;
#address-cells = <0x03>;
#size-cells = <0x02>;
reg = <0x800 0x00 0x00 0x00 0x00>;
wifi@0,0 {
compatible = "mediatek,mt76";
nvmem-cells = <0x1a>;
reg = <0x00 0x00 0x00 0x00 0x00>;
mtd-mac-address = <0x19 0x04>;
mediatek,mtd-eeprom = <0x19 0x00>;
nvmem-cell-names = "mac-address";
};
};
};
leds {
compatible = "gpio-leds";
ether {
gpios = <0x18 0x06 0x00>;
label = "ether:blue";
default-state = "on";
};
status {
gpios = <0x18 0x07 0x00>;
label = "status:red";
default-state = "off";
};
wlan {
gpios = <0x18 0x08 0x00>;
label = "wlan:green";
default-state = "off";
};
};
pll {
compatible = "mediatek,mt7621-pll\0syscon";
#clock-cells = <0x01>;
phandle = <0x08>;
clock-output-names = "cpu\0bus";
};
aliases {
led-status = "/leds/ether";
label-mac-device = "/ethernet@1e100000/mac@0";
serial0 = "/palmbus@1e000000/uartlite@c00";
};
chosen {
bootargs = "console=ttyS0,115200";
};
keys {
compatible = "gpio-keys";
wps {
gpios = <0x18 0x04 0x00>;
label = "wps";
linux,code = <0x211>;
};
reset {
gpios = <0x18 0x12 0x00>;
label = "reset";
linux,code = <0x198>;
};
};
interrupt-controller@1fbc0000 {
compatible = "mti,gic";
#interrupt-cells = <0x03>;
mti,reserved-cpu-vectors = <0x07>;
phandle = <0x01>;
reg = <0x1fbc0000 0x2000>;
interrupt-controller;
timer {
compatible = "mti,gic-timer";
clocks = <0x08 0x00>;
interrupts = <0x01 0x01 0x00>;
};
};
cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
cpu@1 {
compatible = "mips,mips1004Kc";
device_type = "cpu";
reg = <0x01>;
};
cpu@0 {
compatible = "mips,mips1004Kc";
device_type = "cpu";
reg = <0x00>;
};
};
pcie-phy@1e14a000 {
compatible = "mediatek,mt7621-pci-phy";
phandle = <0x17>;
reg = <0x1e14a000 0x700>;
#phy-cells = <0x01>;
};
rstctrl {
compatible = "ralink,rt2880-reset";
#reset-cells = <0x01>;
phandle = <0x03>;
};
cpc@1fbf0000 {
compatible = "mti,mips-cpc";
reg = <0x1fbf0000 0x8000>;
};
pinctrl {
compatible = "ralink,rt2880-pinmux";
pinctrl-0 = <0x0a>;
pinctrl-names = "default";
mdio {
phandle = <0x10>;
mdio {
groups = "mdio";
function = "mdio";
};
};
rgmii1 {
phandle = <0x0e>;
rgmii1 {
groups = "rgmii1";
function = "rgmii1";
};
};
sdhci {
phandle = <0x0b>;
sdhci {
groups = "sdhci";
function = "sdhci";
};
};
spi_pins {
phandle = <0x09>;
spi_pins {
groups = "spi";
function = "spi";
};
};
uart2 {
phandle = <0x06>;
uart2 {
groups = "uart2";
function = "uart2";
};
};
nand {
sdhci-nand {
groups = "sdhci";
function = "nand2";
};
spi-nand {
groups = "spi";
function = "nand1";
};
};
pinctrl0 {
phandle = <0x0a>;
gpio {
groups = "i2c\0uart2\0uart3";
function = "gpio";
};
};
pcie {
phandle = <0x14>;
pcie {
groups = "pcie";
function = "gpio";
};
};
rgmii2 {
phandle = <0x0f>;
rgmii2 {
groups = "rgmii2";
function = "rgmii2";
};
};
i2c_pins {
phandle = <0x04>;
i2c_pins {
groups = "i2c";
function = "i2c";
};
};
uart3 {
phandle = <0x07>;
uart3 {
groups = "uart3";
function = "uart3";
};
};
uart1 {
uart1 {
groups = "uart1";
function = "uart1";
};
};
};
};