Netgear R7800 exploration (IPQ8065, QCA9984)

For Developers
2773

Here ya go

r7500v2 # /bin/cat /sys/kernel/debug/regulator/regulator_summary && /bin/cat /sys/kernel/debug
/clk/clk_summary
 regulator                      use open bypass  opmode voltage current     min     max
---------------------------------------------------------------------------------------
 regulator-dummy                 13   13      0 unknown     0mV     0mA     0mV     0mV 
    29000000.sata-target          1                                 0mA     0mV     0mV
    29000000.sata-phy             1                                 0mA     0mV     0mV
    29000000.sata-ahci            1                                 0mA     0mV     0mV
    1b700000.pci-vdda_refclk      1                                 0mA     0mV     0mV
    1b700000.pci-vdda_phy         1                                 0mA     0mV     0mV
    1b700000.pci-vdda             1                                 0mA     0mV     0mV
    1b500000.pci-vdda_refclk      1                                 0mA     0mV     0mV
    1b500000.pci-vdda_phy         1                                 0mA     0mV     0mV
    1b500000.pci-vdda             1                                 0mA     0mV     0mV
    s1a                           1    1      0 unknown  1100mV     0mA  1050mV  1150mV 
       soc:l2-cache-l2            1                                 0mA  1100mV  1100mV
    s1b                           0    0      0 unknown  1050mV     0mA  1050mV  1150mV 
    s2a                           1    1      0 unknown  1050mV     0mA   800mV  1250mV 
       cpu0-cpu                   1                                 0mA  1045mV  1155mV
    s2b                           1    1      0 unknown  1050mV     0mA   800mV  1250mV 
       cpu1-cpu                   1                                 0mA  1045mV  1155mV
 SDCC Power                       1    0      0 unknown  3300mV     0mA  3300mV  3300mV 
                                 enable  prepare  protect                                duty
   clock                          count    count    count        rate   accuracy phase  cycle
---------------------------------------------------------------------------------------------
 qsb                                  0        0        0           1          0     0  50000
 ebi2_always_on_clk                   1        1        0           0          0     0  50000
 ebi2_clk                             1        1        0           0          0     0  50000
 pcie2_phy_clk                        0        0        0           0          0     0  50000
 pcie2_h_clk                          0        0        0           0          0     0  50000
 pcie2_aux_clk                        0        0        0           0          0     0  50000
 pcie2_a_clk                          0        0        0           0          0     0  50000
 pcie1_phy_clk                        1        1        0           0          0     0  50000
 pcie1_h_clk                          1        1        0           0          0     0  50000
 pcie1_aux_clk                        1        1        0           0          0     0  50000
 pcie1_a_clk                          1        1        0           0          0     0  50000
 sata_phy_cfg_clk                     1        1        0           0          0     0  50000
 sata_a_clk                           1        1        0           0          0     0  50000
 sata_h_clk                           1        1        0           0          0     0  50000
 gsbi7_h_clk                          0        0        0           0          0     0  50000
 gsbi6_h_clk                          0        0        0           0          0     0  50000
 gsbi5_h_clk                          0        0        0           0          0     0  50000
 gsbi4_h_clk                          4        4        0           0          0     0  50000
 gsbi2_h_clk                          0        0        0           0          0     0  50000
 gsbi1_h_clk                          0        0        0           0          0     0  50000
 usb_fs1_h_clk                        0        0        0           0          0     0  50000
 usb_hs1_h_clk                        0        0        0           0          0     0  50000
 sdc3_h_clk                           1        1        0           0          0     0  50000
 sdc1_h_clk                           1        1        0           0          0     0  50000
 pmic_ssbi2_clk                       0        0        0           0          0     0  50000
 pmic_arb1_h_clk                      0        0        0           0          0     0  50000
 pmic_arb0_h_clk                      0        0        0           0          0     0  50000
 rpm_msg_ram_h_clk                    1        1        0           0          0     0  50000
 tsif_h_clk                           0        0        0           0          0     0  50000
 dma_bam_h_clk                        0        0        0           0          0     0  50000
 pmem_clk                             0        0        0           0          0     0  50000
 sfab_sata_s_h_clk                    1        1        0           0          0     0  50000
 pcie_phy_clk                         1        1        0           0          0     0  50000
 pcie_h_clk                           1        1        0           0          0     0  50000
 pcie_aux_clk                         1        1        0           0          0     0  50000
 pcie_a_clk                           1        1        0           0          0     0  50000
 adm0_pbus_clk                        1        1        0           0          0     0  50000
 adm0_clk                             1        1        0           0          0     0  50000
 sleep_clk                            1        1        0       32768          0     0  50000
 pxo_board                            3        3        1    25000000          0     0  50000
    nss_fabric_1_a_clk                0        0        0  2147483647          0     0  50000
    nss_fabric_1_clk                  0        0        0  2147483647          0     0  50000
    nss_fabric_0_a_clk                0        0        0  2147483647          0     0  50000
    nss_fabric_0_clk                  0        0        0  2147483647          0     0  50000
    sfpb_a_clk                        0        0        0  2147483647          0     0  50000
    sfpb_clk                          0        0        0  2147483647          0     0  50000
    sfab_a_clk                        0        0        0  2147483647          0     0  50000
    sfab_clk                          0        0        0  2147483647          0     0  50000
    ebi1_a_clk                        1        1        0   400000000          0     0  50000
    ebi1_clk                          0        0        0  2147483647          0     0  50000
    daytona_a_clk                     0        0        0  2147483647          0     0  50000
    daytona_clk                       0        0        0  2147483647          0     0  50000
    cfpb_a_clk                        0        0        0  2147483647          0     0  50000
    cfpb_clk                          0        0        0  2147483647          0     0  50000
    afab_a_clk                        1        1        0   400000000          0     0  50000
    afab_clk                          0        0        0  2147483647          0     0  50000
    pxo                               6        6        3    25000000          0     0  50000
       pcie2_ref_src                  0        0        0    25000000          0     0  50000
          pcie2_ref_src_clk           0        0        0    25000000          0     0  50000
       pll18                          0        0        0   550000000          0     0  50000
          nss_tcm_src                 0        0        0   275000000          0     0  50000
             nss_tcm_clk              0        0        0   275000000          0     0  50000
          ubi32_core2_src_clk         0        0        0   550000000          0     0  50000
          ubi32_core1_src_clk         0        0        0   550000000          0     0  50000
       pll14                          0        0        0           0          0     0  50000
          pll14_vote                  0        0        0           0          0     0  50000
       hfpll_l2                       1        1        0  1000000000          0     0  50000
          krait_l2_pri_mux            2        2        0  1000000000          0     0  50000
          hfpll_l2_div                0        0        0   500000000          0     0  50000
       pll11                          0        0        0  1066000000          0     0  50000
       hfpll1                         1        1        0   800000000          0     0  50000
          krait1_pri_mux              1        1        0   800000000          0     0  50000
          hfpll1_div                  0        0        0   400000000          0     0  50000
       hfpll0                         1        1        0   800000000          0     0  50000
          krait0_pri_mux              1        1        0   800000000          0     0  50000
          hfpll0_div                  0        0        0   400000000          0     0  50000
       pll8                           1        1        1   384000000          0     0  50000
          pll8_vote                   2        2        1   384000000          0     0  50000
             usb30_utmi_clk           2        2        2    60000000          0     0  50000
                usb30_1_utmi_clk_ctl       1        1        0    60000000          0     0  50000
                usb30_0_utmi_clk_ctl       1        1        0    60000000          0     0  50000
             acpu1_aux                0        0        0   384000000          0     0  50000
                krait1_sec_mux        0        0        0   384000000          0     0  50000
             acpu_l2_aux              0        0        0   384000000          0     0  50000
                krait_l2_sec_mux       0        0        0   384000000          0     0  50000
             acpu0_aux                0        0        0   384000000          0     0  50000
                krait0_sec_mux        0        0        0   384000000          0     0  50000
             gsbi1_qup_src            0        0        0    25600000          0     0  50000
                gsbi1_qup_clk         0        0        0    25600000          0     0  50000
             gsbi4_qup_src            0        0        0    24000000          0     0  50000
                gsbi4_qup_clk         0        0        0    24000000          0     0  50000
             gsbi5_qup_src            0        0        0    48000000          0     0  50000
                gsbi5_qup_clk         0        0        0    48000000          0     0  50000
             gsbi4_uart_src           1        1        0     1843200          0     0  50000
                gsbi4_uart_clk        3        3        0     1843200          0     0  50000
             prng_src                 0        0        0    32000000          0     0  50000
                prng_clk              0        0        0    32000000          0     0  50000
       pll3                           4        4        3  1200000000          0     0  50000
          sata_ref_src                2        2        2   100000000          0     0  50000
             sata_pmalive_clk         1        1        0   100000000          0     0  50000
             sata_rxoob_clk           1        1        0   100000000          0     0  50000
          pcie1_ref_src               1        1        1   100000000          0     0  50000
             pcie1_ref_src_clk        1        1        0   100000000          0     0  50000
          pcie_ref_src                1        1        1   100000000          0     0  50000
             pcie_ref_src_clk         1        1        0   100000000          0     0  50000
          ce5_core_src                0        0        0   150000000          0     0  50000
             ce5_core_clk             0        0        0   150000000          0     0  50000
       pll0                           1        1        1   800000000          0     0  50000
          pll0_vote                   3        3        1   800000000          0     0  50000
             usb30_master_ref_src       2        2        2   125000000          0     0  50000
                usb30_1_branch_clk       2        2        0   125000000          0     0  50000
                usb30_0_branch_clk       2        2        0   125000000          0     0  50000
             ce5_h_clk_src            0        0        0   160000000          0     0  50000
                ce5_h_clk             0        0        0   160000000          0     0  50000
             ce5_a_clk_src            0        0        0   160000000          0     0  50000
                ce5_a_clk             0        0        0   160000000          0     0  50000
             gmac_core4_src           0        0        0   266666666          0     0  50000
                gmac_core4_clk        0        0        0   266666666          0     0  50000
             gmac_core3_src           1        1        0   265968586          0     0  50000
                gmac_core3_clk        1        1        0   265968586          0     0  50000
             gmac_core2_src           1        1        0   265968586          0     0  50000
                gmac_core2_clk        1        1        0   265968586          0     0  50000
             gmac_core1_src           0        0        0   266666666          0     0  50000
                gmac_core1_clk        0        0        0   266666666          0     0  50000
       gp2_src                        0        0        0    25000000          0     0  50000
          gp2_clk                     0        0        0    25000000          0     0  50000
       gp1_src                        0        0        0    25000000          0     0  50000
          gp1_clk                     0        0        0    25000000          0     0  50000
       gp0_src                        0        0        0    25000000          0     0  50000
          gp0_clk                     0        0        0    25000000          0     0  50000
       sata_phy_ref_clk               0        0        0    25000000          0     0  50000
       gsbi7_uart_src                 0        0        0    25000000          0     0  50000
          gsbi7_uart_clk              0        0        0    25000000          0     0  50000
       gsbi6_uart_src                 0        0        0    25000000          0     0  50000
          gsbi6_uart_clk              0        0        0    25000000          0     0  50000
       gsbi5_uart_src                 0        0        0    25000000          0     0  50000
          gsbi5_uart_clk              0        0        0    25000000          0     0  50000
       gsbi2_uart_src                 0        0        0    25000000          0     0  50000
          gsbi2_uart_clk              0        0        0    25000000          0     0  50000
       gsbi1_uart_src                 0        0        0    25000000          0     0  50000
          gsbi1_uart_clk              0        0        0    25000000          0     0  50000
       gsbi7_qup_src                  0        0        0    25000000          0     0  50000
          gsbi7_qup_clk               0        0        0    25000000          0     0  50000
       gsbi6_qup_src                  0        0        0    25000000          0     0  50000
          gsbi6_qup_clk               0        0        0    25000000          0     0  50000
       gsbi2_qup_src                  0        0        0    25000000          0     0  50000
          gsbi2_qup_clk               0        0        0    25000000          0     0  50000
       usb_fs1_xcvr_src               0        0        0    25000000          0     0  50000
          usb_fs1_sys_clk             0        0        0    25000000          0     0  50000
          usb_fs1_xcvr_clk            0        0        0    25000000          0     0  50000
       usb_hs1_xcvr_src               0        0        0    25000000          0     0  50000
          usb_hs1_xcvr_clk            0        0        0    25000000          0     0  50000
       sdc3_src                       0        0        0    25000000          0     0  50000
          sdc3_clk                    0        0        0    25000000          0     0  50000
       sdc1_src                       0        0        0    25000000          0     0  50000
          sdc1_clk                    0        0        0    25000000          0     0  50000
       tsif_ref_src                   0        0        0    25000000          0     0  50000
          tsif_ref_clk                0        0        0    25000000          0     0  50000
 cxo_board                            0        0        0    25000000          0     0  50000
    cxo                               0        0        0    25000000          0     0  50000
 pll4_vote                            0        0        0           0          0     0  50000
2774

yes mine is 17d atm

1 Like
2775 
r7500v2 # uptime
 16:01:58 up 13 days,  5:37,  load average: 0.06, 0.07, 0.08

about an hour and half later, lost power due to an electrical disturbance.

HTH

2776

don't really know how an overclocked router is more stable than one with stock frequency
considering overclocking the production one with many device and see how it goes...
currently CACHE is at 1.7 ghz and cpu is at 1.9ghz
only cpu has more voltage than standard (notice some instability with 2.0 ghz)
cache is still at the max the regulator can give...
this is a joke really...

also temp doesn't seems to have increased a lot (1-2) and this actually gives some perf improvement (10-14%)... the benchmark is done using the cache benchmark

root@No-Lag-Router:~# uptime
 22:53:46 up 18 days,  2:43,  load average: 0.17, 0.13, 0.10

root@No-Lag-Router:~# cat /sys/devices/system/cpu/cpufreq/policy0/stats/trans_ta
ble
   From  :    To
         :    384000    600000    800000   1000000   1400000   1725000   1900000
   384000:         0         4         4         2         3         5         6
   600000:         2         0   2452893    676613         5         3    204314
   800000:         5   2446511         0    220131        10         4     75220
  1000000:         4    636308    215724         0        13        40     81526
  1400000:         4         6         3        30         0         8        26
  1725000:         4         3         5        24        17         0        30
  1900000:         5    250999     73251     36815        29        23         0
2 Likes
2777

Btw. I've just stumbled over a patch submitted upstream, which might speed up routing on ipq806x a bit.

https://lkml.kernel.org/r/20210614022504.24458-1-mcroce@linux.microsoft.com

Disclaimer: I've not tested it yet and am currently not in a position to do so (only remote access to my nbg6817, and I'm not allowed to potentially brick it while being absent), but it would be interesting if anyone on a highspeed internet connection (who's not using NSS based builds) could give it a spin and do some throughput tests.

Scratch that, while it may indeed improve the throughput, it depends on XDP support, which was only just merged for kernel 5.13~ (while backporting that to v5.10 might be possible, it's a quite different task from merely testing an alignment fix).

2778

rip my uptime

Uptime	22d 3h 15m 12s

want to test some old patch about clk... fun times

1 Like
2779

Same here, DSA based build crashed yesterday.
It could be anything really. I think the kid was streaming some children's program over wired connection when it happend. No other activity that I know of, apart from light wifi traffic and other light ethernet traffic.

OpenWrt SNAPSHOT, r16897-04a260911c - Linux - 5.10.42

2780

@Ansuel
Still a newbie with openwrt and my r7800 but want to help as much as possible.
I also tried the command of @anon98444528 and saw some differences.

root@router:~# /bin/cat /sys/kernel/debug/regulator/regulator_summary && /bin/cat /sys/kernel/debug/clk/clk_summary
 regulator                      use open bypass  opmode voltage current     min     max
---------------------------------------------------------------------------------------
 regulator-dummy                 10   13      0 unknown     0mV     0mA     0mV     0mV
    29000000.sata                 1                                 0mA     0mV     0mV
    29000000.sata                 1                                 0mA     0mV     0mV
    29000000.sata                 1                                 0mA     0mV     0mV
    1b700000.pci                  1                                 0mA     0mV     0mV
    1b700000.pci                  1                                 0mA     0mV     0mV
    1b700000.pci                  1                                 0mA     0mV     0mV
    1b500000.pci                  1                                 0mA     0mV     0mV
    1b500000.pci                  1                                 0mA     0mV     0mV
    1b500000.pci                  1                                 0mA     0mV     0mV
    s1a                           0    0      0 unknown  1050mV     0mA  1050mV  1150mV
    s1b                           0    1      0 unknown  1050mV     0mA  1050mV  1150mV
       3000000.nss-common         0                                 0mA     0mV     0mV
    s2a                           0    1      0 unknown   950mV     0mA   775mV  1275mV
       cpu0                       0                                 0mA   950mV  1050mV
    s2b                           0    1      0 unknown   950mV     0mA   775mV  1275mV
       cpu1                       0                                 0mA   950mV  1050mV
 SDCC Power                       1    0      0 unknown  3300mV     0mA  3300mV  3300mV
                                 enable  prepare  protect                                duty
   clock                          count    count    count        rate   accuracy phase  cycle
---------------------------------------------------------------------------------------------
 qsb                                  0        0        0           1          0     0  50000
 ebi2_always_on_clk                   1        1        0           0          0     0  50000
 ebi2_clk                             1        1        0           0          0     0  50000
 pcie2_phy_clk                        0        0        0           0          0     0  50000
 pcie2_h_clk                          0        0        0           0          0     0  50000
 pcie2_aux_clk                        0        0        0           0          0     0  50000
 pcie2_a_clk                          0        0        0           0          0     0  50000
 pcie1_phy_clk                        1        1        0           0          0     0  50000
 pcie1_h_clk                          1        1        0           0          0     0  50000
 pcie1_aux_clk                        1        1        0           0          0     0  50000
 pcie1_a_clk                          1        1        0           0          0     0  50000
 sata_phy_cfg_clk                     1        1        0           0          0     0  50000
 sata_a_clk                           1        1        0           0          0     0  50000
 sata_h_clk                           1        1        0           0          0     0  50000
 gsbi7_h_clk                          0        0        0           0          0     0  50000
 gsbi6_h_clk                          0        0        0           0          0     0  50000
 gsbi5_h_clk                          0        0        0           0          0     0  50000
 gsbi4_h_clk                          4        4        0           0          0     0  50000
 gsbi2_h_clk                          0        0        0           0          0     0  50000
 gsbi1_h_clk                          0        0        0           0          0     0  50000
 usb_fs1_h_clk                        0        0        0           0          0     0  50000
 usb_hs1_h_clk                        0        0        0           0          0     0  50000
 sdc3_h_clk                           1        1        0           0          0     0  50000
 sdc1_h_clk                           1        1        0           0          0     0  50000
 pmic_ssbi2_clk                       0        0        0           0          0     0  50000
 pmic_arb1_h_clk                      0        0        0           0          0     0  50000
 pmic_arb0_h_clk                      0        0        0           0          0     0  50000
 rpm_msg_ram_h_clk                    1        1        0           0          0     0  50000
 tsif_h_clk                           0        0        0           0          0     0  50000
 dma_bam_h_clk                        0        0        0           0          0     0  50000
 pmem_clk                             0        0        0           0          0     0  50000
 sfab_sata_s_h_clk                    1        1        0           0          0     0  50000
 pcie_phy_clk                         1        1        0           0          0     0  50000
 pcie_h_clk                           1        1        0           0          0     0  50000
 pcie_aux_clk                         1        1        0           0          0     0  50000
 pcie_a_clk                           1        1        0           0          0     0  50000
 adm0_pbus_clk                        1        1        0           0          0     0  50000
 adm0_clk                             1        1        0           0          0     0  50000
 sleep_clk                            1        1        0       32768          0     0  50000
 pxo_board                            5        5        1    25000000          0     0  50000
    nss_fabric_1_a_clk                0        0        0  2147483647          0     0  50000
    nss_fabric_1_clk                  1        1        0   266500000          0     0  50000
    nss_fabric_0_a_clk                0        0        0  2147483647          0     0  50000
    nss_fabric_0_clk                  1        1        0   533000000          0     0  50000
    sfpb_a_clk                        0        0        0  2147483647          0     0  50000
    sfpb_clk                          0        0        0  2147483647          0     0  50000
    sfab_a_clk                        0        0        0  2147483647          0     0  50000
    sfab_clk                          0        0        0  2147483647          0     0  50000
    ebi1_a_clk                        1        1        0   533000000          0     0  50000
    ebi1_clk                          0        0        0  2147483647          0     0  50000
    daytona_a_clk                     0        0        0  2147483647          0     0  50000
    daytona_clk                       0        0        0  2147483647          0     0  50000
    cfpb_a_clk                        0        0        0  2147483647          0     0  50000
    cfpb_clk                          0        0        0  2147483647          0     0  50000
    afab_a_clk                        1        1        0   533000000          0     0  50000
    afab_clk                          0        0        0  2147483647          0     0  50000
    pxo                               6        6        3    25000000          0     0  50000
       pcie2_ref_src                  0        0        0    25000000          0     0  50000
          pcie2_ref_src_clk           0        0        0    25000000          0     0  50000
       pll18                          1        1        0   800000000          0     0  50000
          nss_core_clk                1        1        0   800000000          0     0  50000
          ubi32_core2_src_clk         0        0        0   800000000          0     0  50000
          ubi32_core1_src_clk         0        0        0   800000000          0     0  50000
       pll14                          0        0        0           0          0     0  50000
          pll14_vote                  0        0        0           0          0     0  50000
       hfpll_l2                       0        0        0           0          0     0  50000
          hfpll_l2_div                0        0        0           0          0     0  50000
       pll11                          0        0        0  1066000000          0     0  50000
       hfpll1                         1        1        0   800000000          0     0  50000
          krait1_pri_mux              1        1        0   800000000          0     0  50000
          hfpll1_div                  0        0        0   400000000          0     0  50000
       hfpll0                         1        1        0  1725000000          0     0  50000
          krait0_pri_mux              1        1        0  1725000000          0     0  50000
          hfpll0_div                  0        0        0   862500000          0     0  50000
       pll8                           1        1        1   384000000          0     0  50000
          pll8_vote                   3        3        1   384000000          0     0  50000
             usb30_utmi_clk           2        2        2    60000000          0     0  50000
                usb30_1_utmi_clk_ctl       1        1        0    60000000          0     0  50000
                usb30_0_utmi_clk_ctl       1        1        0    60000000          0     0  50000
             acpu1_aux                0        0        0   384000000          0     0  50000
                krait1_sec_mux        0        0        0   384000000          0     0  50000
             acpu_l2_aux              1        1        0   384000000          0     0  50000
                krait_l2_sec_mux       1        1        0   384000000          0     0  50000
                   krait_l2_pri_mux       2        2        0   384000000          0     0  50000
             acpu0_aux                0        0        0   384000000          0     0  50000
                krait0_sec_mux        0        0        0   384000000          0     0  50000
             gsbi1_qup_src            0        0        0    25600000          0     0  50000
                gsbi1_qup_clk         0        0        0    25600000          0     0  50000
             gsbi4_qup_src            0        0        0    24000000          0     0  50000
                gsbi4_qup_clk         0        0        0    24000000          0     0  50000
             gsbi5_qup_src            0        0        0    48000000          0     0  50000
                gsbi5_qup_clk         0        0        0    48000000          0     0  50000
             gsbi4_uart_src           1        1        0     1843200          0     0  50000
                gsbi4_uart_clk        3        3        0     1843200          0     0  50000
             prng_src                 0        0        0    32000000          0     0  50000
                prng_clk              0        0        0    32000000          0     0  50000
       pll3                           4        4        3  1200000000          0     0  50000
          sata_ref_src                2        2        2   100000000          0     0  50000
             sata_pmalive_clk         1        1        0   100000000          0     0  50000
             sata_rxoob_clk           1        1        0   100000000          0     0  50000
          pcie1_ref_src               1        1        1   100000000          0     0  50000
             pcie1_ref_src_clk        1        1        0   100000000          0     0  50000
          pcie_ref_src                1        1        1   100000000          0     0  50000
             pcie_ref_src_clk         1        1        0   100000000          0     0  50000
          ce5_core_src                1        1        0   150000000          0     0  50000
             ce5_core_clk             1        1        0   150000000          0     0  50000
       pll0                           1        1        1   800000000          0     0  50000
          pll0_vote                   4        4        1   800000000          0     0  50000
             nss_tcm_src              2        2        0   400000000          0     0  50000
                nss_tcm_clk           1        1        0   400000000          0     0  50000
             usb30_master_ref_src       2        2        2   125000000          0     0  50000
                usb30_1_branch_clk       2        2        0   125000000          0     0  50000
                usb30_0_branch_clk       2        2        0   125000000          0     0  50000
             ce5_h_clk_src            1        1        0   160000000          0     0  50000
                ce5_h_clk             1        1        0   160000000          0     0  50000
             ce5_a_clk_src            1        1        0   160000000          0     0  50000
                ce5_a_clk             1        1        0   160000000          0     0  50000
             gmac_core4_src           0        0        0   266666666          0     0  50000
                gmac_core4_clk        0        0        0   266666666          0     0  50000
             gmac_core3_src           0        0        0   266666666          0     0  50000
                gmac_core3_clk        0        0        0   266666666          0     0  50000
             gmac_core2_src           0        0        0   266666666          0     0  50000
                gmac_core2_clk        0        0        0   266666666          0     0  50000
             gmac_core1_src           0        0        0   266666666          0     0  50000
                gmac_core1_clk        0        0        0   266666666          0     0  50000
       gp2_src                        0        0        0    25000000          0     0  50000
          gp2_clk                     0        0        0    25000000          0     0  50000
       gp1_src                        0        0        0    25000000          0     0  50000
          gp1_clk                     0        0        0    25000000          0     0  50000
       gp0_src                        0        0        0    25000000          0     0  50000
          gp0_clk                     0        0        0    25000000          0     0  50000
       sata_phy_ref_clk               0        0        0    25000000          0     0  50000
       gsbi7_uart_src                 0        0        0    25000000          0     0  50000
          gsbi7_uart_clk              0        0        0    25000000          0     0  50000
       gsbi6_uart_src                 0        0        0    25000000          0     0  50000
          gsbi6_uart_clk              0        0        0    25000000          0     0  50000
       gsbi5_uart_src                 0        0        0    25000000          0     0  50000
          gsbi5_uart_clk              0        0        0    25000000          0     0  50000
       gsbi2_uart_src                 0        0        0    25000000          0     0  50000
          gsbi2_uart_clk              0        0        0    25000000          0     0  50000
       gsbi1_uart_src                 0        0        0    25000000          0     0  50000
          gsbi1_uart_clk              0        0        0    25000000          0     0  50000
       gsbi7_qup_src                  0        0        0    25000000          0     0  50000
          gsbi7_qup_clk               0        0        0    25000000          0     0  50000
       gsbi6_qup_src                  0        0        0    25000000          0     0  50000
          gsbi6_qup_clk               0        0        0    25000000          0     0  50000
       gsbi2_qup_src                  0        0        0    25000000          0     0  50000
          gsbi2_qup_clk               0        0        0    25000000          0     0  50000
       usb_fs1_xcvr_src               0        0        0    25000000          0     0  50000
          usb_fs1_sys_clk             0        0        0    25000000          0     0  50000
          usb_fs1_xcvr_clk            0        0        0    25000000          0     0  50000
       usb_hs1_xcvr_src               0        0        0    25000000          0     0  50000
          usb_hs1_xcvr_clk            0        0        0    25000000          0     0  50000
       sdc3_src                       0        0        0    25000000          0     0  50000
          sdc3_clk                    0        0        0    25000000          0     0  50000
       sdc1_src                       0        0        0    25000000          0     0  50000
          sdc1_clk                    0        0        0    25000000          0     0  50000
       tsif_ref_src                   0        0        0    25000000          0     0  50000
          tsif_ref_clk                0        0        0    25000000          0     0  50000
 cxo_board                            0        0        0    25000000          0     0  50000
    cxo                               0        0        0    25000000          0     0  50000
 pll4_vote                            0        0        0           0          0     0  50000

Maybe it helps to find something.
Running kongs latest KONG 20 r16868-317920b3b6 / LuCI Master git-21.156.61451-516c58e
with Kernel 5.4.123

2781

Is there similar problem in kernel 5.10 with DSA? After enabling VLANs within build based on @hnyman 's test 5.10 one with DSA support none of clients connected over Ethernet can obtain DHCP address. It is also not possible to reach out to Ethernet connected clients from anything but OpenWrt device to which they are connected or from WiFi clients but only if associated with the same OpenWrt device.
With WiFi clients it can be especially observed while roaming:

From 10.0.0.50 icmp_seq=48 Destination Host Unreachable
From 10.0.0.50 icmp_seq=52 Destination Host Unreachable
From 10.0.0.50 icmp_seq=53 Destination Host Unreachable
From 10.0.0.50 icmp_seq=54 Destination Host Unreachable
64 bytes from 10.0.0.10: icmp_seq=55 ttl=64 time=1.94 ms
64 bytes from 10.0.0.10: icmp_seq=56 ttl=64 time=2.47 ms
64 bytes from 10.0.0.10: icmp_seq=57 ttl=64 time=2.27 ms
64 bytes from 10.0.0.10: icmp_seq=58 ttl=64 time=2.54 ms

For directly attached Ethernet clients the only option that works is manual IP config.

2782

Can someone test this? if you have a d7800 or r7500 or any other device that affects this pr

2783

Well, to me is looks like the PR removes the current MAC reading/patching for R7800 but does not add the corresponding DTS change. (D7800 and R7500v2 are added, but not R7800 :frowning: )

2784

R7800 should already use that? Or I miss that?

2785

Well, I have no idea if the new functionality has already existed (unused) for R7800, but at least you removed the old R7800 functionality here (along r7500v2 and d7800):

https://github.com/openwrt/openwrt/pull/3403/files#diff-0bcd5f788fb506cf320e03521ed1b9d9d59ffb14ef6a1bfbc622d65282b1734eL95-L100

I think that you missed the ipq8065-... DTS changes for R7800.

2786 
&pcie0 {
	status = "okay";

	bridge@0,0 {
		reg = <0x00000000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		ranges;

		wifi@1,0 {
			compatible = "pci168c,0046";
			reg = <0x00010000 0 0 0 0>;

			nvmem-cells = <&macaddr_art_6>;
			nvmem-cell-names = "mac-address";
			mac-address-increment = <(1)>;
		};
	};
};

&pcie1 {
	status = "okay";
	max-link-speed = <1>;

	bridge@0,0 {
		reg = <0x00000000 0 0 0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		ranges;

		wifi@1,0 {
			compatible = "pci168c,0046";
			reg = <0x00010000 0 0 0 0>;

			nvmem-cells = <&macaddr_art_6>;
			nvmem-cell-names = "mac-address";
			mac-address-increment = <(2)>;
		};
	};
};

i can see that r7800 already has the nvmem node. (i checked the repo based on that commit) But ath10k didn't have the required patch so the old hotplug script was still used to patch mac.
So the dts was fixed but we were still using the old implementation.

2787

My bad. Thanks for clarification.

Looks like the unused mac address things have been added already in 2019 by chunkeey and you with 1acc054341, although they have not been used since then.

https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=1acc054341d1e1163f329b54b28562d9724f12b7;hp=2da033eaa6dd6c124c5ca2f3b96f136bbb45ff6a

Ps. took me a while to figure out the correct commit, as the ipq806x dts git history is very confusing with the files-4.19, files-5.4, files dirs, and changes done gradually.

2788

yes that commit was a test by chunkeey to drop the hotplug script. Was done only with r7800 as it was his testing router.

2789

In that case, looks like R7800 would need no other changes than the removal of those two script lines. Looking the MAC addresses in devicetree (without any changes done), I see there the correct MAC of my router (eth0 MAC):

 OpenWrt SNAPSHOT, r17217-39f81b0bf6
 -----------------------------------------------------
root@router1:~# hexdump -C /proc/device-tree/soc/pci@1b500000/bridge@0,0/wifi@1,0/mac-address
00000000  dc ef 09 ef f3 e5                                 |......|
00000006
root@router1:~# hexdump -C /proc/device-tree/soc/pci@1b700000/bridge@0,0/wifi@1,0/mac-address
00000000  dc ef 09 ef f3 e5                                 |......|
00000006

I then removed the mac patch line from the hotplug script, removed the pre-cal firmware files from /overlay/upper/lib/firmware/ath10k, and rebooted.

After teh reboot, both wlan instances still show the correct MAC, so it seems to work for R7800.

wlan0     Link encap:Ethernet  HWaddr DC:EF:09:EF:F3:E6
          inet6 addr: fe80::deef:9ff:feef:f3e6/64 Scope:Link
...
wlan1     Link encap:Ethernet  HWaddr DC:EF:09:EF:F3:E7
          inet6 addr: fe80::deef:9ff:feef:f3e7/64 Scope:Link

(But I am not sure if I should compile a new firmware, so that the hotplug script in /rom would also be the modified one. Haven't though the boot sequence that far.)

1 Like
2790

AFAIK the hotplug script is run on every firmware load

Anyway i'm thinking about introducing one more patch for the ascii variant and one patch for ath to add support for extracting cal data also from nvmem...

Problem that I notice is that is a little slow... I should check if i can find a way to speed that up.
I mean at the very end should be the same... both function are reading from the mtd so i think it's just a problem of nvmem reading one byte at time
(but anyway i tested a patch that used nvmem to get the cal data and all worked correctly... only problem the load was too slow)

These 2 thing can in theory remove the need of the script completely

2791

I've been running 5.10 for quite some time, and it's still currently the testing kernel in the Makefile. Is there anything preventing it from being adopted as the default kernel version?

EDIT: Never mind, I see that the plan is to make 5.10 default once the DSA work has been finished. I probably should help out and give that PR a spin.

2792

Thx a lot. I think we are starting to reach a good point there. I think I still have some hack to fix.