I noticed a performance abnormally lower than expected on a Buffalo Linkstation LS421DE , equipped with a Marvel Armada 370 SoC. So I checked the CPU Sub-system Registers with devmem enabled in an Openwrt custom firmware, and it seems the Level 2 cache isn't enabled
root@OpenWrt:/# devmem 0xd0008100 0x00000000
According to the SoC datasheet this bit should be 1 when the L2 cache is enabled
To be sure, I also checked the bit running the stock firmware, and indeed it should be enabled:
[root@LS421DE7CC ~]# devmem 0xd0008100 0x00000001
To check the performance I made a simple test with wget in Openwrt compiled without netfilter/ipt modules and with the stock firmware:
Linux version 5.4.75 (dani@tool) (gcc version 8.4.0 (OpenWrt GCC 8.4.0 r0-c78e123)) #0 SMP Tue Nov 10 12:11:32 2020 root@OpenWrt:~# devmem 0xd0008100 0x00000000 root@OpenWrt:~# devmem 0xd0008104 0x12086300 root@OpenWrt:~# wget -O- http://192.168.1.7:8000/bigfile.bin > /dev/null --2020-11-10 04:48:08-- http://192.168.1.7:8000/bigfile.bin Connecting to 192.168.1.7:8000... connected. HTTP request sent, awaiting response... 200 OK Length: 2602501255 (2.4G) [application/octet-stream] Saving to: 'STDOUT' 100%[======================>] 2.42G 40.2MB/s in 58s 2020-11-10 04:49:06 (42.6 MB/s) - written to stdout [2602501255/2602501255] root@OpenWrt:~#
- Stock firmware
[root@LS421DE7CC ~]# cat /proc/version Linux version 3.3.4 (root@nasbuild) (gcc version 4.6.2 (Linaro GCC branch-4.6.2. Marvell GCC 201201-883.01c949de) ) #1 Tue Nov 19 11:22:20 JST 2019 [root@LS421DE7CC /]# devmem 0xd0008100 0x00000001 [root@LS421DE7CC /]# devmem 0xd0008104 0x12086302 [root@LS421DE7CC /]# wget -O- http://192.168.1.7:8000/bigfile.bin > /dev/null --2020-11-10 04:15:03-- http://192.168.1.7:8000/bigfile.bin Connecting to 192.168.1.7:8000... connected. HTTP request sent, awaiting response... 200 OK Length: 2602501255 (2.4G) [application/octet-stream] Saving to: `STDOUT' 100%[=========================================>] 2,602,501,255 83.3M/s in 30s 2020-11-10 04:15:33 (82.8 MB/s) - written to stdout [2602501255/2602501255]
As you can see the performance is almost half in Openwrt compared with the stock firmware, 42 MB/s vs 82 MB/s
I made more checkups, and all signs points to a disabled cache:
- Manually enabling the L2Enable bit with devmem makes nothing, the readback is always 0.
- I compiled Openwrt with the L2 cache completely disabled in the kernel, the performance is exactly the same, same boot up times and same speed with wget. Again I can't enable this bit.
- I can enable the L2Enable bit in Uboot with the command:
mw.l 0xd0008100 0x1 1
But again when Openwrt is loaded and running the bit is disabled.
- I can disable the bit in the stock firmware, as expected it locks the system.
- I never got a system lockup while manipulating the cache registers in Openwrt, this indicates the cache isn't enabled.
The Openwrt bootlog https://pastebin.com/YVBvEAXH says:
[ 0.000000] Aurora cache controller enabled, 4 ways, 256 kB
[ 0.000000] Aurora: CACHE_ID 0x00000100, AUX_CTRL 0x12086302
But no apparent cache is working. L2Enable equals to 0 and low performance.
It would be nice if someone could check this bit in his Marvell Armada based device.:
- Ie WRT19000 or WRT3200AC, where the registers are mapped into a different address, so the command should be:
devmem 0xf1008100 devmem 0xf1008104
Any Idea on what's going on with the cache?