I've noticed in the kernel early bootlog a new line when I compiled the kernel in THUMB2 mode for the Buffalo LS421DE :
[ 0.000000] CPU: div instructions available: patching division code
Then I checked the cpuinfo:
root@LinkStation:~# cat /proc/cpuinfo processor : 0 model name : ARMv7 Processor rev 1 (v7l) BogoMIPS : 37.50 Features : half thumb fastmult vfp edsp vfpv3 vfpv3d16 tls idivt CPU implementer : 0x56 CPU architecture: 7 CPU variant : 0x1 CPU part : 0x581 CPU revision : 1 Hardware : Marvell Armada 370/XP (Device Tree) Revision : 0000 Serial : 0000000000000000
And indeed the idivt is there.
The message comes from the kernel option:
... which is configured in:
One may expect having idiva if thumb2 mode isn't enabled, but it isn't the case. Without THUMB2 mode it seems there is no idiv instruction available. This hardware capability is checked here:
I checked the cpuinfo in WRT3200ACM with a more modern CPU and higher capabilities:
root@OpenWrt:~# cat /proc/cpuinfo processor : 0 model name : ARMv7 Processor rev 1 (v7l) BogoMIPS : 1866.00 Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpd32 CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x4 CPU part : 0xc09 CPU revision : 1
Again no idiv instruction available.
As I posted elsewhere, when I compile the kernel in THUMB2 mode, the throughput is noticeably better (tested with the Armada370 SoC). Is the idiv extra instruction the culprit of this extra performance and not the THUMB2 mode?... or maybe both. AFAIK THUMB2 mode gives a similar performance compared with ARM mode.
BTW it seems the kernel option CONFIG_ARM_PATCH_IDIV is useless at least in the CORTEX A9 subtarget, since there is no idiv instruction available for the current kernel config and the hardware lacks idiva instruction (or at least it isn't detected by the setup).