MT7621 ECC correction in bootloader from the start

I suppose you are dealing with parallel NAND connected to MT7621AT (not SPI-NAND for which there is only very limited support), right?

According to the datasheet boot mode and NAND page layout is setup by bootstrap pins (RTS2, RTS3, TXD1, GPIO0) and supported layouts are 2k+64, 2k+128, 4k+128 and 4k+224.

There may also be more secrets in the not fully documented NAND boot header stored at the beginning of the flash:

/* AP BROM Header for NAND */
union nand_boot_header {
        struct {
                char name[12];
                char version[4];
                char id[8];
                uint16_t ioif;                  /* I/O interface */
                uint16_t pagesize;              /* NAND page size */
                uint16_t addrcycles;            /* Address cycles */
                uint16_t oobsize;               /* NAND page spare size */
                uint16_t pages_of_block;        /* Pages of one block */
                uint16_t numblocks;             /* Total blocks of NAND chip */
                uint16_t writesize_shift;
                uint16_t erasesize_shift;
                uint8_t dummy[60];
                uint8_t ecc_parity[28];         /* ECC parity of this header */
        };

        uint8_t data[0x80];
};

/* NAND header for SPI-NAND with 2KB page + 64B spare */
static const union nand_boot_header snand_hdr_2k_64_data = {
        .data = {
                0x42, 0x4F, 0x4F, 0x54, 0x4C, 0x4F, 0x41, 0x44,
                0x45, 0x52, 0x21, 0x00, 0x56, 0x30, 0x30, 0x36,
                0x4E, 0x46, 0x49, 0x49, 0x4E, 0x46, 0x4F, 0x00,
                0x00, 0x00, 0x00, 0x08, 0x03, 0x00, 0x40, 0x00,
                0x40, 0x00, 0x00, 0x08, 0x10, 0x00, 0x16, 0x00,
                0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                0x00, 0x00, 0x00, 0x00, 0x7B, 0xC4, 0x17, 0x9D,
                0xCA, 0x42, 0x90, 0xD0, 0x98, 0xD0, 0xE0, 0xF7,
                0xDB, 0xCD, 0x16, 0xF6, 0x03, 0x73, 0xD2, 0xB8,
                0x93, 0xB2, 0x56, 0x5A, 0x84, 0x6E, 0x00, 0x00
        }
};

So comparing the actual header of the two devices and understanding each bit can help as well.

Also, I suppose you are aware that MediaTek SoC's use a vendor-specific BCH scheme rather than simple 1-bit ECC. Some details about that have previously been discussed here: