they are 1K (direct measure on resistor) and seems like they are connected to LEDs (measured between soldered JTAG point and positive LED pole got 1K again)
JTAG interface has 200ohms on all lines. LEDs on LAN2 and LAN4 turn on almost each time, but sometimes no LED turns on, only a quick short blink on all ports when switched router on. this behaviour is present regardless of JTAG interface connected or not
Hmm 5/6 voltage divider is pretty low I hope leds won't do a high load on programmer and SoC drivers. JTAG 200 is fine, just connect it directly on SoC side. LEDs blinking may be sort of random if the firmware is damaged.
Now connect a voltmeter on TRST_n pin a try to find that bootstraping pin. You won't get JTAG mode until there is "0" (through that resistor). BTW a "0" there doesn't still mean you have JTAG, but "1" there does definitelly mean you don't have JTAG. If you already know a way how to kill off the boot from the NAND chip, apply it:
datasheet says 3.3V NAND and measuring CE (CS) pin it gives 3.10V on power-on so it isn't even enabled for some reason (bad block info lost on erase or who knows what..)
if I understand correctly TRST_n should have low resistance to bootstraping pin?
You cannot know, read the SoC part of initiation code from NAND-flash or not - if you probe that pin only multimeter(it can switch those pins with high speed, it is measured in milliseconds and multimeter does not catch the change a state of pin during this time) - only oscillograph can show true story.
Therefore, it is better to terminate any possible read data from NAND-flash.
If the vcc is full 3.3V (higher than 3.1V on #CE) it could mean the #CE is down (active) only a fraction of the time (the CPU can rest of the time read data from cache). I suppose a hard "1" will disable it (there shouldn't be enough high overload to break SoC's driver).
No that sentence doesn't make a sense. There are two pins TRST_n and bootstrapping (ANT_something). TRST_n must je input (no connection/high impedance), and then the external resistor on PCB will supply a weak GND on it (you can use it as indication if you've got JTAG mode). After you got the JTAG mode, TRST_n may be or may be not used by programmer to reset JTAG interface (cannot tell, this signal is optional a usually there is an equivalent JTAG command to reset).
@psyborg
I have a quesion:
Well, let's say you successfully connect the JTAG.
How will you flash NAND-flash?
Or you need a NAND driver specifically for MT7620(if you will use
OpenOCD).
Or As an option, you can use a U-boot RAM version (with NAND support).
Are you have GPL for yor device with bootloader?
GPL seems to not contain u-boot sources, but any other u-boot source for MT7620 board with NAND should be enough to build RAM-loadable image. fw on cable is urjtag compatible not for openocd
When pulled ANT_TRN to 3.3V I do notice TRST stays at low for 1-2 sec longer on poweron. But still returns to 3.20V (it is not 3.40, other pins are 3.40V)
Seems good. The remaining firmware probably disables that mode, you need to disable the NAND chip now.
BTW When you will get JTAG detected. Don't forget to make at least 3 copies of the NAND chip before any writes. The copies must match.
this seems more likely to be just the opposite case, at least with tp-link i had to short CS pin to GND. maybe it was the reason of unsuccessful jtag on this device.