Mixed tagged/untagged VLAN possible?

Hi to all

i have Mikrotik as my main router and dozen of openwrt device acting as AP/SWITCH

MAIN (untagged) lan is
GUEST (tagged) VLAN2 is
MGMNT (tagged) VLAN is 192,168,254,0/24

ok, everything working fine
on openwrt, the trunk port is on WAN side, software VLAN driver
so i have
eth1, eth1.2 and eth1.254

two SSID is bridged with lan MAIN, and lan GUEST
this set up working as expected

if i need wired access to some device behind AP i could easy assign MAIN,GUEST or MGMNT vlan to switch in access (untagged) mode

but, i have a situation where i need to "extend" my trunk port
so i like to pass whole trunk port to another device

i tried to setup outgoing port to have
MAIN untagged
GUEST tagged
MGMNT tagged

but builtin switch make all packet tagged
tried to set PVID by hand but no success

device: TP-LINK wr841nd v9
switch0: eth0(AR934X built-in switch)

tried with OpenWrt 15.05 and 18.06.x

so, my question: it is possible to mix tagged/untagged traffic on one port?

i have success with Mikrotik and TP-Link Jetsream switches, but could not make it on OpenWrt


Hello new member :slight_smile:

I own this device too and until now I've no success to use a port for untagged and tagged vlans concurrently...
It works for only multiple tagged or only a single untagged vlan.

All my other devices with external (non soc integrated, like on tp link wr1043 v2) switches do work with concurrent tagged and untagged vlans.

So seems that the integrated soc switches, or more precisely the used driver, doesn't support concurrent tagged and untagged vlans on the same port.

Hi @juppin

thank you for your reply

i see you have many posts on this forum, so i (sadly) need to accept this fact that some device could not work with mixed tagged/untagged VLAN's

While I never run untagged on a trunk myself, I have run into the switch-driver limitation of the VLAN table at 128 or less. To run higher number VLANs, you need to specify vid for the tag. As I recall, the PVID is specified by table-entry number, not using the tag itself.

Hi @jeff

tnx for reply

even if i left out Vlan254 and try to pass only
main untagged
and guest tagged

swconfig show both are tagged.
playing with PVID has no success

root@WR_test:~# swconfig dev eth0 vlan 1 set ports '0t 1 2 3 4'
root@WR_test:~# swconfig dev eth0 vlan 2 set ports '0t 1t'
root@WR_test:~# swconfig dev eth0 set apply
root@WR_test:~# swconfig dev eth0 show

        vid: 1
        ports: 0t 1t 2 3 4 
        vid: 2
        ports: 0t 1t 

as you could see, vlan1 have "T" letter


1 Like

You could try if it works with the new ath79 target...
I haven't tried vlans with 841v9 on ath79 by myself.


The ath79 target does use the same switch driver for the soc integrated switch as the external atheros/qualcomm switches...
On ar71xx there was a extra driver for the soc integrated switches!

Take a look into the following commits if you are interested in the changes for ath79:

Hi @juppin

tnx again

i tried snapshot build link you send, and no, still the same
i see there is lot of improvement in switch config like MIB counters and learned MAC addresses, but god damn T flag is still there
it is no matter whatever PVID i try

tnx again for your time

swconfig dev mdio-bus.0:1f show
Global attributes:
        enable_vlan: 1
        ar8xxx_mib_poll_interval: 500
        ar8xxx_mib_type: 0
        enable_mirror_rx: 0
        enable_mirror_tx: 0
        mirror_monitor_port: 0
        mirror_source_port: 0
        arl_table: address resolution table
Port 0: MAC 00:02:a5:4b:e8:b8
Port 0: MAC e8:94:f6:c0:26:e6
Port 0: MAC 18:03:73:9d:9e:c6
Port 0: MAC 64:d1:54:28:01:4f
Port 0: MAC 94:b8:6d:7a:90:d6
Port 0: MAC 00:0e:08:c1:a3:cf
Port 0: MAC 64:d1:54:28:01:46
Port 0: MAC 00:1a:4b:22:90:80
Port 1: MAC 64:d1:54:9a:51:3c

Port 0:
        mib: MIB counters
RxGoodByte  : 115710 (112.9 KiB)
TxByte      : 30782 (30.0 KiB)

        pvid: 0
        link: port:0 link:up speed:1000baseT full-duplex txflow rxflow 
Port 1:
        mib: MIB counters
RxGoodByte  : 30426 (29.7 KiB)
TxByte      : 82415 (80.4 KiB)

        pvid: 1
        link: port:1 link:up speed:100baseT full-duplex auto
Port 2:
        mib: No MIB data
        pvid: 1
        link: port:2 link:down
Port 3:
        mib: No MIB data
        pvid: 1
        link: port:3 link:down
Port 4:
        mib: No MIB data
        pvid: 1
        link: port:4 link:down
        vid: 1
        ports: 0t 1t 2 3 4 
        vid: 2
        ports: 0t 1t 
1 Like

Would be interesting why this issue happens on the soc integrated atheros / qualcomm switches...

If you are motivated to dig deeper into this issue here are some datasheets of the atheros / qualcomm chipsets: